INL and DNL

INL and DNL show the non-linearity performance of pipelined ADC. Figure 5.8 (a) is before calibration, because gain error of opamp, DNL has missing code and INL is about

±3LSB. After calibration, Figure 5.8(b), the missing code in DNL is disappeared and INL is

improved to be less than ±0.5LSB, obviously. The LSB is 9bit resolution to full scale input.

(a)

(b)

Figure 5.8 INL and DNL

(a) Before calibration (b) After calibration 5.2.4 Dynamic Range

Figure 5.9 shows the dynamic range simulation result. Two curves with and without calibration are almost the same while input signal level is low. While input level becomes higher, the two lines will separate because gain error dominates in lower line. The dynamic range shown in figure is about 60dB.

Figure 5.9 Dynamic range 5.2.5 Specification Table

Table 5.1 shows the performance summary simulated in 0.18μm CMOS process. The conversion rate is 80MS/s and resolution is 9bit. In post-simulation, the ENOB is 8.76bit and 8.69bit at input frequency is 8MHz and 40MHz, respectively. The total power added by ADC core, clock generator, and calibration circuit is 11.5mW. The FOM is defined as

2^ENOB

Power

FOM = Conversion rate

× (5.1)

In this design, the FOM is 0.40pJ/Setp at input frequency is 40MHz and 0.35pJ/Setp at input frequency is 8MHz at post-simulation.

Table 5.1 ADC specification of pre-simulation and post-simulation

Figure 5.10 depicts the measurement setup used to assess the performance of the experimental low voltage pipelined ADC described in this work. The supply voltages for both analog and digital parts to the board are generated by the power supply. In order to prevent the digital noise coupling to the analog circuits, analog and digital powers are isolated to each other in the PCB board. The input signal is provided by a high performance signal generator, Agilent E4438C and system clock is supplied by pulse generator, Agilent 8133A. Otherwise, the output bit streams are fed to the logic analyzer, Agilent 16700. The digital data stored in the logic analyzer is subsequently download to a personal computer and processed by

MATLAB, including of calibration and FFT analysis.

Figure 5.10 Measurement consideration 5.3.2 Experimental Result

Figure 5.11 shows the chip microphotograph of the fabricated ADC. The chip dimensions are 1.45×1.55 mm² and the active area is 0.85×0.9 mm². Operating at a 40MS/s sampling rate under 1.8 and 1V power supplies, the total analog circuit consumes a total of 7.3mW and digital circuit consumes 4.2mW.

Pipelined ADC

Calibration Circiut

Figure 5.11 ADC chip microphotograph

Figure 5.12 shows the measured calibration circuit output. Figure 5.12(a) is at transient state and Figure 5.12(b) averages the outputs by 512 samples to suppress the noise. The value 49.78 is close to the post-simulation result.

(a) (b) Figure 5.12 The measured calibration circuit output

Figure 5.13 shows the ADC’s differential nonlinearity (DNL) and integral nonlinearity (INL) characteristics obtained from code-density measurements. The LSB is normalized to 9bit resolution in those figures. The number of registered output code is 16384. Figure 5.12 shows the ADC’s native DNL and INL before activating the off-line calibration. The DNL is +1.2/-0.8 LSB and INL is +4/-4 LSB. Figure 5.14 shows the ADC’s DNL and INL after calibration is activated. The DNL is +1.1/-0.8LSB, and the INL is reduced to +1.3/-1.3 LSB.

Figure 5.13 Measured DNL and INL at 80MS/s with calibration off.

Figure 5.14 th calibration on.

Figure 5.15 shows the ADC’ FFT) spectra at a 80MS/s

sampling rate. The input is dif Without calibration,

the third-order harm , which is -46.4dB below the

fundamental signal. The signa ratio (SNDR) is 42.3dB and the

spurious-free dynami NDR is ferential 600mVPP 1MHz sinusoidal signal.

onic is the dominant distortion term l-to-distortion-plus-noise

c range (SFDR) is 46.4dB. After calibration is activated, the S proved by 42.3dB to 46dB and the SFDR is improved by 46.4dB to 54.7dB. Notably

ing error remain almost the same before and after calibration. The mprovement after calibration comes from the elimination of harmonic tones.

Figure 5.16 shows the ADC’s measured SNDR and SFDR versus input frequencies at a 80HS/s sampling rate. The SNDR and SFDR decrease up to the Nyquist frequency because of aperture jitter dominating the performance. Generally, the calibration can improve the SNDR by 4dB and the SFDR by 10dB at low input frequency. Figure 5.17 shows the ADC’s SNDR versus input signal level with calibration on and off respectively. The 1MHz input is sampled at 80MS/s. The figure 5.17 reveals that the measured dynamic range is 52dB. The figure 5.18 shows the measured ENOB versus sampling frequencies at a 1MHz sinusoidal signal. With pling rate above 80MS/s, the performance deceases below 7 bit after calibration is activated.

The 600mVPP led at 80 MS/s.

Figure 5.15 Measured output FFT spectra.

1MHz differential sinusoidal input is samp

Figure 5.16 Measured SFDR,SNDR, and ENOB versus sinusoidal input is sampled at 80 MS/s.

Figure 5.17 Measured SNDR and SNR versus input level. The 1MHz differential sinusoidal input is sampled at 80 MS/s

Figure 5.18 Measured SNDR and differential sinusoidal input is sampled at 80 MS/s

SNR versus input level. The 1MHz

C HAPTER 6 C ONCLUSION

Table 6.1 summarizes the measured performance of the ADC prototype at room perature. The power supplies are 1.8V and 1V. With calibration on, the SNDR is 46.0dB

pling rate is 80MS/s and input frequency is 1MHz. The FOM r references shown in table I, the performance is 4 times ss than [4] and [7] but is similar to reference [1] under the same technology.

Table 6.1 Performance summary of ADC at room temperature tem

ISSCC[7] ISSCC[1] ISSCC[4] Simulation Measurement

Technology 90nm 0.18μm 90nm 0.18μm 0.18μm

Supply Voltage 0.8V 1.8V 1V 1.8V,1V 1.8V,1V

Resolution 10bit 10bit 10bit 9bit 9bit

Conversion Rate 80MS/s 125MS/s 30MS/s 80MS/s 80MS/s

SNDR 55dB 53.7dB 58.4dB 54.1dB 46.0dB

ENOB 8.8bit 8.6bit 9.4bit 8.69bit 7.35bit

Signal Swing +/-600mV - +/-500mV +/-300mV +/-300mV

Power

The low power 9bit, 80MS/s pipelined ADC was fabricated using a 0.18μm 1P6M CMOS technology, and occupied an area of 1.45×1.55mm². The techniques implemented in this design are summarized below:

(1) FADAC replaces the front-end sample and hold can save power and achieve higher accuracy of ADC by 1bit.

(2) Opamp scaling in last 2 stages is for power saving.

(3) A novel 1V OP with split Gm stage for gain enhancement by abo

(4) Double edge sampling operation doubles the conversion rate and m utilization of opamp.

SFDR of 54dB and an SNDR of 46dB. The

and SNDR by 4dB. y ity , tim en

two uplin s. T um ling r

op re ji minates the perfor e whil t frequen gh.

ev O pJ pling rate and 1MHz

sinusoidal input with 1. V p ppl cal di nonlinea

integra arity (IN +1.1 B an /-1.3L ctively.

ve 10dB.

akes efficient

(5) Improving accuracy of calibration circuit by chopper averaging and input offset cancellation.

(6) With calibration on, INL improved by 3X and ENOB improve by 0.6 bits (2 bits by simulation).

The total ADC consumes 11.5mW under 1.8V and 1V power supplies. It achieves an calibration circuit can improve SFDR by 10dB The SNDR is limited b non-linear opamp gain ing error betwe paths and co g noise he maxim samp ate is limited by the speed of the

amps. The apertu tter do manc e the inpu cy goes hi

The ADC achi ed good F M of 0.88 /conversion at 80MS/s sam

8 and 1 ower su ies. Typi fferential rity (DNL) and l nonline L) are /-0.8LS d +1.3 SB, respe

ENCE

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