This thesis is organized into six chapters. In Chapter 1, this thesis is briefly introduced.
Chapter 2 begins with the concepts of analog-to-digital conversion and performance metrics used to characterize ADCs. Then, the architecture of pipelined ADC is reviewed. The pipelined architecture is described in detail from its basic operation to the actual implementation of each pipelined stage. The 1.5-bit architecture with accuracy and speed requirement are pointed out. The affection of gain error in low voltage ADC and calibration
technique are also discussed in detail. Finally, the behavioral level simulations of a pipelined ADC are built by MATLAB so as to obtain the specification of design.
Chapter 3 describes the design issues of each block. The key circuit blocks used in the low-voltage ADC is presented. Among them are the proposed operational amplifier, the dynamic common mode feedback, the comparator, the FADAC and the clock generator. Then, transistor level simulated results of each circuit are shown.
Chapter 4 describes the calibration circuit which is constructed by SAR (Successive Approximation) architecture. The goal is to calculate the gain error in pipelined ADC which is described in chapter 3. By the output digital code, off-line calibration can boost the efficiency of pipelined ADC.
Chapter 5 shows the experimental results, including the chip layout, system simulation result, and measurement consideration. Following the experimental test results for the low-voltage pipelined ADC described in Chapter 3 and Chapter 4 and fabricated in a standard TSMC 0.18μm CMOS technology are summarized.
The conclusions of this work are summarized in Chapter 6. Following additional areas of researches are suggested and recommendations for the future work.
C HAPTER 2 N YQUIST R ATE D ATA C ONVERTER
2.1 Introduction
In this chapter, the first describes the concept of analog to digital conversions and discusses performance metrics to characterize ADCs. The second reviews some analog-to-digital converter (ADC) architectures, including flash ADC, cyclic ADC, and pipelined ADC. The fundamental issues in this design will be reviewed. Among them we focus on Nyquist rate pipelined ADC architecture. The third focuses on key building blocks in pipelined analog-to-digital converters. The specification of constraints and several techniques including of double sampling and power optimization are discussed. At the end of the chapter, the behavior model of pipelined analog-to-digital converter is built by MATLAB.
2.2 ADC Performance Metrics
The ADC converts the analog signal to digital domain. The ADC divides the continuous analog signal into several subranges. The size of each of the subranges is often referred to as the step size. These steps are usually uniform in size, but not always. During the conversion process, the ADC decides the input signal level in which subrange and sends the appropriate digital code to the output. Analog-to-digital converters are characterized in a number of different ways to indicate the performance efficiency, including resolution, SNR, SNDR, dynamic range, INL and DNL.
2.2.1 Resolution
Resolution describes the fineness of the quantization performed by the ADC. It is also named as effective number of bits (ENOB). A high resolution ADC means the input range can
be divided into a larger number of subranges than a low resolution ADC. In general cases, resolution is defined as the base 2 logarithm of subranges, and is usually affected by either noise or nonlinearity. Therefore, SNR, INL and DNL are applied to characterize the performance in noise and nonlinearity.
2.2.2 Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio of signal power to noise power in the output of the ADC. In Figure 2.1(a), the transfer characteristic curve is shown. The use of quantization introduces an error, quantization error, defined as the difference between the dash line and the output signal. Figure 2.1(b) shows the quantization error range is between +Δ and –Δ.
Figure 2.1 (a) Transfer characteristic curve (b) Quantization error
As figure 2.2(a) shows, the quantizer can be model as input signal added by quantization error. The symbol Δ presents the value of 1LSB. By assumption, the quantization
error is defined as a uniformly distributed random variable and the interfering effect on the quantizer input is similar to that of thermal noise. The probability density function for such an error signal will be a constant value and is independent of the sampling frequency, fS, and input signal, as the Figure 2.2(b) shows. The distribution of the quantization error is expressed as Equation (2.1).
(b) The probability density function of the quantization error
1,
Hence, the R.M.S. value of the quantization error is
1 2 The SNR formula is to assume that VIN is a sinusoidal waveform between –VSwing and VSwing. Thus, the AC R.M.S. value of the sinusoidal wave is
, 2
Swing IN rms
V =V (2.3)
Let N denote the number of bits used in the construction of the binary code. The ΔLSB has a relationship with Vref. Then, the SNR can be derived
,
By equation (2.5), the simple equation shows the relation between SNR and ADC output bit number. As N increases by one, the SNR specification is added 6dB. For example, 8bit ADC requires at least 50dB. Besides, note that Equation (2.5) gives the best possible SNR for an N-bit ADC.
2.2.3 Spurious Free Dynamic Range (SFDR) and Signal to Noise Distortion Ratio (SNDR)
In ADC measurement, the input signal is usually a sinusoidal input. When a sinusoidal signal of a single frequency is applied to a system, the output of the system generally contains a signal component at the input frequency. Due to distortion, the output also contains signal components at harmonics of the input frequency. Otherwise, quantization error during conversion is also injected to output signal. As the figure 2.3 shows, the output signal consists of three components, input signal, distortion and noise level. The spurious free dynamic range (SFDR) is defined as the ratio of the largest spurious frequency and the fundamental frequency. The signal-to-noise-and-distortion ratio (SNDR) is the ratio of all error energy to signal energy. Quite often the term signal-to-noise ratio is used although SNDR is actually meant.
Figure 2.3 Example of frequency domain plot 2.2.4 Dynamic Range(DR)
Dynamic range is another useful performance benchmark. Dynamic range is a measure of the range of input signal amplitudes for which useful output can be obtained from a system.
When the signal to noise ratio is 0dB, it means that it is the minimum detectable input signal power. Figure 2.4 illustrates a plot of SNR versus input level. The dynamic range is defined as the ratio of the input signal level for maximum SNR to the input signal level for 0dB SNR.
If the noise power is independent of the level of the signal, the dynamic range is equal to the SNR at full scale. However, in some cases the noise power increases as the signal level increases. Therefore, the maximum SNR is less than the dynamic range normally.
Limited by noise
Figure 2.4 SNR versus input level 2.2.5 Imperfections
ADC has a transfer characteristic that approximates a straight line. The transfer characteristic for an ideal version of such an ADC input progresses from low to high in a series of uniform steps. However, the transfer characteristic of a practical ADC has several imperfections. Such non-idealities can be expressed in several ways as showing in Fig 2.5. In figure 2.5(a), the transfer curve all shift by a constant amount which is named offset. It may be caused by offset of operational amplifier but not affect the linearity of ADC. Figure 2.5(b) shows the practical ADC has gain error so the slope is not equal to ideal. The deviation between them comes from insufficient gain of operational amplifier and mismatch by manufacturing. In figure 2.5(c), steps are not perfectly uniform, and this deviation generally contributes to further non-idealities. Linearity error refers to the deviation of the actual threshold levels from their ideal values and is generated by distortion feature of transistor. The excessive linearity error results in missing code.
(a) (b)
(c)
Figure 2.5 Imperfections in ADC (a) Offset (b) Gain error (c) Non-linearity
2.2.6 Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) Nonlinearity is characterized by INL and DNL admittedly. Differential nonlinearity (DNL) measures how far each of the step sizes deviates from the ideal value of the step size.
Integral nonlinearity (INL) is the difference between the actual transfer characteristic and the straight line characteristic which the ADC is intended to approximate. DNL and INL are both plotted as a function of code. DNL and INL are generally expressed in terms of least significant bit (LSB) of the input. The value of LSB has been shown by equation (2.4) previously. Figure 2.6 illustrates DNL and INL, which can be expressed as Equation (2.7) and Equation (2.8).
Flash ADC, which is the fastest and one of the simplest ADC architectures, is shown in Figure 2.7. It performs 2N−1 level quantization with an equal number of comparators. The
reference voltages for the comparators are generated using a resistor string, which is connected between the positive VREF and the negative -VREF reference voltage determining the full scale signal range. Together the comparator outputs form a 2N −1 bit code, where all the bits below the comparator whose reference is the first to exceed the signal value are ones, while the bits above are all zeros. This so-called thermometer code is converted to N-bit binary code with a logic circuit, which can also contain functions for removing bit errors (bubbles).
Figure 2.7 Flash ADC architecture
The most prominent drawback of flash ADC is the fact that the number of comparators grows exponentially with the number of bits. Increasing the quantity of the comparators also increases the area of the circuit, as well as the power consumption. And the other
disadvantage is comparator offset sensitivity. At high resolutions, this required comparator offset becomes very small and are difficult to design. Thus, very high resolution flash ADCs are not practical, typical resolutions are seven bits or below.
2.3.2 Cyclic ADC
A cyclic ADC operates the same as a single pipeline stage. With the output feedback to the input, the cyclic ADC converses the data during the next clock cycle. The block diagram is illustrated in Figure 2.8. The stage conversion time from the input sample to complete digital output is the same as for a pipelined ADC. However, the throughput rate is much less than for a pipelined ADC because the entire digital word must be generated after several clock cycles passed. However, a cyclic ADC is much superior in hardware and power because of just one stage is reused repeatedly.
Figure 2.8 Cyclic ADC architecture
2.3.3 Pipelined ADC
The block diagram of a typical pipelined ADC is shown in Figure 2.9. Mostly, the beginning sample and hold relaxes the timing requirements of the first stage during its sampling phase by holding the instantaneous value of the analog input. Following the S/H, it consists of a coarse subADC, coarse subDAC result, subtraction, and amplification of the remainder.
Within each stage, the analog input signal from the last stage is first sampled and held.
The signal is coarsely quantized by a subADC to resolve n bits. Then using a subDAC, the quantized value is subtracted from original input signal to yield the output residue. For the output signal range is the same with the input signal range for each stage, this is made by the amplifier with gain of 2n. The resulting residue signal is applied to the next stage for finer conversion on the next clock cycle. The function of the D/A, the subtraction, and the amplification of the remainder are combined into one single circuit called the multiplying DAC (MDAC).
Take 1.5bit conversion stage for example. Figure 2.11(a) shows the 1.5bit transfer curve which has three segments and is encoded as 00, 01, and 10. The input range is normally the same as output range. The conversion gain in each part is 2. The two side lines decided by subADC are 1/4VREF and -1/4VREF.
Now introduce some non-linearity affections, including of comparator offset, amplifier offset, and gain error. As illustrated in figure 2.11(b), comparator offset shifts the sight line by an offset value. Although the offset may lead output swing to over range, 1.5bit architecture has 1/4VREF tolerance of comparator offset to overcome. Figure 2.11(c) shows the amplifier offset which moves the whole conversion curve by a value. But for linearity, amplifier offset is inessential. Figure 2.11(d), gain error in subDAC, will cause the slope of transfer curve less than 2 and the output digital code will be missing.
Figure 2.9 Pipelined ADC architecture
Figure 2.10 Block diagram of radix-2 1.5b pipeline stage
(a) (b)
(c) (d)
Figure 2.11 (a) Ideal transfer curve (b) With comparator offset (c) With amplifier offset (d) With gain error
2.4 Design Issue of Pipelined ADC
2.4.1 Stage Accuracy and Speed Requirement
In the pipelined ADC, MDAC in each stage has two main specifications, speed and accuracy requirement. The speed requirement means the operation speed which is related to bandwidth of operational amplifier and feedback factor in MDAC architecture. The accuracy requirement is also affected by feedback factor but the main cause is the open-loop gain of operational amplifier. However, the constraint on each stage is different because the stage resolution decreases as the stage goes lower. Lower stage resolution means that design constraints are more relaxed. Considering the gain requirement becomes looser for later stages, several benefits are obtained if each stage is design specifically, for instance the power consumption and chip area.
General speaking, the way to implement the MDAC function is to use the switch capacitor technique. First of all, because the 1.5bit architecture is applied in this design, we just analyze this one that is shown as figure 2.12. By sampling the input signal on the capacitor and redistribution the signal charge on the capacitor, the output in hold mode is as (2.8). Note that equation ignores the time domain factor which will be discussed latter.
( )
Equation (2.9) shows that VO has a gain error term due to A is finite. In order to achieve N-bit
performance, this gain error term should be less than 1LSB of the next stage resolution (z-bit)
Therefore, the specification of gain is given by (2 P )2Z
A> +C C (2.11) Subsequently, the equation of speed requirement for the MDAC’s amplifier is derived.
By assuming that the MDAC in hold mode is a single pole system and ignoring the slewing behavior, the MDAC settling time constant is
(
2 P)
u
τ C C ω
= + (2.12)
Where ωu is unity-gain bandwidth of amplifier. Since the setting error of a single pole system is
2 2 ,
T Z
e−φ τ < − Tφ =time interval in hold mode
2 (2.13)
The constraint of unity-gain bandwidth is expressed as
2
According to equation (2.11) and (2.14), the gain and unity-gain bandwidth can be well designed to meet the constraints.
2.4.2 Double Sampling
Double sampling means another duplicated path is added to let the amplifier is always in hold conversion. Output data rate is equivalently doubled without any power added.
Unfortunately, several nonlinearities are also induced to decrease the efficiency, including memory effect, timing skew, and gain mismatch.
Memory effect means a fraction of the previous sample remains stored in the parasitic capacitance in the input of the amplifier due to the finite gain of the amplifier. Timing skew is caused by the distance between two adjective sampled edges is not the same as clock period.
It can be found in the frequency spectrum domain. If input frequency is n Hz and sampling rate is m Hz, the timing error will be produced in the position of (m/2-n) Hz. While there is a gain mismatch between the parallel circuits, the sampling sequences they produced have different amplitudes. In the frequency domain, additional component is at multiples of half sampling rate.
Memory effect and timing skew can be suppressed by proper circuit design, which will be introduced later. Gain mismatch is avoided by symmetry layout to get better device matching.
2.4.3 Power Optimization
Error source is the random component whose dominant source is thermal noise. They are contributed by transistors in amplifier and capacitors in each stage. Assuming that thermal noise is additive Gaussian, the noise at the amplifier output appears as being superimposed on the signal. The power of the thermal noise is then described by its variance, and the variance should be much less than one LSB in order to maintain sufficiently high SNR. So, for the pipeline stage with N-bit accuracy requirement, the total input referred noise should be much
less than one LSB at N-bit level.
total 1LSB
σ < (2.20) The total input referred noise can be found by summing all the noise components from subsequent stages and is given by
2 4 4 the thermal noise of capacitor in stage j. Notice that the dominant source of noise is from the first stage and the noise contribution from subsequent stages is reduced by the inter stage gain.
Besides, equation (2.11) and (2.14) show the constraints will be relaxed down as the z parameter gets lower. Therefore, we can design stage by stage to optimize power consumption and the noise performance is still acceptable[15].
2.5 MATLAB Behavior Model
In this section, the behavioral model of a 10-bit pipelined ADC with the 1.5-bit per stage architecture is constructed by MLTLAB. The pipelined ADC consists with 9 stages is shown as figure 2.13. First stage is named FADAC[2], 2 to 8 stages use conventional MDAC and 2bit flash ADC is in final stage. Finally combine each 2bit output to produce 10bit digital code.
Figure 2.13 Block diagram of behavior model
First of all is finding out all of mathematical characteristics of each block including 1st stage FADAC, MDAC, and 2bit flash ADC. The FADAC and MDAC in hold time are shown in Figure 2.14. Besides, 2bit flash ADC can be described by if-then-else syntax in coding easily.
(a) (b)
Figure 2.14 (a) FADAC in hold mode (b) MDAC in hold mode
Discuss gain error effect in characteristic function of each stage. The transfer curve with finite gain error due to amplifier in FADAC and MDAC are shown in (2.22) and (2.23).
, , Where CP is input capacitor of Amplifier, CS and Cf are sample and hold capacitor, respectively. If the gain of amplifier is finite, VO will have gain error.
The gain of amplifier is set 48dB which is the same as the circuit level simulation result.
Figure 2.15 illustrates the spectrum domain of reconstructed digital output. While calibration off, the third harmonic tone is 54dB and ENOB is 8.21bit. After calibration, SFDR increases to 70dB and it means the non-linearity is suppressed well. As the figure 2.15 shows, the calibration can effectively reduce the harmonic tone to increase the performance but notice
that the noise flow is the same no matter the calibration is on or not.
(a) (b) Figure 2.15 Simulation result of Behavior model
(a)With calibration (b)Without calibration
Then plot the curve by changing the gain value from low to high as the figure 2.16(a).
With gain increasing, the resolution also increases but settles to 8.88bit finally. The least gain to achieve above 8bit is about 30dB. Figure 2.16(b) is the difference between two curves in figure 2.16(a). The improvement is over 2bit with lower gain. With gain increasing to 55dB, the improvement is down to 0bit. The trade-off range of gain between the performance and improvement is from 30dB to 50dB. In the circuit level we design is about 48dB which meets the simulation result of behavior model.
With gain increasing, the resolution also increases but settles to 8.88bit finally. The least gain to achieve above 8bit is about 30dB. Figure 2.16(b) is the difference between two curves in figure 2.16(a). The improvement is over 2bit with lower gain. With gain increasing to 55dB, the improvement is down to 0bit. The trade-off range of gain between the performance and improvement is from 30dB to 50dB. In the circuit level we design is about 48dB which meets the simulation result of behavior model.