3.2 Each Block of Pipelined ADC
3.2.10 Clock Generator
Figure 3.15 shows the clock generator schematic and waveform diagram. Because of the use of double sampling technique, we need to be aware of the clock skew effect. As the mark 1 show, creating a Gating signal to make sure the space between Clkf1 and Clkf2 falling edges can reduce clock skew. Mark 2 indicates Clkd1 falling production. Besides, we should let the point a and b have the same delay, so a transmission gate is added. It is shown as mark 3. By tuning the size of transmission gate, we can get the best situation which has least clock skew effect. Figure (c) shows the simulation result.
(a) (b)
(c)
Figure 3.15 (a) clock generatior schematic (a) waveform diagram (c) simulation resolutoin 3.2.11 Timing Diagram
The important role in pipelined ADC is timing diagram. Figure 3.16 shows the timing diagram which ensures the ADC function correctly in timing sequence. Q1 and Q2 are alternate each other and represent the two channels under double sampling. Mark 1 shows FADAC samples data and comparator evaluates at this time. Mark 2 means encoder decides to do right subtraction and FADAC transit to hold mode. At the same time, MDAC in next stage
is in sample mode. Then, Mark 3 is the time at the end of MDAC hold state. Mark 4, the signal has already settled accurately and MDAC transit sample state to hold mode.
Besides, Clkrst introduced in 3.2.8 Double Sampling is between two adjacent states to cancel the memory effect.
Figure 3.16 Timing diagram
C HAPTER 4 C ALIBRATION C IRCUIT
4.1 Calibration Conception
(a)
(b) (c)
Figure 4.1 (a) Ideal and real transfer curves (b) FADAC in hold mode (c) MDAC in hold mode
Figure 4.1 shows the radix-2 1.5bit transfer curve in MDAC circuit. The transverse axle means input value and longitudinal axle is output value. Black line is ideal curve and each
slope in the three segments is 2. Red line is less than 2 due to opamp gain error. Define slope in black line is Gn, slope in red line is Gn’. Figure 4.1(b) is FADAC circuit in hold mode and (c) is MDAC circuit in hold mode. By hand calculation, assume C=CS=CF, the slope can be written
MDAC due to the feedback factor in MDAC is almost twice than which in FADAC.
Then, define G=G1=G2, and assume the first stage is FADAC and others are MDACs, from 10bit analog to digital conversion equation
( ) ( )
where A is the input signal, Anda is digital code from n-th subADC output, G is ideal conversion gain and G’ is real conversion gain.
The value of ΔA is what the calibration circuit need to measure. By (4.2) constructed, the gain error can be compensated ideally. So the performance of pipelined ADC should be improved.
4.1.1 Nonlinearity of gain
In the above discussion, the gain is assumed as a constant value. Accordingly, the transfer curve of each section is approximated to a straight line. In practical, the output impedance is dependant on the output value, so the gain value also varies with the output. As
the figure 4.2 shows, the slope of G’ due to gain deviation is various with a small range.
Define the gain deviation due to gain nonlinearity
0 0
-A
A A
Δ = A (4.3) Where A0 is the gain without gain deviation and A is the gain with gain deviation. By the intuition, set parameter k is improvement of calibration circuit. We can get
2k
Δ <A (4.4) On the other hand, the nonlinearity of gain is the dominant influence in the efficiency of calibration. Figure 4.3 shows the simulated nonlinearity of opamp which is the same as figure 3.2(b) shows. With the corner simulation, the gain deviation is about 25%. By the equation of (4.4), the improvement can be near 2 bit.
Figure 4.2 Slope deviation due to gain deviation
Figure 4.3 Nonlinearity of opamp versus differential output
4.2 Calibration Circuit
Figure 4.4 shows the calibration circuit which is applied to measure the gain error. The components are two opamps, one comparator, and an accumulator. One of the opamps is the same as which in first several stages and the other has higher gain to have higher resolution.
In Clka, Vi samples to CF and CH. when Clkb becomes high, due to the gain error VO is a slightly smaller than Vi. Define the difference is symbol of Δ. Furthermore, Vout is much close to Vi because AC gain is high. Then, Clk1 and Clk2 start to become high alternately. So Vout
decreases one Δ as one clock period passes. As the figure (b) shows, while Vout becomes less than zero, comparator lets the accumulator stop counting. At this time, digital code output is produced and shown as (4.4).
(a) (b)
Figure 4.4 (a) Calibration circuit (b) Clock and output waveform
P PC
From (4.5), there are a simple relation between Digital Code and gain error. Then combine (4.2) and (4.5)
3 9
Where n is the calibration circuit output, G is ideal conversion gain, and Anda is digital code from n-th subADC output. Equation (4.6) means the compensated operation in off-line calibration and illustration is shown in figure 4.5. The division and add operations are needed.
⎛ ⎞
Figure 4.5 Illustration of off-line calibration operation
4.3 Operation Amplifier in Calibration Circuit
In calibration circuit, a high gain opamp is needed but the unity-gain frequency and output swing is not required strictly. As the figure 4.6(a) shows, folded-cascoded opamp is applied. The output swing just needs 150mV, so the VDD is allowed to be 1V. The wide swing cascode bias circuit is shown in figure 4.6(b). The common mode feedback circuit (CMFB) is used as figure 3.4(a). The simulation result is shown in table 4.1. The dc gain is 64dB and power consumption is 220μW.
(a) (b) Figure 4.6 (a) Amplifier in calibration circuit (b) Bias circuit
Table 4.1 Amplifier in calibration circuit simulated result
Temperature 50℃
Supply Voltage 1V
Input and output common mode voltage 0.75V , 0.5V
Output Loading 0.2pF
Differential Output Range 300mVPP
Corner TT SS FF
DC Gain A0 [dB] 64.4 63.3 64.3
Unity-Gain Frequency fu [MHz] 100 94.5 103
Phase Margin [º] 58 59 57
Power Consuption [μW] 220 210 225
4.4 Calibration Circuit with Offset Cancellation
(a)
(b) (c) (d) Figure 4.7 (a) Calibration circuit with offset.
(b) VOS1 affection (c) VOS2 affection (d) VOS3 affection
Now, consider the offset effect from each component in calibration circuit. There have three offsets contributed from replica opamp, calibration opamp, and comparator. As the figure 4.7 shows, discuss each offset effect due to VOS1, VOS2, and VOS3, respectively. First, if VOS1 is not equal to zero, VO will always have VOS1 term and finally let the subtraction operation have a false result. Second, assume VOS2 is larger than Δ, then Vout will increase step by step during clock period passing and finally be saturated. That is not desirable situation. Third, VOS3 cause the comparator decision level to shift by a value. Therefore, depend on VOS3 is negative or positive, digital output may be increase or decrease.
Furthermore, in order to get accurate output data, offset cancellation is applied to eliminate the offset non-ideal effect.
The technique of input offset storage cancellation (IOS) is applied. The conception is to keep opamp differential inputs as voltage of VOS during whether Clk1 or clk2. Because of opamp input and output common mode voltage are not the same, we use the capacitor to be feedback.
Figure 4.8 shows how to cancel VOS1 effect. In Clk1, Vi samples to CH, the feedback Cr
is connect between opamp input and output node. The opamp input is virtual ground to be VOS1 under negative feedback loop. So the offset is retained in CH. when next Clk comes, Clk2, Cr is replaced by CH. In this time, the voltage of opamp input is still the same as VOS1 and output have no offset effect. It means the offset is cancelled. As figure (b) shows, VO is equal to Vi during Clk2.
(a) (b)
Figure 4.8 (a) VOS1 cancellation circuit (b) Waveform representation
Figure 4.9 shows cancellation circuit of VOS2. The method is the same as above. Cr is the feedback capacitor and replaced by C in rotation. The output waveform is shown in figure.
Vout decreases by Δ as one clock period passes. Although the gap of every step is correct but the initial value of Vout is still have VOS2 term. It will affect the output digital code of calibration circuit. Nevertheless, the problem will be solved in next paragraph.
(a) (b)
Figure 4.9 (a) VOS2 cancellation circuit (b) Waveform representation
Finally, about VOS3 effect, we try to change polarity of input voltage in turns.
Considering the VOS3 and residual VOS2 will be combined into a constant offset equivalently, offset affection can be cancelled by average operation. In positive polarity, Sel=1, Vi is positive input; On the other hand, Sel=0 means in minus polarity.
As figure 4.10 shows, during Sel=1 and Sel=0, digital output are N1 and N2, respectively. By average operation, calibration circuit output n is produced
n = N + N1 2
2 (4.7)
(a)
(b)
Figure 4.10 (a) VOS3 cancellation circuit (b) Waveform representation
4.5 Simulation Result
The simulation result of calibration circuit is shown in figure 4.11(a) and (b). Figure 4.11(a) is pre-simulation result, because of no offset effect, the digital output is equal no matter Sel is changed or not. In post-simulation result, by layout couple capacitor effect, the digital output are less than figure 4.11(a) and different in Sel=1 and Sel=0 cases. After layout, digital output is 47 in TT corner, 56.5 in SS corner, 43.5 in FF corner.
(a)
(b)
Figure 4.11 Calibration circuit simulation result (a) Pre-simulation (b) Post-simulation
C HAPTER 5 E XPERIMENTAL R ESULT
5.1 Floor-planning and Layout
The experimental implementation of time-interleaved pipelined ADC has been integrated in a 0.18μm CMOS process. The active area of ADC is 0.9×0.9mm2 and the die area is 1.45×1.5mm2. Figure 5.1 shows the floor-planning and layout of the chip. A differential analog signal is applied to the FADAC at the top left side. The stage 1 through 8 and ends up are shown in the figure. Calibration circuit is at the bottom left corner. Output buffer is at the middle and clock generation is space at the top left corner. Additionally, bypass capacitor is used to stable the reference voltages which connect to each stage. No matter the input or output pads, ESD pads are applied. And in order to isolate the couple noise, we separate pads into analog and digital parts.
Figure 5.1 Floor-planning and layout
5.2 System Simulation Result
5.2.1 Time domain Simulation
Figure 5.2 shows the time domain simulation. Figure 5.2(a) is input waveform at amplitude is 1.2V and frequency is 8MHz. Figure 5.2 (b) is ADC digital output waveform.
The output is reconstructed by ideal DAC and normalized from -128 to 128. The input and output waveform are almost the same and indicates the ADC function is correct.
(a) (b)
Figure 5.2 (a) Input waveform (b) Reconstructed output waveform 5.2.2 Dynamic Simulation
Figure 5.3 shows the pre-simulated and post-simulated FFT plot. The SNDR, SFDR, and ENOB at a 8MHz input and a 80MS/s sampling frequency are shown in each top right corner of figure. Before calibration, the ENOB of ADC is above 7bit both of pre-simulation and post-simulation. With calibration on, the performance of ADC is increased to 8.7bit at least. The 3rd harmonic tone is suppressed obviously and the improvement due to calibration circuit is about 1.5bit. In figure (d), at 32 MHz, timing error due to capacitor couple effect after layout is about 70dB. In the calibration operation, the accuracy of division operator is set to be 14bit, calibration circuit digital output are set 53 and 47 while pre-simulation and
post-simulation, respectively.
(a) (b)
(c) (d) Figure 5.3 Simulated FFT in input frequency=8MHz,
Sampling rate=80MS/s
(a) Pre-simulation and calibration OFF (b) Pre-simulation and calibration ON (c) Post-simulation and calibration OFF (d) Post-simulation and calibration ON
The relation between frequency of sampling clock and ADC performance is shown in figure 5.4. Lower line is without calibration curve and upper line is after calibration curve. It shows that the improvement due to calibration circuit can hold out 1.5bit when sampling frequency is lower than 80MS/s. When sampling frequency is above 80MS/s of, the efficiency
will degrade due to signal is not settled in each stage of ADC.
Figure 5.4 Post-simulated ENOB vs. sampling frequency
Then, discuss with affection of calibration output to ADC ENOB. From figure 4.8 of chapter 4, digital output of calibration circuit after layout is 47. By changing the digital output code from low to high, figure 5.5 shows the curve of improvement after calibration at input frequency is 8MHz and sampling frequency is 80MS/s. Without calibration, the ADC performance is 7bit. With the calibration on, the improvement is up to 1.5 bit at the calibration output is 47 and decreases with calibration output goes high or low.
Figure 5.5 Improvement vs. calibration output digital code with calibration ON
Increase the input frequency up to half clock rate to plot the dynamic performance curve. Figure 5.6(a) is pre-simulation result, input frequency is from 8MHz to 40MHz, SFDR and SNDR is about 45dB and ENOB is about 7bit without calibration. When calibration on, SFDR and SNDR are obviously boosted to above 60dB and 52dB, respectively. And the ENOB is improved to 8.6 to 8.4bit with input frequency goes high. Figure 5.6(b) is post-simulation result, it also have the same tendency as curves in figure 5.6(a). The improved ENOB is from 0.5 to 0.8bit.
(a)
(b)
Figure 5.6 (a) Pre-simulation of SFDR, SNDR, and ENOB vs input frequency (b) Post-simulation of SFDR, SNDR, and ENOB vs input frequency
Variation from foundry will affects characteristic of transistors, so corner simulation is also needed. Figure 5.7(a) shows the TT and FF simulation result. Basically, the two corner curves have the same tendency. Before calibration, ENOB is about 7 bit, and after calibration ENOB is about 8.4bit. The total calibration improvement is 1.4bit. Figure 5.7(b) is simulated in corner SS. Due to parasitic effect and timing error between two paths, sampling rate decreases to 60MS/s and one path is chosen to analyze in order to have the same performance as corner TT and FF. Equivalently, the ADC operates at sampling rate is 30MS/s. In the above-mentioned, the calibration digital output is applied with 47 in TT corner, 56.5 in SS corner, 43.5 in FF corner.
(a) (b) Figure 5.7 Corner of post-layout simulation (a) Sampling frequency is 80MS/s in TT and FF corners
(b) Sampling frequency is 60MS/s in SS corner
5.2.3 INL and DNL
INL and DNL show the non-linearity performance of pipelined ADC. Figure 5.8 (a) is before calibration, because gain error of opamp, DNL has missing code and INL is about
±3LSB. After calibration, Figure 5.8(b), the missing code in DNL is disappeared and INL is
improved to be less than ±0.5LSB, obviously. The LSB is 9bit resolution to full scale input.
(a)
(b)
Figure 5.8 INL and DNL
(a) Before calibration (b) After calibration 5.2.4 Dynamic Range
Figure 5.9 shows the dynamic range simulation result. Two curves with and without calibration are almost the same while input signal level is low. While input level becomes higher, the two lines will separate because gain error dominates in lower line. The dynamic range shown in figure is about 60dB.
Figure 5.9 Dynamic range 5.2.5 Specification Table
Table 5.1 shows the performance summary simulated in 0.18μm CMOS process. The conversion rate is 80MS/s and resolution is 9bit. In post-simulation, the ENOB is 8.76bit and 8.69bit at input frequency is 8MHz and 40MHz, respectively. The total power added by ADC core, clock generator, and calibration circuit is 11.5mW. The FOM is defined as
2ENOB
Power
FOM = Conversion rate
× (5.1)
In this design, the FOM is 0.40pJ/Setp at input frequency is 40MHz and 0.35pJ/Setp at input frequency is 8MHz at post-simulation.
Table 5.1 ADC specification of pre-simulation and post-simulation
Figure 5.10 depicts the measurement setup used to assess the performance of the experimental low voltage pipelined ADC described in this work. The supply voltages for both analog and digital parts to the board are generated by the power supply. In order to prevent the digital noise coupling to the analog circuits, analog and digital powers are isolated to each other in the PCB board. The input signal is provided by a high performance signal generator, Agilent E4438C and system clock is supplied by pulse generator, Agilent 8133A. Otherwise, the output bit streams are fed to the logic analyzer, Agilent 16700. The digital data stored in the logic analyzer is subsequently download to a personal computer and processed by
MATLAB, including of calibration and FFT analysis.
Figure 5.10 Measurement consideration 5.3.2 Experimental Result
Figure 5.11 shows the chip microphotograph of the fabricated ADC. The chip dimensions are 1.45×1.55 mm2 and the active area is 0.85×0.9 mm2. Operating at a 40MS/s sampling rate under 1.8 and 1V power supplies, the total analog circuit consumes a total of 7.3mW and digital circuit consumes 4.2mW.
Pipelined ADC
Calibration Circiut
Figure 5.11 ADC chip microphotograph
Figure 5.12 shows the measured calibration circuit output. Figure 5.12(a) is at transient state and Figure 5.12(b) averages the outputs by 512 samples to suppress the noise. The value 49.78 is close to the post-simulation result.
(a) (b) Figure 5.12 The measured calibration circuit output
Figure 5.13 shows the ADC’s differential nonlinearity (DNL) and integral nonlinearity (INL) characteristics obtained from code-density measurements. The LSB is normalized to 9bit resolution in those figures. The number of registered output code is 16384. Figure 5.12 shows the ADC’s native DNL and INL before activating the off-line calibration. The DNL is +1.2/-0.8 LSB and INL is +4/-4 LSB. Figure 5.14 shows the ADC’s DNL and INL after calibration is activated. The DNL is +1.1/-0.8LSB, and the INL is reduced to +1.3/-1.3 LSB.
Figure 5.13 Measured DNL and INL at 80MS/s with calibration off.
Figure 5.14 th calibration on.
Figure 5.15 shows the ADC’ FFT) spectra at a 80MS/s
sampling rate. The input is dif Without calibration,
the third-order harm , which is -46.4dB below the
fundamental signal. The signa ratio (SNDR) is 42.3dB and the
spurious-free dynami NDR is ferential 600mVPP 1MHz sinusoidal signal.
onic is the dominant distortion term l-to-distortion-plus-noise
c range (SFDR) is 46.4dB. After calibration is activated, the S proved by 42.3dB to 46dB and the SFDR is improved by 46.4dB to 54.7dB. Notably
ing error remain almost the same before and after calibration. The mprovement after calibration comes from the elimination of harmonic tones.
Figure 5.16 shows the ADC’s measured SNDR and SFDR versus input frequencies at a 80HS/s sampling rate. The SNDR and SFDR decrease up to the Nyquist frequency because of aperture jitter dominating the performance. Generally, the calibration can improve the SNDR by 4dB and the SFDR by 10dB at low input frequency. Figure 5.17 shows the ADC’s SNDR versus input signal level with calibration on and off respectively. The 1MHz input is sampled at 80MS/s. The figure 5.17 reveals that the measured dynamic range is 52dB. The figure 5.18 shows the measured ENOB versus sampling frequencies at a 1MHz sinusoidal signal. With pling rate above 80MS/s, the performance deceases below 7 bit after calibration is activated.
The 600mVPP led at 80 MS/s.
Figure 5.15 Measured output FFT spectra.
1MHz differential sinusoidal input is samp
Figure 5.16 Measured SFDR,SNDR, and ENOB versus sinusoidal input is sampled at 80 MS/s.
Figure 5.17 Measured SNDR and SNR versus input level. The 1MHz differential sinusoidal input is sampled at 80 MS/s
Figure 5.18 Measured SNDR and differential sinusoidal input is sampled at 80 MS/s
SNR versus input level. The 1MHz
C HAPTER 6 C ONCLUSION
Table 6.1 summarizes the measured performance of the ADC prototype at room perature. The power supplies are 1.8V and 1V. With calibration on, the SNDR is 46.0dB
pling rate is 80MS/s and input frequency is 1MHz. The FOM r references shown in table I, the performance is 4 times ss than [4] and [7] but is similar to reference [1] under the same technology.
Table 6.1 Performance summary of ADC at room temperature tem
ISSCC[7] ISSCC[1] ISSCC[4] Simulation Measurement
Technology 90nm 0.18μm 90nm 0.18μm 0.18μm
Supply Voltage 0.8V 1.8V 1V 1.8V,1V 1.8V,1V
Resolution 10bit 10bit 10bit 9bit 9bit
Conversion Rate 80MS/s 125MS/s 30MS/s 80MS/s 80MS/s
SNDR 55dB 53.7dB 58.4dB 54.1dB 46.0dB
ENOB 8.8bit 8.6bit 9.4bit 8.69bit 7.35bit
Signal Swing +/-600mV - +/-500mV +/-300mV +/-300mV
Signal Swing +/-600mV - +/-500mV +/-300mV +/-300mV