4.2 Measured Results
4.2.2 Measured Results of the Delta-sigma Modulator
The measured results of the delta-sigma modulator are shown in Fig. 4.5 and Fig.
4.6. Those represent the relation between the clock signal Clk and the output bit stream b[n] under different input voltage. As discussion in chapter 2, the probability of ‘logic-1’ in the bit stream b[n] is approximately equal to the input voltage ratio. As the input voltage Vi+ is equal to 1V and Vi- is equal to 9V at the operating frequency of 2 MHz, 16 cycles of ‘logic-0’ accompany 2 cycles of ‘logic-1’ can be found in the bit stream b[n] as shown in Fig. 4.5. With such an input signal, the probability of
‘logic-1’ of b[n] is approximately 0.11, which is close to the input voltage ratio (1/10).
Fig. 4.6 shows another example that the input voltage Vi+ and Vi- are both changed into 5V. Then, 4 cycles of ‘logic-0’ accompany 4 cycles of ‘logic-1’ can be found in the bit stream b[n], which producing the probability of ‘logic-1’ of b[n] is 0.5 to fit in the input voltage ratio (5/10).
Figure 4.5 Measured result of the delta-sigma modulator between the relation of output bit stream b[n] and clock signal Clk as the input Vi+ is 1V and Vi- is 9V.
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Figure 4.6 Measured result of the delta-sigma modulator between the relation of output bit stream b[n] and clock signal Clk as both input Vi+ and Vi- are 5V.
To measure the circuit performance of the delta-sigma modulator, Vi+ is changed from 1V to 9V and Vi- is changed from 9V to 1V, respectively. The result is shown in Fig. 4.7. Fig. 4.7 shows the comparison between ideal and the measured results of probability of ‘logic-1’ in the bit stream b[n]. Good agreement between ideal calculation and measured results can be obtained from the fabricated delta-sigma modulator.
In this experiment, there are 10 panels measured and compared as shown in Fig.
4.8 where each panel is illustrated with different characters. As the figure shows, the measured results of these 10 panels approach each other and their average waveform shown in Fig. 4.9 is linear and close to the ideal calculation line. Besides, the standard deviation between these 10 panels is calculated and illustrated in Fig. 4.10. It can be found that the minimum of standard deviation occurs as Vi+ of 5V and the maximum of that which is less than 2% occurs as Vi+ of 9V. Summing up the above measured
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results, the delta-sigma modulator is successfully implemented and verified on glass substrate in a 3-μm LTPS technology.
Figure 4.7 Measured results of the fabricated delta-sigma modulator, comparing with the ideal calculation.
Figure 4.8 Comparison between ideal and measurement results of probability of
‘logic-1’ in the bit stream b[n] with different 10 panels.
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Figure 4.9 Measured results comparison between the average of the 10 panels and the ideal one.
Figure 4.10 Standard deviation calculated between 10 panels with the input signal Vi+
changing from 1V to 9V.
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In this section, the measured results of the decimation filter are illustrated. As the discussion in chapter 3, the decimation filter which is a low pass filter can down sample the input signal coming from the delta-sigma modulator and decimates into 8-bit digital code. At first, the decimation filter is measured without combining with the delta-sigma modulator. On the contrary, the Agilent 81110A pulse generator is used to substitute for the delta-sigma modulator to provide input signal of the decimation filter. Fig. 4.11 shows the measured results of the decimation filer which input is provided by changing the duty cycle in the waveform of the pulse generator.
Because such decimation filter will sum up the number of ‘logic-1’ in every 256 cycles, changing the duty cycle of the input pulse will change the probability of
‘logic-1’ counted by the decimation filter. The measured results are compared with the ideal one in decimal form. Good agreement between ideal and measured results can be obtained from the fabricated decimation filter.
Figure 4.11 Measured results of the decimation filter and its input signal is given by the pulse generator instead of the delta-sigma modulator.
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4.2.4 Measured Results of the Delta-sigma A/D Converter
The measured results of the whole delta-sigma ADC are shown in Fig. 4.12 and Fig. 4.13 for two measured panels. The output of the delta-sigma ADC has a small range of variation on b[n] when the input is unchanged. The reason for this phenomenon is that the period of the bit stream b[n] is not always a factor of 256 (the 256 is the conversion cycle number of the decimation filter) and it is different from each other when the different input is given. For example, the period of b[n] is 18 cycles containing 2 numbers of ‘logic-1’ and 16 numbers of ‘logic-0’ as shown in Fig.
4.5. When the number 256 is divided by 18, the remainder is 4. Thus, that will cause 4 cycles error. Thus, as the input signal is unchanged and the period of b[n] is not a factor of 256, the results calculated by the decimation filter in every 256 cycles will cause some difference.
The minimum and maximum measured results are both shown in Fig. 4.12 and Fig. 4.13. As these figures show, the square character identifies the minimum value obtained by the digital output of the decimation filter and then normalized with a factor 256. The circle character identifies the maximum value. The triangle character identifies the probability of ‘logic-1’ in bit stream b[n] which is measured by the procedure discussed in section 4.2.2. Thus, both in Fig. 4.12 and Fig. 4.13, the triangle character lines always locate between the other two lines.
Fig. 4.13 shows the error level that is derived by counting the differences between the maximum/minimum measured value and the ideal one. The maximum value of the error level is less than 2 and the minimum value of that is larger than -2.
Thus, the resolution of this proposed delta-sigma ADC is derived as about 7-bit as the calculation in equation (4.1).
256
7=2 7
2 ⇒ − bit Resolution
±
. (4.1)~ 57 ~
Figure 4.12 Measured results of the ADC where its digital output is normalized to compare with the probability of b[n].
Figure 4.13 Measured results of the ADC where its digital output is normalized to compare with the probability of b[n] with another panel.
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Figure 4.14 The error level observed by counting the differences between the maximum/minimum value and the ideal one.
Furthermore, the fabricated delta-sigma ADC is measured under different ambient light to estimate whether the proposed circuit operates normally when that is integrated on panel and exposed to the back light. The fabricated delta-sigma ADC is measured under strong light source, weak light source, and daylight. The measured results are nothing different under these three measurement conditions. Thus, this proposed delta-sigma ADC can be applied to the panel application without worrying about the influence contributed by the backlight.
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As the observing in section 4.2.2, the delta-sigma modulator is successfully designed and verified with its standard deviation is lower than 2%. The decimation filter can just be seen as a counter to process the signal coming from the delta-sigma modulator. The decimation filter will contribute some error because of the time variant property of this ADC and the period difference in the bit stream b[n]. The measured error level locates between +2 and -2, and the resolution of this proposed delta-sigma ADC is about 7-bit. Besides, the proposed circuit can be further applied to the panel application for its resistance to the backlight.
Thus, the proposed delta-sigma ADC has been successfully designed and realized in a 3-μm LTPS technology, and that is suitable to be further integrated with display panel for SOP applications.
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Chapter 5
Conclusions and Future Works
5.1 Conclusions
A delta-sigma ADC on glass substrate for panel integration has been successfully designed and fabricated in a 3-μm LTPS technology. A delta-sigma modulator is formed with an integrator, a comparator, a D flip-flop, and the negative feedback loop by Rf1 and Rf2 resistors operating at frequency equal to 2MHz to produce a serial bit stream b[n] output. The input signal can be reconstructed by calculating the running probability of b[n]. The decimation filter is used to change the high sampling rate and low resolution results into the low sampling rate and high resolution results. Good agreement between ideal calculation and experimentally measured results has been obtained from the fabricated delta-sigma modulator. The delta-sigma ADC studied in this work, which is realized on glass substrate and successfully verified in a 3-μm LTPS technology, is firstly reported in the literature. The proposed delta-sigma ADC can be further used to achieve the precise analog circuits for SOP applications, which enables the analog circuits to be integrated in the active matrix LCD (AMLCD) panels.
5.2 Future Works
The proposed delta-sigma ADC is realized with fully-differential structure;
however, most of sensing signals produced by the sensor are single-ended signals.
Thus, some circuits such as single-input to differential-output circuit should be further designed.
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Furthermore, the proposed delta-sigma ADC could be combined with sensing circuits such like temperature sensor or touch-sensing circuit to perform temperature-to-digital converter (TDC) as shown in Fig. 5.1 [14] or touch panel readout circuits and integrated on the glass substrate.
Figure 5.1. Block diagram of the temperature sensor.
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VITA
姓 名：蔡佳琪 學 歷：
國立武陵高級中學 (89 年 9 月~92 年 6 月) 國立交通大學電機與控制工程學系 (92 年 9 月~96 年 1 月) 國立交通大學電子研究所碩士班 (96 年 2 月~98 年 3 月)
研究所修習課程：
類比積體電路 吳介琮教授
數位積體電路 周世傑教授
積體電路之靜電放電防護設計特論 柯明道教授
計算機結構 劉志尉教授
功率積體電路設計 陳科宏教授
TFTLCD 面板設計實務 戴亞翔教授
數位信號處理 冀泰石教授
鎖相迴路設計與應用 陳巍仁教授
永久地址：桃園縣龜山鄉幸福村幸福三街39 號 5 樓
Email：nino.ee95g@nctu.edu.tw m9511706@alab.ee.nctu.edu.tw
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PUBLICATION LIST
[1] C.-C. Tsai, M.-D. Ker, Y.-H. Li, C.-H. Kuo, C.-H. Li, Y.-J. Hsieh, and C.-T.
Liu, “Design and realization of delta-sigma analog-to-digital converter in LTPS technology,” SID, Dig. Tech. Papers, 2009, in press.