Design of Fully-differential Folded-cascode Operational Amplifier

This section analyzes the frequency response of the fully differential folded-cascode amplifier. The schematic diagram of the fully-differential folded-cascode operational amplifier is shown in Fig. 2.4. Compared with the two stage operational amplifier, this architecture has better input common mode range and power supply rejection ratio. In particular, it provides large gain and it is easier to frequency compensate (the load capacitance is also the compensation capacitor).

Furthermore, it does not suffer from frequency degradation of the power supply rejection ratio unlike the two stage operational amplifier. The p-channel M1 and M2

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are the input driver transistors, M1A, M2A, M11 and M12 formed n-type cascode load devices, and M3A, M4A, M3 and M4 formed p-type cascode load devices. One important design point is that the dc current flowing through the cascode load (M3 and M4) should be designed never going to zero. If the current goes to zero, a delay is needed in turning these out of current transistors back on because of the parasitic capacitances that must be charged. To suppose the input differential voltage is large enough that transistor M1 turns off and M2 turns on, all of I3 flows through M2, resulting in I2=I3. If I5 is not greater than I3, then the current I4 will be zero. Thus, the value of I5 is normally between I3 and twice of I3 to avoid this delay problem.

The common-mode feedback (CMFB) circuit is needed for any fully-differential operational amplifiers. Without it the common-mode output remains undefined, and the amplifier will drift out of the high gain operating regime. The CMFB can be achieved by controlling the bias voltages of M11 and M12. The CMFB circuit comprises of transistors MCM1– MCM6, where the differential currents of two differential pairs (MCM1, MCM2 and MCM3, MCM4) flow into a current-mirror load MCM5, MCM6. The common-mode voltage is held at the reference potential VCM, which is usually analog ground in order to maximize output signal swing.

Finally, the amplifier is simulated using eldo simulator. The simulated frequency response of the fully differential operational amplifier in open-loop condition is shown in Fig. 2.5. The characteristic of the operational amplifier, such as the DC gain and the phase margin are found to be 61.55 dB and 79^o, respectively. The approximate gain bandwidth is found to be 4.3MHz, and the average power dissipation is about 2.3 mWatt.

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Figure 2.4 Circuit implementation of the fully-differential folded-cascode operational amplifier on glass substrate in a 3-μm LTPS technology.

Figure 2.5 The simulated frequency response of the fully differential operational amplifier in open-loop condition.

~ 27 ~ 2.2.2 Design of 1-bit Quantizer

This section presents the design of the 1-bit quantizer appropriate for use in conventional and delta-sigma converters. The schematic diagram of the quantizer is depicted in Fig. 2.6. It comprises of three parts as following. The first part is the differential input pair, M1 and M2. The second part is a latch circuit composed of a n-type flip-flop, M4 and M5, with a pair of n-type transfer gate, M8 and M9. There are also a p-type flip-flop, M6 and M7, with a pair of p-type precharge transistors, M10 and M11, and the transistor M12 is a switch for resetting. The third part is a latch composed of transistor M14-M21.

φ1 and φ2 are the two non-overlapping clocks as depicted in Fig. 2.7. The dynamic operation of this circuit can be divided into two intervals, reset time interval and regeneration time interval, respectively. During φ2, the comparator is in reset mode and transistors M8 and M9 isolate the p-type flip-flop from the n-type flip-flop.

After the input stage settles on its decision, a voltage which is proportional to the input voltage difference is established between node a and node b. Node c and node d are precharged to the power supply voltage by two closed transistor, M10 and M11. Transistors M20 and M21 are closed and transistors M14 and M15 are open, then two inverters are formed with transistors M16-M19. The output signal Q is injected into one inverter producing its complement which is injected into another inverter simultaneously. Thus, the output Q is forced to keep the previous state value by the followed SR latch. Any change in the input stage will not affect the output when the circuit is in the reset time interval.

The regeneration mode is initialized when transistor M12 is opening. The n-type flip-flop, together with the p-type flip-flop, regenerates the voltage differences between nodes a and b and between nodes c and d. Then, the voltage difference between node c and d is amplified to near the power supply voltage. The following

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SR latch is driven to full complementary digital output levels at the end of the regeneration mode. Thus, the polarity of the 1-bit quantizer is decided in the regeneration time interval and kept in the reset time interval.

Figure 2.6 Circuit implementation of the 1-bit quantizer on glass substrate in a 3-μm LTPS technology.

Figure 2.7 Time relation between φ1and φ2.

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Finally, the simulated result of the quantizer is shown in Fig. 2.8. It can successfully find out which of the two input nodes is higher and the result is shown in the output.

Figure 2.8 The simulated result of the 1-bit quantizer.

2.2.3 Design of D Flip-flop

The schematic diagram of the D flip-flop is shown in Fig. 2.9. This flip-flop requires only one clock, called a true-single-phase-clock (TSPC) flip-flop. As the input signal D is low, transistor M5 is closed as the clock signal (Clk) is low. Then the drain of transistor M5 is pulled to low and so is the output signal Q. Similarly, the output signal Q will be high as long as the input signal D is high in the Clk signal is in its rising edge. The simulated result of the D flip-flop is shown in Fig. 2.10.

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Figure 2.9 Circuit implementation of the D flip-flop on glass substrate in a 3-μm LTPS technology.

Figure 2.10 The simulated result of the D flip-flop.

~ 31 ~ 2.2.4 Summary

A first-order delta-sigma modulator is implemented by combining the operational amplifier, 1-bit quantizer, and the D flip-flop discussed above. The simulated results are shown in the following pictures, Fig. 2.11 – Fig. 2.14, with different input data.

By the section 2.2.1 and the foreword of section 2.2, the probability of ‘logic-1’

in the output bit stream of the delta-sigma modulator will be correctly equal to the input voltage ratio, x over the power supply voltage, where the variable x is the input signal used and shown in Fig 2.2. However, in this fully differential architecture of the delta-sigma modulator, the input voltage ratio should be modified into equation (2.7) as shown below.

Thus, different input voltage should produce different probability of ‘logic-1’ at the output of the modulator. As the input voltage Vi+ is 8V, the probability of ‘logic-1’

should be 0.8 calculated by equation (2.7).

In the mean time, the simulated results using the eldo simulator are shown in Fig.

2.11. The probability of ‘logic-1’ in one period is also calculated and listed in table 2.2, and which is equal to 0.808. That is, this circuit has worked successfully in this input situation. Next, different input situations have necessarily to be verified. Fig. 2.12 to Fig. 2.14 show that the simulated results of input signal Vi+ is 7V, 5V, and 3V, respectively. The probability of ‘logic-1’ in one period of these different three situations is calculated and tabled in table 2.3 to table 2.5 simultaneously. As the input signal Vi+ is 7V, the calculated probability result is 0.703. The input signal Vi+ are 5V and 3V, the calculated probability results are 0.5 and 0.293, respectively. By such calculation and simulation, this circuit is successfully verified by eldo simulator.

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Figure 2.11 The simulated result of the first-order delta-sigma modulator when the input Vi+ is 8V.

Cycle number of ‘logic-1’ in one period 207 cycles

Period 256 cycles

Probability of ‘logic-1’ in one period 0.808

Table 2.2 The probability of ‘logic-1’ in one period is calculated and listed as Vi+ is 8V.

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Figure 2.12 The simulated result of the first-order delta-sigma modulator when the input Vi+ is 7V.

Cycle number of ‘logic-1’ in one period 180 cycles

Period 256 cycles

Probability of ‘logic-1’ in one period 0.703

Table 2.3 The probability of ‘logic-1’ in one period is calculated and listed as Vi+ is 7V.

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Figure 2.13 The simulated result of the first-order delta-sigma modulator when the input Vi+ is 5V.

Cycle number of ‘logic-1’ in one period 128 cycles

Period 256 cycles

Probability of ‘logic-1’ in one period 0.5

Table 2.4 The probability of ‘logic-1’ in one period is calculated and listed as Vi+ is 5V.

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Figure 2.14 The simulated result of the first-order delta-sigma modulator when the input Vi+ is 3V.

Cycle number of ‘logic-1’ in one period 75 cycles

Period 256 cycles

Probability of ‘logic-1’ in one period 0.293

Table 2.5 The probability of ‘logic-1’ in one period is calculated and listed as Vi+ is 3V.

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Chapter 3

Decimation Filter for First-order Delta-sigma Modulator

3.1 Introduction

For a delta-sigma ADC, the delta-sigma modulator is operated with oversampling to produce 1-bit output stream in high data rate. However, the results of the modulator can’t represent the converting results of input analog signal directly. A decimation filter is thus needed to solve this problem. Decimation filter acts as a low-pass function to filter the signal outer the frequency band and decimate the output bit stream down to the Nyquist rate. This process changes the high sampling rate and low resolution digital signals into the high resolution digital signals. Then, the bit stream will be converted into 8-bit determined digital signals. In such case, a counter which is a finite-impulse-response (FIR) filter is used as a decimation filter to compute a running average of the output bit stream b[n] from the delta-sigma modulator and produce the 8-bit digital output. As the Fig. 3.1 shows, the input bit stream b[n] comes from the delta-sigma modulator discussed in chapter 2. Then, the decimation filter produces 8-bit output signal y[n]. The relation between bit stream b[n] and 8-bit digital signal y[n] and how a counter could be seen as a decimation filter are both discussed in the next section.

Figure 3.1 Diagram shows the input/output variables of the decimation filter.

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In such design, a counter is used to calculate the running average of the bit stream b[n] coming from the delta-sigma modulator and translate this message into the 8-bit digital code [18]. Thus, the output y[n] of the decimation filter can be expressed as a function of the bit stream b[n]. N numbers of successive data of b[n]

are summed up and then divided by N as shown in equation (3.1).

1

Then, the z-domain transfer function of equation (3.1) can be derived as equation (3.2). The variable H1 is used to represent the system of the decimation filter. The frequency response of this system can also be derived by substituting the variable z in equation (3.1) for the exponential equation with the index number is j2πf as expressed in equation (3.3). By observing this equation, this transfer function is composed by a sinc function divided by another one and why this circuit is termed as a Sinc filter can be figured out.

By equation (3.3) derived above, the amplitude of the transfer function can be analyzed in different frequency. It is close to 1 near zero frequency and it decays as frequency increases in the mean while. It represents a low-pass filter. However, the harmonic tones of that transfer function in equation (3.3) exist in high frequency.

These unexpected tones will contribute some noise to the delta-sigma ADC and cause this filter a non-ideal low-pass filter. Because of such problem, the noise in the output bit stream b[n] can be attenuated perfectly at only the certain frequencies. However, this filter used for the first-order delta-sigma modulator is adequate and very

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economic. Thus, a non-ideal low-pass filter is applied by using a counter to be the decimation filter. Besides, more calculating number would lead to the error decrease gradually, even though the counter results in some error.

3.2 Circuits Implementation on Glass Substrate

The block diagram of the decimation filter is shown in Fig. 3.2. It consists of a counter, a register, and a divider. At the beginning of a new conversion, the counter and the register are both reset. The input signal b[n] is coming from the front circuit (delta-sigma modulator) and injecting into the counter. The counter will count up as long as the b[n] is ‘logic-1’ when the clock (Clk) is in the rising edge. Fig. 3.3 shows its timing chart. Once in every N clock cycles, the output of the counter is clocked into a register. In the mean time, the divider will produce the Clk_N signal to reset the counter. Thus, the output y[n] is down-sampled and represented in digital code. The counter produces k-bit output if N=2^k, which may be interpreted as a binary fraction between 0 and 1. In this case, N is chosen as 256 for 8-bit digital output.

Next, the circuit implementation of the three parts of the decimation filter, the counter, the register, and the divider is discussed in the following section.

Figure 3.2 Block diagram of decimation filter composed of a counter, register, and a divider.

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Figure 3.3 The timing chart represents the relation between the Clk, Clk_N, and the output signal y of the decimation filter.

3.2.1 Design of the Counter

At first, the design of the counter is demonstrated. However, the JK flip-flop needs to be discussed before how to design the counter. The JK flip-flop is the most widely used flip-flop because of its versatility and its block diagram is shown in Fig.

3.4.

Figure 3.4 The circuit implementation of the JK Flip-flop which comprises of some logic gates and two SR_latches.

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The JK flip-flop consists of four AND gates, one inverter, and two SR_latches. It is obviously a master/slave structure. As the Clk signal is high, the front part of the JK flip-flop is on. If the input signals J and K are both high, the front SR_latch is controlled only by the signal which is feeding back from the output. If the output signal of the JK flip-flop, Q, is high, the input signal of the front SR_latch (S, R) is (0, 1). Hence, it drives the output of the front SR_latch (Q, Qb) becoming (0, 1). Then, as the Clk signal goes low, the output signal of the rear SR, Q, which is also the output signal of the JK flip-flop, is driving low. Thus, it is transformed into its complement.

Another example is given as J and K are both low. In such case, the input signal of the front SR_latch (S, R) are both low no matter what the output signal fed back is. Thus, the output signal of the front latch will keep the value equal to its previous state.

Similarly, as the Clk signal goes low, the signal coming from the front part will influence the rear part of the JK flip-flop. Then, its output signal is contained as its previous state. Besides, this JK flip-flop is obviously a negative edge trigger structure by the above deriving, and the Clr signal is used to reset this circuit. The discussion above is also demonstrated as the truth table in the table 3.1, and that two cases are mainly used in this application.

J K Q(t+1)

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The block diagram of the counter is shown in Fig. 3.5. The counter contains 8 JK flip-flops whose input signal J and K are combined together. As the input J and K are both high, the output Q of that JK flip-flop will toggle. On the contrary, if J and K are both low, the output Q of that JK flip-flop will keep the previous state value. As the Fig. 3.5 shows, the input of the LSB JK flip-flop is b[n] produced by the delta-sigma modulator, and it is negative edge triggered by the Clk signal. The inputs of the other 7 JK flip-flops are all ‘1’ driven by the power supply voltage, and all of them are negative edge triggered by the previous stage output. Then, the output of the counter, c0-c7, are produced and also shown in Fig. 3.5.

Fig. 3.6 shows the timing chart of this counter as b[n] is high and the initial value of c0, c1, and c2 are all low (where this only least 3 significant bits are shown). As long as the Clk is going to low, c0 is toggled. Similarly, every time when c0 is going to low, c1 is toggled. The like c2-c7 will be produced similarly. Observing this operation shown in Fig. 3.6, it can be found that the output of the counter is counted up and represented as 8-bit digital code.

Figure 3.5 The block diagram of the counter built up with the JK Flip-flop and controlled by the Clk and Clr signals where the input signal is b[n] and the output signal is c0-c7.

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Figure 3.6 The timing chart of the counter as b[n] is high where the only least 3 significant bits are shown.

Otherwise, as long as b[n] is low, the least significant JK flip-flop will keep its output data c0. That is no negative edge will be found in c0, and all other outputs are the same. Thus, the 8-bit digital output will be kept as b[n] is low and counted up as b[n] is high in 256 cycles. Its output will be kept in the 8-bit register which is

illustrated in section 3.2.2 and then the counter will be reset and controlled by the divider circuit discussed in section 3.2.3.

3.2.2 Design of the Register

The register is used to keep the value calculated by the counter and the counter is just able to calculate next 256 data in the next time. Fig. 3.7 shows the block diagram of the register which consists of 8 D flip-flops, and the register is positive edge triggered by the Clk_N signal which is produced by the divider and will be discussed in the next section.

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Figure 3.7 The block diagram of the register which consists of 8 D flip-flops which is positive edge triggered by the Clk signal.

3.2.3 Design of the Divider

The block diagram of the divider is shown in Fig. 3.8. The divider uses 8 D flip-flops as an inherent counter. The least significant D flip-flop is positive edge triggered by Clk and then reflects the input on the output. However, the input signals of all of the flip-flops are fed back by their own output, and specially is the complementary one (Qb). Thus, every time the Clk is going to high, q0 which is the least significant bit of this counter is toggled. At the same time, q0 is also the signal used to trigger the next D flip-flop, and q1 will toggle as long as q0 is going to high.

This operation is just like the counter discussed above; however, the counter here is a down-counter on the contrary and the output q0-q7 is counted down from 255 to 0 again and again. The timing chart of such divider is shown in Fig. 3.9. However, all of

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q4, q5, q6, and q7 have the same waveform; therefore, all of them are shown together.

As long as the counter here is counted to 0, the divider will produce a pulse in the output Clk_N by these 7 logic gates. Clk_N is used to reset the counter shown in section 3.2.1 and to trigger the 8-bit register.

Figure 3.8 The block diagram of the divider which consists of 8 D flip-flops.

~ 45 ~ Figure 3.9 Timing chart of the divider.

3.2.4 Summary

The timing chart of the decimation filter is summarized and showed in Fig. 3.10,

The timing chart of the decimation filter is summarized and showed in Fig. 3.10,