Design of D Flip-flop

The schematic diagram of the D flip-flop is shown in Fig. 2.9. This flip-flop requires only one clock, called a true-single-phase-clock (TSPC) flip-flop. As the input signal D is low, transistor M5 is closed as the clock signal (Clk) is low. Then the drain of transistor M5 is pulled to low and so is the output signal Q. Similarly, the output signal Q will be high as long as the input signal D is high in the Clk signal is in its rising edge. The simulated result of the D flip-flop is shown in Fig. 2.10.

~ 30 ~

Figure 2.9 Circuit implementation of the D flip-flop on glass substrate in a 3-μm LTPS technology.

Figure 2.10 The simulated result of the D flip-flop.

~ 31 ~ 2.2.4 Summary

A first-order delta-sigma modulator is implemented by combining the operational amplifier, 1-bit quantizer, and the D flip-flop discussed above. The simulated results are shown in the following pictures, Fig. 2.11 – Fig. 2.14, with different input data.

By the section 2.2.1 and the foreword of section 2.2, the probability of ‘logic-1’

in the output bit stream of the delta-sigma modulator will be correctly equal to the input voltage ratio, x over the power supply voltage, where the variable x is the input signal used and shown in Fig 2.2. However, in this fully differential architecture of the delta-sigma modulator, the input voltage ratio should be modified into equation (2.7) as shown below.

Thus, different input voltage should produce different probability of ‘logic-1’ at the output of the modulator. As the input voltage Vi+ is 8V, the probability of ‘logic-1’

should be 0.8 calculated by equation (2.7).

In the mean time, the simulated results using the eldo simulator are shown in Fig.

2.11. The probability of ‘logic-1’ in one period is also calculated and listed in table 2.2, and which is equal to 0.808. That is, this circuit has worked successfully in this input situation. Next, different input situations have necessarily to be verified. Fig. 2.12 to Fig. 2.14 show that the simulated results of input signal Vi+ is 7V, 5V, and 3V, respectively. The probability of ‘logic-1’ in one period of these different three situations is calculated and tabled in table 2.3 to table 2.5 simultaneously. As the input signal Vi+ is 7V, the calculated probability result is 0.703. The input signal Vi+ are 5V and 3V, the calculated probability results are 0.5 and 0.293, respectively. By such calculation and simulation, this circuit is successfully verified by eldo simulator.

~ 32 ~

Figure 2.11 The simulated result of the first-order delta-sigma modulator when the input Vi+ is 8V.

Cycle number of ‘logic-1’ in one period 207 cycles

Period 256 cycles

Probability of ‘logic-1’ in one period 0.808

Table 2.2 The probability of ‘logic-1’ in one period is calculated and listed as Vi+ is 8V.

~ 33 ~

Figure 2.12 The simulated result of the first-order delta-sigma modulator when the input Vi+ is 7V.

Cycle number of ‘logic-1’ in one period 180 cycles

Period 256 cycles

Probability of ‘logic-1’ in one period 0.703

Table 2.3 The probability of ‘logic-1’ in one period is calculated and listed as Vi+ is 7V.

~ 34 ~

Figure 2.13 The simulated result of the first-order delta-sigma modulator when the input Vi+ is 5V.

Cycle number of ‘logic-1’ in one period 128 cycles

Period 256 cycles

Probability of ‘logic-1’ in one period 0.5

Table 2.4 The probability of ‘logic-1’ in one period is calculated and listed as Vi+ is 5V.

~ 35 ~

Figure 2.14 The simulated result of the first-order delta-sigma modulator when the input Vi+ is 3V.

Cycle number of ‘logic-1’ in one period 75 cycles

Period 256 cycles

Probability of ‘logic-1’ in one period 0.293

Table 2.5 The probability of ‘logic-1’ in one period is calculated and listed as Vi+ is 3V.

~ 36 ~

Chapter 3

Decimation Filter for First-order Delta-sigma Modulator

3.1 Introduction

For a delta-sigma ADC, the delta-sigma modulator is operated with oversampling to produce 1-bit output stream in high data rate. However, the results of the modulator can’t represent the converting results of input analog signal directly. A decimation filter is thus needed to solve this problem. Decimation filter acts as a low-pass function to filter the signal outer the frequency band and decimate the output bit stream down to the Nyquist rate. This process changes the high sampling rate and low resolution digital signals into the high resolution digital signals. Then, the bit stream will be converted into 8-bit determined digital signals. In such case, a counter which is a finite-impulse-response (FIR) filter is used as a decimation filter to compute a running average of the output bit stream b[n] from the delta-sigma modulator and produce the 8-bit digital output. As the Fig. 3.1 shows, the input bit stream b[n] comes from the delta-sigma modulator discussed in chapter 2. Then, the decimation filter produces 8-bit output signal y[n]. The relation between bit stream b[n] and 8-bit digital signal y[n] and how a counter could be seen as a decimation filter are both discussed in the next section.

Figure 3.1 Diagram shows the input/output variables of the decimation filter.

~ 37 ~

In such design, a counter is used to calculate the running average of the bit stream b[n] coming from the delta-sigma modulator and translate this message into the 8-bit digital code [18]. Thus, the output y[n] of the decimation filter can be expressed as a function of the bit stream b[n]. N numbers of successive data of b[n]

are summed up and then divided by N as shown in equation (3.1).

1

Then, the z-domain transfer function of equation (3.1) can be derived as equation (3.2). The variable H1 is used to represent the system of the decimation filter. The frequency response of this system can also be derived by substituting the variable z in equation (3.1) for the exponential equation with the index number is j2πf as expressed in equation (3.3). By observing this equation, this transfer function is composed by a sinc function divided by another one and why this circuit is termed as a Sinc filter can be figured out.

By equation (3.3) derived above, the amplitude of the transfer function can be analyzed in different frequency. It is close to 1 near zero frequency and it decays as frequency increases in the mean while. It represents a low-pass filter. However, the harmonic tones of that transfer function in equation (3.3) exist in high frequency.

These unexpected tones will contribute some noise to the delta-sigma ADC and cause this filter a non-ideal low-pass filter. Because of such problem, the noise in the output bit stream b[n] can be attenuated perfectly at only the certain frequencies. However, this filter used for the first-order delta-sigma modulator is adequate and very

~ 38 ~

economic. Thus, a non-ideal low-pass filter is applied by using a counter to be the decimation filter. Besides, more calculating number would lead to the error decrease gradually, even though the counter results in some error.

3.2 Circuits Implementation on Glass Substrate

The block diagram of the decimation filter is shown in Fig. 3.2. It consists of a counter, a register, and a divider. At the beginning of a new conversion, the counter and the register are both reset. The input signal b[n] is coming from the front circuit (delta-sigma modulator) and injecting into the counter. The counter will count up as long as the b[n] is ‘logic-1’ when the clock (Clk) is in the rising edge. Fig. 3.3 shows its timing chart. Once in every N clock cycles, the output of the counter is clocked into a register. In the mean time, the divider will produce the Clk_N signal to reset the counter. Thus, the output y[n] is down-sampled and represented in digital code. The counter produces k-bit output if N=2^k, which may be interpreted as a binary fraction between 0 and 1. In this case, N is chosen as 256 for 8-bit digital output.

Next, the circuit implementation of the three parts of the decimation filter, the counter, the register, and the divider is discussed in the following section.

Figure 3.2 Block diagram of decimation filter composed of a counter, register, and a divider.

~ 39 ~

Figure 3.3 The timing chart represents the relation between the Clk, Clk_N, and the output signal y of the decimation filter.