1.1 Video Display System Overview
PC RGdigitaldigita
l
Bdigital
CKp CKp
RGdigitaldigita
l
Bdigital
Fig. 1.1 Video display system
The simplified video display system is shown in Fig. 1.1 [1], the RGB (Red/Green/Blue) analog signal, Vertical Synchronous clock (Vsync), and Horizontal Synchronous clock (Hsync) are sent from Random Access Memory Digital-Analog Converter (RAMDAC) of Personal Computer (PC) to the RGB acquisition interface.
The RGB signal has been converted to digital domain from Variable Gain Amplifier (VGA), Analog-to-Digital Converter (ADC) in RGB acquisition interface, and the Pixel Clock (CKp) is also generated by it. Then the digital RGB signal can be computed in the following digital processes.
The clock for ADC to sample analog data to digital is generated from a clock generator which is usually composed of a Phase-Lock Loop (PLL), and the high speed pixel clock (CKp) is produced according to the setting of display quality, and is aligned
to the Hsync. The multiplication factor between Hsync and pixel clock is proportion to the display horizontal resolution which is defined according to the display specifications in video electronics standards association (VESA). That means the display resolution has to be improved for the quality of display.
Table 1.1 Monitor timing specification
As shown in the Table 1.1, the multiplication factor of the clock generator in video system applications is very large, for example, 2160 in UXGA. The input frequency is very low, for example, 75kHz Horizontal frequency in UXGA. Besides, the range of pixel frequency is from 25MHz to 229.5MHz which is difficult for designers to realize an oscillator to cover such wide range. The stability of PLL loop is not good in this situation in traditional design, and the output jitter is also not easy to be controlled.
Fig. 1.2 Video analog signal vs. sampling clock diagram
Besides, the high speed pixel clock has to be aligned to Hsync, otherwise an ambiguous signal will be sampled. The relationship between phase of pixel clock and analog RGB signal is shown in Fig. 1.2. The edges of pixel clock have to be located in static signal region, otherwise the converted digital signals would be ambiguous which result in blurry display image.
However, the input of clock generator Hsync comes in with high noise and low frequency pulse. How to improve the loop stability in large multiplication and low input frequency, and align the phase of a highly noisy Hsync clock become the main considerations of video capture clock generator design.
Vsync Vback Vdisplay(N Hsync cycles) Vfront Vsync
Vsync Vback Vdisplay(M pixel clocks) Vfront Vsync Vsync
Hsync Video Data
Hsync Pixel Clock Video Data
Fig. 1.3 Relationship between V/Hsync and pixel clock
The relationship between Vsync, Hsync, and Pixel clock is shown in Fig. 1.3. The Hsync clock string is generated by Vsync, and the Pixel clock is generated by Hsync.
The video data is sampled by pixel clock and converted to digital domain by ADC. The display resolution directly corresponds to the multiplication factor M and N.
1.2 Motivation
The main targets of the clock generator for video application are tracking the phase of a highly noisy and low frequency HSYNC from the display-card, and generating the high speed pixel clock, with large multiplication factor from 800 to 2160 times [1].
Some analog approaches are proposed to accomplish these targets. For example, an architecture which separates the frequency and phase operation into two loop filters [2] is proposed to help phase tracking and to meet the specification. The second example of PLL for video application employs 3 PLLs, an internal PLL is used to generate a 5-phase 660MHz extra high frequency clock from an additional crystal as a high precision time resolution [3], and then it utilizes a high-precision 28-bit digital frequency synthesizer to generate an output clock. The third example applies a 2-stage cascaded PLL to overcome the low-rate input clock [4]. However, those analog approaches often result in larger power consumption, long lock-in time. Furthermore, because of the small input frequency, the loop filters (LPF) of analog PLL need external RC components.
Some digital approaches are also realized for this application. A DLL-based clock generator with analog variable delay cell and charge pump is proposed to accomplish the specification [5]. Another example of a digital PVT tolerant PLL for large
multiplication frequency synthesizer employs a digital controller, DAC, and VCO [6].
Both the digital controlled clock generator designs utilize the customized analog oscillator for high resolution in frequency to overcome the difficulty of large multiplication design.
From the development of CMOS process, a cell-based all-digital PLL has become more and more popular because of high integration in SOC design, good immunity against switching noise, better portability for technology scaling, and low leakage current in advanced process.
In this thesis, a cell-based all-digital PLL circuit for video application with large multiplication is proposed. The main target is to accommodate to the current monitor timing specifications [7]. This chip is implemented in a 0.18μm 1p5m 1.8v/3.3v standard CMOS process. The chip area is 1000×1000μm2, and the power consumption is 6.65mW at 6MHz input clock, 192MHz output clock.
1.3 Thesis Organization
This thesis is arranged as follow. In chapter 2, the surveys of video application PLL and the design challenges are described. In chapter 3, all the details of the proposed ADPLL clock generator, including the circuit architecture, functional blocks, control algorithm, and block simulation results are presented. The chip implementation and overall simulation results are reported in chapter 4. Finally, we make conclusions and discuss future work in chapter 5.