Working Principle

In TDC-loop, the phase error is quantified by TDC, and then the PLL controller tunes the DCO-code according to TDC-code for the phase error compensation caused by instant HSYNC jitter. Besides, the TDC-code is only used to influence DCO-code once, and it will not change the average frequency. Therefore, the TDC-loop compensates large HSYNC jitter at once, and avoids instability caused by input noise injection.

Fig. 3.23 A PLL with TDC loop working principle

Fig. 3.23 shows the working principle of TDC. The phase drift is detected by PFD and quantified by TDC to TDC-code. The TDC-code is multiplied by TDC-loop-gain and sent into SDM-DCO. Then the tuning-code will be averagely scattered over the flowing pixel clock by SDM. For this reason, before the next HSYNC rising-edge, the phase error caused by HSYNC jitter this time has been compensated.

3.5.2 Structure

(a)

(b)

Fig. 3.24 TDC structure [15]

TDC structure is shown in Fig. 3.24. Because of the performance of input jitter compensation is strongly dependent on the TDC resolution, a traditional TDC [15] is used in the proposed ADPLL.

For the lead and lag information, two duplicate TDC is used, the advantages of this structure are small resolution and small dead zone. The simulation result is listed in the Table tdc_performance. In SS corner, the resolution is 100ps, and the dead zone of detection is 190ps.

Table 3.2 Summary of the TDC performance

resolution dead zone range

SS 100ps <190ps can’t be detected 6400ps

FF 44ps <70ps can’t be detected 2816ps

3.5.3 Simulation Result

3.5.3.1 Discussion of Time-to-Digital Converter Loop

In Fig. 3.25 left half, the x axis is the input jitter and the y axis is the phase error (ns). The simulation without TDC is shown in the left half of Fig. 3.25 (a), the phase error reaches 6ns at 1.2ns jitter. The simulation with TDC is shown in the left half of Fig.

3.25 (b), the phase error is reduced to 1.6ns at the same case.

The percentage of ideal pixel clock period versus input jitter is shown in the right half of Fig. 3.25 (a) and Fig. 3.25 (b). Since the period of ideal pixel clock in UXGA mode is only 6.173ns, the phase error have to be smaller than 33% of ideal pixel clock period. From the simulation result, the performance in UXGA mode and 1.2ns input jitter is reduced from 80% to 22 % by adding the TDC loop.

0 0.2 0.4 0.6 0.8 1 1.2 1.4

TDC off HYSNC and HSOUT Phase Drift over jitter

jitter(ns)

Phase Drift [% of output clock ]

VGA(800)

6 TDC off HYSNC and HSOUT Phase Drift over jitter

jitter(ns)

(a) Simulation without TDC, the maximum phase drift is 6ns (78%)

0 0.2 0.4 0.6 0.8 1 1.2 1.4

1.8 TDC on HYSNC and HSOUT Phase Drift over jitter

jitter(ns)

TDC on HYSNC and HSOUT Phase Drift over jitter

jitter(ns)

Phase Drift [% of output clock ]

VGA(800) SVGA(1056) XGA(1344) SXGA(1688) UXGA(2160)

(b) Simulation with TDC, the maximum phase drift is 1.6ns (22%)

Fig. 3.25 Simulation the phase error of PLL with and without TDC in VGA to UXGA The detailed simulation data is listed in Table 3.3. The column represents different input jitter (0ps ~ 1.2ns) and the row represents different view modes (VGA to UXGA).

The shadowed statics are simulated without TDC-loop and the unshadowed ones are simulated with TDC-loop and the unit is in percentage.

Table 3.3 Phase Error in Different Operation Modes (phase error unit: %)

% VGA SVGA XGA SXGA UXGA

0.3348 0.6242 1.5470 3.4938 2.6730 Jitter

0ps 0.1158 0.1120 0.0910 0.8262 0.9639

1.8114 2.9731 6.5422 11.0106 19.9422 Jitter

200ps 0.7527 1.4045 2.1612 3.0564 4.6656

4.7329 8.7713 12.0672 19.3752 31.0716 Jitter

500ps 1.7132 2.3729 3.6367 6.2424 9.5742

10.8077 13.2890 26.4354 34.8192 63.3744 Jitter

1000ps 3.4012 5.0859 7.2345 11.5398 18.0711

14.6494 18.3709 31.6484 53.1036 78.1002 Jitter

1200ps 4.0809 6.2163 9.2397 12.8628 21.6270

3.5.3.2 Discussion of TDC Loop Gain

The result in the above section is simulated on the basis of ideal TDC gain.

However, in reality, the TDC resolution and the DCO resolution are both affected by PVT variation. The simulation below is to discuss the effect of non-ideal TDC gain.

The ideal TDC gain is calculated as follow,

IdealPixelPeriod=CoarseResolution CoarseCode+FineResolution FineCode+Epixel Epixel Multiplication=Ehsync=TdcResolution TdcCode+

Ehsync 1 TdcCode TdcResolution

TuneCode=

From the equation above, Epixel is the difference between ideal pixel clock period and DCO clock period and then Ehsync is amplified from Epixel by multiplication factor. Etdc is the difference between actual phase error and TDC detected phase drift.

If the Ehsync (actual phase error) can be uniformly scattered over the flowing pixel clock period, the Ehsync can be almost eliminated (except for Etdc) before next HSYNC rising-edge.

However, the TDC delay-cell is different from DCO delay-cell so the DCO-code cannot be adjusted by TDC-code directly. The best DCO tuning-code has to be converted from TDC code. The relation between best tuning code and TDC code is calculated in the equation, and the Etdc is ignored.

The ideal TDC gain is decided by TDC-resolution, DCO-resolution and Multiplication-factor. The multiplication-factor is a constant (decided by view-mode) but the resolution of DCO and TDC are changed in PVT variation. In the following simulation, the assumptions are 4ps DCO resolution, 100ps TDC resolution, 6bits fractional code, and the ideal TDC gain being around 1~2 as listed in Table 3.4.

Table 3.4 Ideal TDC Gain for Different Operation Mode TDC resolution 100ps, fine tune resolution 4ps/64

Mode VGA(800) SVGA XGA SXGA UXGA(2160)

Ideal gain 2 1.56 1.19 0.95 0.76

In order to verify the influence of TDC-gain, a PLL model is established in MATLAB, and simulations with different jitter models and different TDC-gain are made. In the following simulations, ratio factor is defined by the variation rate of HSYNC jitter. HSYNC jitter varies fast with small ratio factor, and vice versa. The equation of ratio factor is given by

ratio= fs fm

HSYNC Jitter=Pk-Pk Input Jitter sin(2π fm # of period)× × ×

In the equation, fs is defined as sampling frequency used in MATLAB simulation.

0 2 4 6 8 10

Fig. 3.26 Example of HSYNC jitter models

In Fig. 3.26, the x axis is the numbers of HSYNC period and the y axis is the period of HSYNC. The HSYNC period varies fast in ratio1.7 and varies slow in ratio 8.7. The peak-to-peak jitters of two conditions are the same, but the cycle-to-cycle jitter of ratio1.7 is much bigger than that of ratio 8.7.

0 5 10 15 20 25 30 35 40 45 50

TDCnoM PhaseError(p-p)=+-7.067(ns) gain=0.0 ratio=19.7

HSYNC jitter

TDCnoM PhaseError(p-p)=+-3.402(ns) gain=0.0 ratio=10.7

HSYNC jitter

TDCnoM PhaseError(p-p)=+-2.674(ns) gain=0.0 ratio=8.7

HSYNC jitter HSOUT jitter Phase Drift Filter output jitter

(c) ratio=8.7

Fig. 3.27 Simulation without TDC

Fig. 3.27 shows the simulation of ADPLL loop jitter performance without TDC-loop. The peak-to-peak value of HSYNC jitter is set to ±1.2ns in all simulations, and the ratio is set to 19.7, 10.7 and 8.7 respectively in (a), (b) and (c). In the Fig., the circle marked line is HSYNC jitter, the upward-pointing triangle marked line is

HSOUT jitter, the asterisk marked line is phase error between HSYNC and HSOUT, and the point marked line is the output jitter of digital loop filter.

The simulation results show that when the HSYNC jitter varies more slowly, the accumulated phase error is larger. The phase error is up to ±7.076ns when ratio is equal to 19.7, and phase error is ±2.674 when ratio is 8.7.

TDCnoM PhaseError(p-p)=+-0.957(ns) gain=0.5 ratio=2.7

HSYNC jitter

TDCnoM PhaseError(p-p)=+-1.766(ns) gain=0.5 ratio=19.7

HSYNC jitter

TDCnoM PhaseError(p-p)=+-1.309(ns) gain=1.0 ratio=2.7

HSYNC jitter

TDCnoM PhaseError(p-p)=+-1.103(ns) gain=1.0 ratio=19.7

HSYNC jitter

TDCnoM PhaseError(p-p)=+-1.964(ns) gain=2.0 ratio=2.7

HSYNC jitter

TDCnoM PhaseError(p-p)=+-1.239(ns) gain=2.0 ratio=19.7

HSYNC jitter HSOUT jitter Phase Drift Filter jitter

(c) gain=2.0

Fig. 3.28 Simulation with different TDC gain and different HSYNC jitter ratio Fig. 3.28 shows the discussions of phase drift with different TDC gain and different HSYNC jitter ratio. The ADPLL phase error performance is simulated in different TDC gain, which are (a) 0.5 times, (b) 1 times, and (c) 2 times of ideal TDC gain respectively. The Fig.s in the left are simulated with 2.7 ratio factor (fast rate of jitter variation), and the ratio factor in the right half of the Figures are set to 19.7 (slow rate).

From the simulation result, when the HSYNC jitter varies slowly, the performance of ADPLL with larger TDC gain is better than which with the smaller ones. However, when the HSYNC jitter varies fast, the ADPLL with the smaller TDC gain is better.

Hence, when the HSYNC with same direction occurs successively, the accumulation of phase drift can be restrained by TDC loop. But when the HSYNC jitter varies between plus and minus rapidly, there is no contribution for the phase error of the TDC loop.

Fortunately, there is not much accumulation of phase error in this case.

0 5 10 15 20

pp phase error (ns)

ratio

HSYNC jitter=1.20ns pp, filter tank=8 Peak to Peak Phase Error VS. ratio

gain=0.0 gain=0.5 gain=1 gain=2

Fig. 3.29 Phase error vs. HSYNC jitter ratio with different TDC gain

The Fig. 3.29 shows the peak-to-peak phase error versus ratio with different TDC gain. From the results, in the large ratio situation, the accumulation of phase error can be reduced by ADPLL loop with large TDC gain. However, in the small ratio situation, additional phase error is introduced by large TDC gain. Therefore, a suitable TDC gain is important to the performance of input jitter compensation.

0 5 10 15 20 25 30 35 40 45 50 -1

-0.5 0 0.5 1

jitter (ns)

# of period

HSYNC from computer, SXGA mode, period pp=+-0.950ns

Fig. 3.30 Measurement of the practical HSYNC jitter

In order to find a suitable TDC gain, a real HSYNC jitter is measured from PC through D-sub probe and shown in Fig. 30. We use discrete Fourier transform to find the correspond ratio, and simulate in the MATLAB ADPLL model, a better performance is achieved when TDC gain about 0.5~1.