Dithering Technique

3.4.1 Dithering Theorem

P1+n2 Δ n1+n2

×

Fig. 3.17 Dithering technique enhances period resolution

Fig. 3.17 shows how the use of high rate clock improves the equivalent DCO resolution [11][12]. The x axis is the DCO period and the y axis is time. Here, n1 cycles of period P1 and n2 cycles of period P1+Δ are mixed in one HSOUT period. The equivalent pixel clock period is given by P1 n1+(P1+Δ) n1

n1+n2

× ×

= n2 Δ

P1+n1+n2

× . The

equivalent resolution is improved from Δ to

n1+n2

Δ by mixing P1 and P1+Δ.

HSYNC

Fig. 3.18 Phase error reduction by dithering technique

Fig. 3.18 shows how to use over-sampling method to reduce the phase error. For example, the multiplication factor in the Figure is M, and DCO resolution is Δ. Assume the cycle of Ideal pixel clock is T + Δ / 2. In one HSYNC cycle, if all the periods of M pixel clock cycles are T, the phase error is accumulated to M×∆/2. If the periods of pixel clock are controlled by high-speed clock, that is, HSOUT is formed with a mix of T and T + Δ pixel clock periods, and then the phase error is controlled under Δ/2.

From the figure, another key point is that the high-speed pixel clock controller should averagely separate two kinds of different periods to minimize the pixel clock Phase error accumulation.

In order to reduce the complexity of circuits, Sigma-Delta Modulator (SDM) is applied to realize the dithering of DCO period.

3.4.2 Sigma Delta Modulator Overview

SDM is widely used in over-sampling data converter for its capability to push noise to high frequency. Then, the quantization noise can be removed by low pass filter.

For ADC application, analog input is converted to digital output with enhanced resolution after passing through the sigma delta modulator. In a sufficiently long time period, the average of digital output will be much closer to the value of the analog input than that in an ADC without SDM. In Fractional-N PLL application, the multiplication factor can be considered as over-sampling a DC analog signal. For example, a non-integer multiplication factor of frequency can be generated by more than one divide ratio dithering at over-sampling rate.

In this design, a SDM is applied to dither the DCO control code to minimize the phase error in phase tracking procedure. Since the multiplication factor of Video Capture PLL is from 800~2160, this architecture intrinsically produces a clock in slow rate and a clock in high rate. This characteristic of Video Capture PLL is used to improve the DCO equivalent resolution by sampling slow rate signal by high rate clock.

Fig. 3.19 First-order SDM Structure

A first order SDM is shown in Fig. 3.19 [13]. The ∆ block is digital differential block and ∑ block is digital integration. Inside the block, Z^-1 is the digital delay cell. A

delayed y signal is sent into ∆ block to generate the difference between output y and input x, then v is generated from ∑ block by integrating the difference. After v is quantified by the quantification, output y is refreshed.

From the discussion in time domain

( ) ( 1) ( 1) ( )

x n −y n− +v n− =v n

When n is substituted for 1, 2, 3, to N, the equations are generated below (1) (0) (0) (1)

The equation below is generated by summing up the equations above

1

From the assumption of x is a slow rate signal, and v converges all the time, the approximate equation is generated below.

1

Sigma delta modulator improves the equivalent resolution in digital application, but it requires another high speed over-sampling clock. In the video capture ADPLL application, the large multiplication factor provides a high over-sampling ratio (OSR) and over-sampling rate in nature. The enhancement of equivalent resolution can be achieved with no penalty.

3.4.3 Sigma Delta Modulator Structure and Working Principle

Fig. 3.20 Modified first-order SDM

In the proposed Video Capture PLL, a modified first order SDM is applied, as shown in Fig. 3.20, so that the area of SDM can be reduced in this structure and the cycle-to-cycle jitter can be minimized.

Fig. 3.21 The working principle of SDM [11]

The working principle of SDM is shown in Fig. 3.21. After Fine & Fraction SAR State, the fractional code is generated from PLL controller which is triggered by slow-rate phase clock, and then sent into the SDM which is triggered by high-rate pixel

clock. After that, SDM generates a series of high-rate changing integer codes according to the fraction code and is used to control the DCO so the non-integer DCO resolution can be performed.

3.4.4 Simulation Result

Fig. 3.22 shows the simulations of the jitter performance with the assumptions of 1ps DCO resolution and ideal input HSYNC clock (no input jitter). Simulations with 0 bits, 5 bits, 6 bits fractional codes are shown respectively.

0 200 400 600 800 1000 1200

-80

80 UXGA HYSNC and HSOUT: Phase Drift Over Time

Time Index

Phase Drift (ns)

(a) 0 bits fractional code

0 200 400 600 800 1000 1200

-2

2 UXGA HYSNC and HSOUT: Phase Drift Over Time

Time Index

Phase Drift (ns)

(b) 5 bits fractional code

0 200 400 600 800 1000 1200

0.2 UXGA HYSNC and HSOUT: Phase Drift Over Time

Time Index

Phase Drift (ns)

(c) 6 bits fractional code

Fig. 3.22 Simulation with different fractional code bits

Table 3.1 Summary of peak-to-peak phase drift in different fractional code bits

0 bits 5 bits 6 bits

Peak-to-Peak Phase drift (ns) ±67.406 ns ±1.573 ns ±0.165 ns From the simulation, the performance of phase drift is ±67.406 ns with 0 bits fractional code, ±1.573 ns with 5 bits, and ±0.165 ns with 6bits, as shown in Table 3.1.

The phase drift is improved by adding the fractional bit counts substantially, that is, when the fractional bit counts are increased, the equivalent resolution is better.