Chapter 5 Proposed Algorithm
5.2 Luminance Scaling
The original CBCS algorithm [10] is used in the second phase. The affined linear transformation of a pixel pL can be parameterized by
,
The image quality is defined by
),
0, 0
and PDF(x) is the probability density function of pixel value x. The RGB backlights are scaled simultaneously by a factor bL such that no more color shift will be introduced. Since the ratio between the RGB is fixed, this phase is called luminance scaling. The following LED power equation is used.
PR(bLbR)+PG(bLbG)+PB(bLbB) (5-6)
The objective function is to find the optimal gl, gu, and bL that minimize Equation (5-6) subject to the given image quality constraint FC.
Sample transfer functions of chromaticity and luminance scaling are shown in Figure 5-3.
Figure 5-3. Transfer functions of chromaticity and luminance scaling.
5.3 Summary
In our algorithm, the chromaticity scaling is employed to find the maximum power consumption which can be saved in an image while the color difference ∆E is determined. We reduce the backlight intensity by using the results of chromaticity scaling.
Luminance scaling uses CBCS algorithm. The transfer function changes the pixel data for compensating the luminance loss while the backlight intensity is reduced. The algorithm is the foundation that constructing a platform of the low power display.
0 x
Chapter 6
Prototype
6.1 Framework
For implementing our algorithms of backlight scaling, a prototype of experimental platform is necessary. Unfortunately, it is too difficult to get an appropriate hardware for matching the portable electronic device. Furthermore, the structure and optical mechanism of the portable electronic device can be easily shifted or damaged after the panel refitted.
Therefore, it is critical to determine a prototype to overcome these difficulties.
Figure 6-1. Backlight scaling of portable electronic device.
The design of our prototype is changed from the portable electronic device system (small size panel) to the laptop computer system (large size panel) through the support of CPT Corporation. Because our purpose is to reduce the power consumption of the TFT-LCD backlight, this switch has no influence on our implementation. There are several benefits in this switch. A ready hardware (FPGA board) from the support of CPT Corporation can be used to design this prototype. Refitting the large size panel is easier than refitting the small ones for us. Moreover, for a panel manufacturer, they can apply the technology of large size
panel to the small size panel readily. The power consumption of the LCD backlight can be measured more conveniently.
In our framework, the backlight scaling algorithm is realized in a Field Programmable Gate Array (FPGA) board. The FPGA board is used for image processing and backlight controller, which connects the TFT-LCD and the personal computer. The TFT-LCD displays the images before/after the backlight scaling process with the FPGA, while we measure the power consumption of TFT-LCD backlight.
Figure 6-2. Our notion of backlight scaling.
6.1.1 Image Processing Flow
In image data processing flow of the personal computer, first, the image data is stored in the frame buffer by the CPU, and then graphic card fetches this image data and generates appropriate analog or digital image data to the video interface. The image data is carried by VGA or DVI interface and delivered to the scaler board.
According to the panel characteristic, the scaler board automatically scales the image data to appropriate frame resolution and frame rate. Moreover, some scaler chips include extra functionality, such as video decoding, video processing and 3D graphics accelerator, etc.
Finally, the image data is translated into the signal format of TTL or Low Voltage Differential Signaling (LVDS) by scaler board and is delivered to panel controller board.
Figure 6-3. Block diagram of image processing flow.
6.2 Block Diagram of Prototype
Our goals are to reduce the power consumption of the LCD backlight and to maintain the image brightness with our backlight scaling algorithms. This consideration of fetching and processing image data from the PC will be used to design the experimental platform. There are different methods available to fetch the image data; one is to fetch the image data as it is delivered by graphic card, and another is to fetch the image data as it passes the scaler board.
It is more complex to process image data with the first method. Furthermore, some scaler boards include the functionality of image processing. While the image data passes the scaler board, the image data is probably adjusted or changed by scaler board. Base on the above reasons, we chose the second method. Unfortunately, because of the higher resolution TFT-LCD panel, the image data is translated into LVDS signal format by the scaler board while the image data passes the scaler board. LVDS signal format will complicate the image
fetching and processing.
Figure 6-4. Fetching the image data as the image data is delivered by graphic card.
Figure 6-5. Fetching the image data as the image data passes the scaler board.
6.2.1 Low Voltage Differential Signaling
The signal format of LVDS is a technology addressing the needs of today’s high
performance data transmission applications. The LVDS standard is becoming the most popular differential data transmission standard in the industry.
In the TFT-LCD field, the LVDS standard is usually used in the signal transmission of the higher-resolution LCD because it requires more data flow than low-resolution LCD.
LVDS delivers high data rates while consuming significantly less power than competing technologies. In addition, it brings many other benefits, which include:
• Low-voltage power supply compatibility
• Low noise generation
• High noise rejection
• Robust transmission signals
• Ability to be integrated into system level ICs
LVDS technology allows products to address high data rates ranging from 100’s of Mbps to greater than 2 Gbps. For all of the above reasons, it has been deployed across many market segments wherever the need of speed and low power exists.
Figure 6-6. Simplified diagram of LVDS driver and receiver.
LVDS is a low swing, differential signaling technology, which allows single channel data transmission at hundreds or even thousands of megabits per second (Mbps). Its low swing and
a wide range of frequencies.
LVDS outputs consist of a current source (nominal 3.5 mA) that drives the differential pair lines. The basic receiver has a high DC input impedance, so the majority of driver current flows across the 100Ω termination resistor generating about 350 mV across the receiver inputs. When the driver switches, it changes the direction of current flow across the resistor, thereby creating a valid “one” or “zero” logic state.
6.3 Platform
6.3.1 Experimental Panel
The experimental panel is equipped with a 1280×1024, 19”, 24-bit color, transmissive, color TFT-LCD monitor, ViewSonic VX912.
In our work, LED was used to fabricate backlight module. The backlight scaling panel and backlight was evaluated by a conventional TFT-LCD monitor. The prototype was built on a VX912 monitor. Originally the LCD panel has two side-lit CCFL backlights on the top and bottom. We custom made two LED backlights to replace the CCFL backlights.
Figure 6-7. VX912 monitor and panel.
The display panel manufactured by AUO Corporation includes a major application specific integrated circuit (ASIC) and an SXGA TFT-LCD panel [30]. The image data feeds into the AUO ASIC, which includes the timing controller and RSDS transmitter. The connector receives the LVDS signal which is from the scaler board, and then delivers to the AUO ASIC. The LVDS signal is translated into RSDS by the AUO ASIC, and then delivers to TFT-LCD.
Figure 6-8. Block diagram of the AUO panel.
6.3.2 FPGA Board
In the beginning, we implement the panel controller and backlight controller with an FPGA board which is supplied by CPT Corporation and Xilinx Spartan-3 Starter Kit [31], respectively. The CPT FPGA board includes an LVDS transmitter and receiver, and an FPGA chip. The Xilinx Spartan-3 starter kit houses 200,000-gate Xilinx Spartan-3 XC3S200 FPGA in a 256-ball thin ball grid array package (XC3S200FT256), 2Mbit Xilinx XCF02S platform flash, in-system programmable configuration PROM, 1M-byte of fast asynchronous SRAM, 3-bit, 8-color VGA display port, 9-pin RS-232 serial port, 50 MHz oscillator, and several I/O ports.
Figure 6-9. Xilinx Spartan-3 Starter Kit Board [31].
The CPT FPGA board includes three major ports; they are LVDS receiver, FPGA chip, and LVDS transmitter. The function of the LVDS receiver is to translate the LVDS signal format of image data to TTL signal format. Next, the TTL signal is delivered to the FPGA chip.
Our backlight scaling algorithm was programmed in HDL code, and then written into the FPGA chip. The TTL signal format of image data is processed by the FPGA chip, and then translated into LVDS signal format through the LVDS transmitter.
6.3.3 LED backlight
Our prototype LED backlight uses top-emitting LED chips. Each LED chip houses four LEDs – one red, two green in series, and one blue. The 1:2:1 ratio was determined by chromatic sensitivity and device efficiency. The three colors were driven separately such that the output chromaticity can be adjusted.
The LED backlights were used to replace the CCFL backlights of the VX912. Each LED backlight consists of 24 LED chips, wired as 4 parallel sets of 6 serial chips. Each channel is driven by a dedicated current mirror driver on a custom designed PCB. The driving current is controlled by a pulse-width modulation (PWM) signal.
Figure 6-10. LED and LED backlight.
Figure 6-11. Block diagram of backlight module.
Figure 6-12. LED backlight driving board.
6.3.4 Instruments and Equipment
The color and brightness of image are the most important properties of a system that we want to evaluate. The chroma meter (Konica-Minolta chroma meter CS-200) was used to measure these properties. It utilizes three high-sensitivity silicon photo-cells, which are filtered to match the CIE standard observer response. It can be used to measure various chromaticity coordinates by calculating three measurements, such as Lxy, Luv, Lu’v’, dominant wavelength, color temperature, etc. With this compact, reliable color analyzer, we
can easily get the chromaticity coordinates and luminance of the displayed image. The chroma meter CS-200 was also used to calibrate the white point of our prototype.
The programmable power supplies, GW PPT-3615, were used to support the LED driving board and LED backlights power. The digital multimeters, GDM 8246, were used to measure the current of LED backlights. We can obtain the voltage data of the LED backlights from the power supplies, and also obtain the current data from the multimeters. The power consumption can be calculated as the product of the voltage and current.
Figure 6-13. Chroma meter. Figure 6-14. Power supply. Figure 6-15. Multimeter.
6.3.5 Platform Block Diagram
In the final block diagram, we combined the backlight controller and panel controller onto the CPT FPGA board. The algorithm was also implemented in VHDL, the CPT FPGA Board. The following block diagrams are illustrated around the experimental setup in Figure 6-16.
z PC: Generating the image signals for the scaler board.
z Scaler Board: Scaling the image data to appropriate frame resolution and frame rate where the image signal is LVDS format.
z FPGA Board: Receiving LVDS signals and then translating signal to the TTL format.
Furthermore, performing the proposed algorithm image processing, and then outputting the VGA signal to drive the 19” TFT-LCD panel. At the same time, The FPGA board also generates the pulse width modulators (PWM) to control the
backlight intensity of the RGB channels.
z Multimeter: Measuring the driving current of the LEDs.
z Power Supply: Powering LED and their drivers.
z LED Driver: Driving the LEDs.
Figure 6-16. Layout of experimental system.
6.4 FPGA Architecture
The critical component of our experimental platform is the CPT FPGA board. The algorithm of backlight scaling is programmed with very high speed integrated circuit hardware description language (VHDL) code and then writes into the FPGA chip, which is on the CPT FPGA board. The two major assignments are executed by FPGA chip adjust the image data from the scaler board and adjust the backlight intensity.
6.4.1 Display Signal
The display signal plays a decisive role in programming HDL code. CRT display is based
on an afterimage of human eyes. As we reduce the refresh rate of the CRT display that exceeds the minimum period for an afterimage on the human eye, we start to feel flicker. In other words, the image on the CRT display is always flickering; but human eyes do not recognize it as long as the flickering frequency is high enough. Meanwhile, the image on the TFT LCD panel also flickers, but the flicker on the LCD panel is of a different nature. As far as the refresh rate is higher than the time constant of the storage capacitors, the image on the LCD display does not flicker at all. Consequently, we can reduce the refresh rate of the LCD display as long as it is shorter than the time constant of the storage capacitors. Actually, modern LCD displays adopt flicker free techniques, and the time constant is much longer than that of the CRT display. In addition, as we increase the refresh rate of the CRT display far exceeding the minimum period for the afterimage, we do feel better quality; so we often use 120Hz or higher refresh rate for high quality image. However, once the refresh rate is higher than the time constant of the storage capacitors, the image quality of the LCD display is not enhanced further. Therefore, most LCD panels support fixed refresh rate, unlike CRT displays.
Vertical synchronization (Vsync) is a signal used to describe the process or set a value telling the monitor when to draw the next vertical line. Vsync determines the frame frequency of the display. The frame rate of CRT display can be adjusted, but LCDs cannot, due to the LC response time is limited. So, most LCDs support fixed frame rate, unlike CRT display.
Meanwhile, the frame rate of the TFT-LCDs is usually 60Hz. Horizontal synchronization (Hsync) is a signal telling the monitor to stop drawing the current horizontal line, and starts drawing the next line. Each high state of the DE (data enable) signal matches the high state of a Hsync signal.
Figure 6-17. Waveform chart of video signal (a).
The DE signal determines the data writing in the period of the high state. In the period of high state of the DE signal, which is active time and the data of an image is valid. As the DE signal is low state, the data of the image is invalid even though the Hsync is high state.
Figure 6-18. Waveform chart of video signal (b).
The DCLK means the pixel clock. Each period of the DCLK represents the transmission data of a pixel is valid and the amount of the pixels is 1280 while the DE is high state.
Meanwhile, the data width is 24 bits, which means that the data width of R, G, and B of an image has 8 bits.
Figure 6-19. Waveform chart of video signal (c).
6.4.2 LVDS Interface / TFT Data (Color) Mapping
Different color mapping options exist. The LVDS clock wave shape is shown in Figure 6-20. The rising edge of the LVDS clock occurs two LVDS sub symbols before the current cycle of data. The clock is composed of a 4 LVDS sub symbol HIGH time and a 3 LVDS sub symbol LOW time. The respective pin (transmitter and receiver) names are shown in Figure 6-20. As stated above, these names are not the color mapping information (MSB/LSB), but the pin names only.
In Figure 6-20, inputs B17 and B27 are double width. In the LVDS receiver IC, these bits are sampled in the back half of the bit only. Also, the DE signal is mapped to two LVDS sub symbols. The LVDS receiver IC only samples the DE bit on channel A2.
Figure 6-20. TTL data inputs mapped to LVDS outputs [32].
6.4.3 Implementation of Algorithm
The basic hierarchy of the FPGA is shown in Figure 6-21. The LVDS signal, which is from scaler board, is translated into TTL signal by the LVDS receiver of CPT FPGA board and then is delivered to FPGA chip. In our process flow, first, each frame is stored with his image data. Next, we calculate the clipping boundary of the histogram by our algorithm. The two blocks of backlight adjusting hierarchy and transmittance adjusting hierarchy employ the clipping boundary as the parameter for the image process based on our backlight scaling algorithm to calculate the pixel transfer function for the original image. Finally, the original image data is translated into scaling image data by transmittance adjusting hierarchy and then is delivered to LVDS transmitter. The LVDS transmitter translates the TTL signal into LVDS signal and then delivers the LVDS signal to the TFT-LCD panel. At the same time, the PWM signal delivered to the LED backlights from backlight adjusting hierarchy for dimming the LED backlights.
Figure 6-21. Basic hierarchy of the HDL code.
Histogram Calculation
Because of the memory issues of the FPGA chip, we divided the histogram of the image data into four bins. There are totally 256×3 registers to count the number of image data of a pixel. We program a dynamic RAM with the FPGA chip and store the statistics of these registers in the dynamic RAM.
Figure 6-22. The histogram calculation module.
There are three histogram calculation modules for RGB channel. Each gray value of the 256 values is used as an input for the 8 to 256 decoder shown in Figure 6-22 to determine
which of the 256 counters will be incremented. The counters Counter_0 to Counter_255, illustrated in the figure, are used to determine the number of pixels utilizing each gray level.
The value of each counter is stored in a register hi, where i = 0, 1, 2, ..., 255 is the corresponding gray value. At this point, the histogram values for all of the gray levels are obtained.
Determine Boundary
In our algorithm, it requires a large number of the calculation to determine these clipping boundaries. The implementation of the FPGA is difficult due to the logic gate of the FPGA chip is limited and the code of HDL is very complex. Furthermore, lots of the calculation also causes serious timing delay.
Due to the transmission speed of the image signal of the SXGA panel is very fast, the influence of the timing delay cannot be neglected. For example, two identical signals from the scaler board input the FPGA chip at the same time, one signal which passing through the longer path in the FPGA chip has more serious timing delay than the other which passes through the shorter path in the FPGA chip. The two different timing delays between the signals will cause the signals are not synchronous and then the LCD displays the wrong image.
The Lookup table (LUT) is created and used to overcoming that the timing delay and number of the logic gate issues. The determine boundary block will generate corresponding data according to the LUT while the histogram data delivers to this block.
Figure 6-23. The boundary determination block.
Backlight adjusting hierarchy
The backlight adjusting hierarchy is used to determine the PWM signal through the data
The backlight adjusting hierarchy is used to determine the PWM signal through the data