Implementation of Algorithm

The basic hierarchy of the FPGA is shown in Figure 6-21. The LVDS signal, which is from scaler board, is translated into TTL signal by the LVDS receiver of CPT FPGA board and then is delivered to FPGA chip. In our process flow, first, each frame is stored with his image data. Next, we calculate the clipping boundary of the histogram by our algorithm. The two blocks of backlight adjusting hierarchy and transmittance adjusting hierarchy employ the clipping boundary as the parameter for the image process based on our backlight scaling algorithm to calculate the pixel transfer function for the original image. Finally, the original image data is translated into scaling image data by transmittance adjusting hierarchy and then is delivered to LVDS transmitter. The LVDS transmitter translates the TTL signal into LVDS signal and then delivers the LVDS signal to the TFT-LCD panel. At the same time, the PWM signal delivered to the LED backlights from backlight adjusting hierarchy for dimming the LED backlights.

Figure 6-21. Basic hierarchy of the HDL code.

Histogram Calculation

Because of the memory issues of the FPGA chip, we divided the histogram of the image data into four bins. There are totally 256×3 registers to count the number of image data of a pixel. We program a dynamic RAM with the FPGA chip and store the statistics of these registers in the dynamic RAM.

Figure 6-22. The histogram calculation module.

There are three histogram calculation modules for RGB channel. Each gray value of the 256 values is used as an input for the 8 to 256 decoder shown in Figure 6-22 to determine

which of the 256 counters will be incremented. The counters Counter_0 to Counter_255, illustrated in the figure, are used to determine the number of pixels utilizing each gray level.

The value of each counter is stored in a register hi, where i = 0, 1, 2, ..., 255 is the corresponding gray value. At this point, the histogram values for all of the gray levels are obtained.

Determine Boundary

In our algorithm, it requires a large number of the calculation to determine these clipping boundaries. The implementation of the FPGA is difficult due to the logic gate of the FPGA chip is limited and the code of HDL is very complex. Furthermore, lots of the calculation also causes serious timing delay.

Due to the transmission speed of the image signal of the SXGA panel is very fast, the influence of the timing delay cannot be neglected. For example, two identical signals from the scaler board input the FPGA chip at the same time, one signal which passing through the longer path in the FPGA chip has more serious timing delay than the other which passes through the shorter path in the FPGA chip. The two different timing delays between the signals will cause the signals are not synchronous and then the LCD displays the wrong image.

The Lookup table (LUT) is created and used to overcoming that the timing delay and number of the logic gate issues. The determine boundary block will generate corresponding data according to the LUT while the histogram data delivers to this block.

Figure 6-23. The boundary determination block.

Backlight adjusting hierarchy

The backlight adjusting hierarchy is used to determine the PWM signal through the data from the above block. The backlight adjusting hierarchy includes three major units, the data registers, PWM signal generators and timing adjusted unit. In the beginning, the data is stored in the data registers, and then the PWM generators determine the duty cycle of the output signal according to the data of the registers. Next, the PWM signal is delivered to timing adjusted unit. The timing adjusted unit is enabled by timing buffer, and the PWM Generator will deliver the PWM signal to the LED backlights. The intensity of the LED backlights will be determined by the PWM signal.

Figure 6-24. The circuit scheme of backlight adjusting hierarchy.

The PWM Generator is composed of a 6-bit counter and a 6-bit unsigned comparator shown in Figure 6-25. The duty cycle of the PWM signal depends on the Data_in. The output of the comparator is high while C_in is smaller than Data_in.

Figure 6-25. The PWM Generator.

Transmittance adjusting hierarchy

The transmittance adjusting hierarchy is used to the transmittance of the panel. It

includes the registers, subtracts, multipliers, dividers, and timing control unit. The output results of every pixel are calculated according to the input data which is from the above block.

The circuit scheme is shown in Figure 6-26. Due to the pixel data is unsigned, the process that eliminating negative value is necessary. The outputs of the comparators are used to make subtracts generate absolute value.

Figure 6-26. The circuit scheme of transmittance adjusting hierarchy.

In our luminance scaling algorithm, the transfer function will result in a floating decimal.

In order to avoid computing the floating decimal and simplify the circuit, we finish the multiplication first, and then do division.

Timing Buffer

The timing buffer is composed of the flip-flop. This buffer is very important for synchronize the panel transmittance and LED backlight intensity. The timing buffer synchronizes the output of transmittance adjusting hierarchy and backlight adjusting hierarchy.

If the variations of the LED backlight and panel are asynchronous, the observers will perceive the wrong image on this display.

Figure 6-27. The block diagram of the FPGA chip.

Figure 6-27. shows the block diagram of the FPGA chip. The following description expresses the function of every pins of the FPGA chip.

z RE, GE, and BE: The inputs of the even line of the image data.

z RO, GO and BO: The inputs of the odd line of the image data.

z CLK0: The input of the pixel clock.

z DENA0: The input of the data enable.

z HD0: The input of the Hsync.

z VD0: The input of the Vsync.

z sws: The ON/OFF of the backlight scaling.

z reset: The image data reset.

z FE_R, FE_G, and FE_B: The outputs of the even line of the image data.

z FO_R, FO_G, and FO_B: The outputs of the odd line of the image data.

z DCLK_out: The output of the pixel clock.

z DENA_out: The output of the data enable.

z Hsync_out: The output of the Hsync.

z Vsync_out: The output of the Vsync.

z pr, pg, and pb: The output of the PWM signal for adjusting LED backlight intensity.