Chapter 5 Transmitter
5.3 M EASUREMENT R ESULT
Fig. 5.18 shows the chip photo of the transmitter which is fabricated in a 0.25-µm 1P5M CMOS process with the 3.3-V power supply. The chip area of the transmitter is 1500 µm × 1500 µm. The measurement setup of the transmitter is shown in Fig. 5.19. Fig. 5.20 shows the top view of the testing PCB photo for the transmitter.
One of the four data channels and the PLL channel are tested. Fig. 5.21 shows the bottom view of the testing PCB photo for the transmitter. The measured output signals of the transmitter which is in the LVDS or RSDS mode are shown in Figs. 5.22 and 5.23 respectively. The output signal voltage swings of the LVDS and RSDS mode are
Fig. 5.25 shows the measured RSDS eye diagram of the transmitter at 700 Mb/s. The peak-to-peak jitter is 25.15 %. Fig. 5.26 shows the measured LVDS eye diagram of the transmitter at 840 Mb/s. The peak-to-peak jitter is 31.5 %. Fig. 5.27 shows the measured RSDS eye diagram of the transmitter at 840 Mb/s. The peak-to-peak jitter is 32.8 %. Fig. 5.28 shows the measured LVDS eye diagram of the transmitter at 1.05 Gb/s. The peak-to-peak jitter is 26.25 %. Fig. 5.29 shows the measured RSDS eye diagram of the transmitter at 1.05 Gb/s. The peak-to-peak jitter is 27.89 %. All above eye diagrams are measured with package. In order to have better jitter performance, bare die with bond wires is tested on the PCB. Fig. 5.30 shows the measured LVDS eye diagram of the transmitter at 700 Mb/s by using bare die. The peak-to-peak jitter is 21.87 %. Fig. 5.31 shows the measured LVDS eye diagram of the transmitter at 840 Mb/s by using bare die. The peak-to-peak jitter is 18.4 %. Fig. 5.32 shows the measured LVDS eye diagram of the transmitter at 1.05 Gb/s by using bare die. The peak-to-peak jitter is 19.7 %. It is obvious that the jitter performance of the transmitter is better by using bare die rather than package. Figs. 5.33 and 5.34 show the measured output clock of the PLL at 120 MHz and 150 MHz. The duty cycle of the output clocks at 120 MHz and 150 MHz are almost four to three. The long-term peak-to-peak jitter of the PLL output signal at 120 MHz is 88 ps which is 1.056 % of the PLL output signal time period as shown in Fig. 5.35.
Fig. 5.36 shows the measurement setup of the transmitter with a 3-meter long UTP Cat.6 line. The measurement of the 3-meter long UTP Cat.6 line with two termination boards is shown in Fig. 5.37. Figs. 5.38, 5.39 and 5.40 show the measured 840-Mb/s eye diagram of the transmitter with UTP Cat.6 lines at 1 meter, 2 meter and 3 meter. Figs. 5.41, 5.42 and 5.43 show the measured 1-Gb/s eye diagram of the transmitter with UTP Cat.6 lines at 1 meter, 2 meter and 3 meter. Fig. 5.44 shows the layout and schematic of the ESD protection circuit which is employed to protect the
core circuit. Fig. 5.45 shows the measurement setup of the ESD testing. The testing model is the human body model (HBM). Fig. 5.46 shows the measurement results of the ESD protection circuit. The measured parameter of the transmitter is summarized in Table 5.1.
5.4 CONCLUSION
A transmitter that can converts 28 bits of TTL data to four LVDS or RSDS data streams plus one clock data is implemented in this thesis. The 28 bits of TTL data include eight Red data, eight Green data, eight Blue data and four control lines which is one of the specifications in the flat panel display links. The measured data rate of the transmitter is up to 1.05 Gb/s which can support the SXGA (1280 × 1024 pixels) resolution of flat panel displays.
Table 5.1
The simulated and measured parameters of the designed PLL.
Function PLL
Simulation Results
Operate Voltage 3.3 V
Input Frequency 120 MHz
Output Frequency 120 MHz
Charge Pump Current 100 µA
Divided by N N = 1
Loop Bandwidth 4.8 MHz
Extra Zero 1.07 MHz
Extra Pole 21.77 MHz
Natural Frequency 2.32 MHz
Damping Factor 0.766
Power 34.48 mW@120 MHz
Measurement Results
Technology VIS 0.25-µm 1P5M CMOS
Output Clock Jitter 88 ps (long-term peak-to-peak jitter)@120 MHz, < 1.056 %
Function Transmitter
Measurement Results
Operate Voltage 3.3 V
Power Consumption (1) 283 mW@840 Mb/s
Power Consumption (2) 300.3 [email protected] Gb/s
Data Rate Target at 840 Mb/s
(Measured up to 1.05 Gb/s)
Technology VIS 0.25-µm 1P5M CMOS
Fig. 5.1 The block diagram of the transmitter.
Fig. 5.3 The circuit block of the transmitter which converts seven parallel TTL data to one serial LVDS or RSDS data stream.
Fig. 5.4 The circuit implementation of the pseudo random binary sequence (PRBS).
Fig. 5.5 The circuit implementation of the positive edge-triggered D-type flip-flop using true single-phase clock logic (TSPC).
Fig. 5.6 The simulated patterns of the pseudo random binary sequence (PRBS).
Fig. 5.7 The architecture of the PLL which is used in the transmitter.
Fig. 5.8 The circuit implementation of the phase frequency detector.
Fig. 5.9 The circuit implementation of the charge pump.
Fig. 5.10 The circuit implementation of the self-biased replica-feedback bias generator.
Fig. 5.12 The circuit implementation of the differential-to-single-ended converter.
Fig. 5.13 The simulated seven output clocks with four to three duty cycle of the PLL.
Fig. 5.14 The circuit implementation of the multiplexer.
Fig. 5.16 The circuit implementation of the co-designed output buffer.
Fig. 5.17 The parallel to serial conversion of the seven parallel PRBS data to one serial LVDS data stream.
Fig. 5.18 Photograph of the transmitter in a 0.25-µm 1P5M 3.3-V CMOS process.
Fig. 5.20 The top view of the testing PCB photo for the transmitter.
Fig. 5.21 The bottom view of the testing PCB photo for the transmitter.
Fig. 5.22 The differential output signals of the transmitter in the LVDS mode.
Fig. 5.24 The measured eye diagram of the transmitter at 700 Mb/s with package.
The peak-to-peak jitter is 24 %. The transmitter is in the LVDS mode.
Fig. 5.25 The measured eye diagram of the transmitter at 700 Mb/s with package.
The peak-to-peak jitter is 25.15 %. The transmitter is in the LVDS mode.
Fig. 5.26 The measured eye diagram of the transmitter at 840 Mb/s with package.
The peak-to-peak jitter is 31.5 %. The transmitter is in the LVDS mode.
Fig. 5.27 The measured eye diagram of the transmitter at 840 Mb/s with package.
Fig. 5.28 The measured eye diagram of the transmitter at 1.05 Gb/s with package.
The peak-to-peak jitter is 26.25 %. The transmitter is in the LVDS mode.
Fig. 5.29 The measured eye diagram of the transmitter at 1.05 Gb/s with package.
The peak-to-peak jitter is 27.89 %. The transmitter is in the LVDS mode.
Fig. 5.30 The measured eye diagram of the transmitter at 700 Mb/s without package.
The peak-to-peak jitter is 21.87 %. The transmitter is in the LVDS mode.
Fig. 5.31 The measured eye diagram of the transmitter at 840 Mb/s without package.
Fig. 5.32 The measured eye diagram of the transmitter at 1.05 Gb/s without package.
The peak-to-peak jitter is 19.7 %. The transmitter is in the LVDS mode.
Fig. 5.33 The measured output clock of the PLL at 120 MHz with package. The duty cycle of the output clock is almost four to three.
Fig. 5.34 The measured output clock of the PLL at 150 MHz with package. The duty cycle of the output clock is almost four to three.
Fig. 5.36 The measurement setup of the transmitter with a 3-meter long UTP Cat.6 line.
Fig. 5.37 Measurement of the 3-meter long UTP Cat.6 line with two termination boards.
Fig. 5.38 The eye diagram of the transmitter at 840Mb/s with 1-m UTP Cat.6 line.
Fig. 5.39 The eye diagram of the transmitter at 840Mb/s with 2-m UTP Cat.6 line.
Fig. 5.40 The eye diagram of the transmitter at 840Mb/s with 3-m UTP Cat.6 line.
Fig. 5.41 The eye diagram of the transmitter at 1 Gb/s with 1-m UTP Cat.6 line.
Fig. 5.42 The eye diagram of the transmitter at 1 Gb/s with 2-m UTP Cat.6 line.
Fig. 5.43 The eye diagram of the transmitter at 1 Gb/s with 3-m UTP Cat.6 line.
Fig. 5.44 The layout and schematic of the ESD protection circuit (GGNMOS).
Fig. 5.45 The measurement setup of the ESD testing. The ESD testing model is the
Fig. 5.46 The measurement results of the ESD testing.
Chapter 6
Summary and Future Works
6.1 SUMMARY
In the chapter 2, detail DC specifications of the LVDS and RSDS standards are discussed. LVDS stands for Low Voltage Differential Signaling and RSDS stands for Reduced Swing Differential Signaling. Both technologies have been developed to provide the high-speed and low-power interface applications which can be used in variety aspects. One of the applications is in the flat panel display systems which is the main issue in this thesis.
In the chapter 3, a phase-locked loop has been implemented in a 0.25-µm 1P5M CMOS process and the power supply is 2.5 V. The PLL has ten different output phases which are 200 MHz. The tuning frequency of the PLL is measured from 80 MHz to 360 MHz. The main application of the designed PLL is to perform the parallel-to-serial conversion with a multiplexer which is used in a transmitter.
According to the measured jitter of the PLL, it is good enough to be employed in the transmitter to have better performance.
In the chapter 4, three I/O buffers have been fabricated in a 0.25-µm 1P5M CMOS process and the power supply is 3.3 V. These I/O buffers are fully compatible with both LVDS and RSDS standards. The data rate of the output buffers are tested up to 1.2 Gb/s which can support the UXGA (1600 × 1200 pixels) resolution of the flat panel displays. The data rate of the input buffer is tested up to 840 Mb/s. The output
In the chapter 5, a transmitter which converts 28 bits of parallel TTL data into four LVDS or RSDS data streams plus one clock data stream has been implemented in a 0.25-µm 1P5M CMOS process and the power supply is 3.3 V. The PLL in the transmitter has seven different clock phases in order to perform parallel-to-serial conversion of incoming data. The data rate of the transmitter is tested up to 1.05 Gb/s which can support the SXGA (1280 × 1024 pixels) resolution of the flat panel displays.
6.2 FUTURE WORKS
Although the functions of the designed circuits in this thesis are all verified, there are still many drawbacks needed to be improved. First is that new proposed circuit technologies should be employed in the transmitter in order to reduce the jitter of the measured eye diagrams. Second is to design pre-emphasis circuit in the transmitter in order to have better transmission qualities through connecting materials.
Models of transmission lines and packages should also be measured and modeled.
Third is to keep on studying the architecture of receiver such as 3x-oversampling in order to complete the whole transceiver function [24].
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