T HESIS O RGANIZATION

The chapter 2 of the thesis discusses the low-voltage differential signaling (LVDS) standard and the reduced-swing differential signaling (RSDS) standard. The detail DC specifications and applications of both standards are presented. In the chapter 3, a phase-locked loop (PLL) is described and the simulation results are in the final section. In the chapter 4 and 5, three I/O buffers and the complete transmitter for flat panel display applications are implemented. The new proposed I/O buffers with both LVDS and RSDS standards are presented and detail circuit functions of the transmitter are discussed. The last chapter recapitulates the major consideration of this thesis and concludes with suggestion for future investigation.

Table 1.1

Industrial standards for high-speed serial link.

Standard Speed

Comparison between different transmission technologies that are applied for different I/O interfaces.

RS-422 PECL LVDS RSDS Optics GTL TTL

Low High Low Low Low High High

Fig. 1.1 Basic serial-link transceiver architecture.

Fig. 1.2 Reduce noise and suppress EMI effect by using the differential transmission technology.

Chapter 2

Specifications of Low-Voltage Differential

Signaling (LVDS) Standard and Reduced-Swing Differential Signaling (RSDS) Standard

2.1 BACKGROUND

Recent growth in high-end processors, multi-media, virtual reality and networking have demanded more bandwidth than ever before. But the point-to-point physical layer interfaces have not been able to deal with moving information at the data rates required. Some of today’s biggest challenges that remain to be solved include the ability to transfer data fast, lower power systems than currently available, and economical solutions to overcome the physical layer bottleneck. Data transmission standards such as RS-422, RS-485, SCSI and others all have their own limitations most notably in transferring raw data across a medium. Therefore, low-voltage differential signaling (LVDS) is a high-speed (> 400 Mb/s), low-power general purpose interface standard that solves the bottleneck problems while servicing a wide range of application areas.

2.2 TWO STANDARDS OF LVDS

There are two industry standards that define LVDS [3]. The more common of the

application specific standard is the IEEE (Institute for Electrical and Electronics Engineering) standard which is titled SCI (Scalable Coherent Interface).

2.2.1 ANSI/TIA/EIA-644

This standard defines driver output and receiver input characteristics. Functional specifications and/or protocols are not within the scope of the TIA standard. It notes a recommended maximum data rate of 655 Mb/s and a theoretical maximum of 1.923 Gb/s based on a loss-less medium. However, maximum data rate is application (desired signal quality), and device specific (transition time). It is feasible that LVDS based interface will operate in the 500 Mb/s to 1.5 Gb/s range in the near future.

Minimum media specifications are also defined within the standard. It also discusses failsafe operation of the receiver under fault conditions and other configurations issues such as multi-receiver operation. National Semiconductor Corporation held the editor position for this standard.

2.2.2 IEEE 1596.3 SCI-LVDS

SCI originally referenced a differential ECL (Emitter Coupled Logic) interface within the SCI 1596-1992 IEEE standard [5]. However, this only addressed the high data rates required and did not address the low power concerns. Thus, SCI-LVDS was defined as a subset of SCI, and is specified in IEEE 1596.3 standard. SCI-LVDS specifies signaling levels (electrical specifications) for the high-speed/low-power physical layer interface. It also defines the encoding for packet switching used in SCI data transfers. Packets are constructed from 2-byte (doublet) symbols. This is the fundamental 16-bit symbol size. No media are specified and the data rate can be in the order of 500 MT/s based on serial or parallel transmission of 1, 4, 8, 16, 32, and 64 ...

bits. The IEEE 1596.3 standard was approved in March 1994. National

Semiconductor Corporation held the chairperson position for this standard.

SCI-LVDS is similar to the TIA version but differs in some electrical requirements and load conditions. Both standards feature similar driver output levels, receiver thresholds and data rates. The TIA version is the more generic of the two standards and is intended for multiple applications. The electrical-only ANSI/TIA/EIA-644 standard is shown in Table 2.1, and it is intended to be referenced by other standards that specify the complete interface (connectors, protocol, etc.).

2.3 INTRODUCTION TO LVDS

Following is the detail discussion of low-voltage differential signaling (LVDS) applications and basic circuits.

2.3.1 Basic Concepts

LVDS stands for Low Voltage Differential Signaling. It is a way to communicate data using a very low voltage swing (about 350 mV) differentially over two PCB traces or balanced cables. The simplified diagram of LVDS driver and receiver connected via 100 Ω differential impedance media is shown in Fig. 2.1. The driver consists of a current source which drives the differential pair lines. The basic receiver has high DC input impedance, so the majority of driver current flow across the 100 Ω termination resistor generating about 350 mV across the receiver inputs. When four MOS switches (the M1 - M4 in Fig. 2.1) of the driver switch, the direction of current across the resistor is changed, thereby creating a valid “one” or “zero” logic state. The signaling levels of LVDS are shown in Fig. 2.2.

wires with opposite current/voltage swings instead of the one wire used in single-ended methods to convey data information. The advantage of the differential approach is that if noise is coupled onto the two wires as common-mode (the noise appears on both lines equally) and is thus rejected by the receiver which detects only the voltage difference between the two signals. The differential signals also tend to radiate less noise than single-ended signals due to the canceling of magnetic fields.

The current-mode driver is not prone to ringing and switching spikes, further reducing noise. Because differential technologies such as LVDS reduce concerns about noise, they can use lower signal voltage swings. This advantage is crucial, because it is impossible to raise data rates and lower power consumption without using low voltage swings. The low swing nature of the driver means data can be switched very quickly.

Since the driver is also current-mode, very low almost flat power consumption across frequency is obtained. Switching spikes in the driver are very small, so that total current consumption does not increase exponentially as switching frequency is increased. Also, the power consumed by the load (3.5 mA × 350 mV = 1.225 mW) is very small in magnitude.

2.3.2 Easy Termination

Whether the LVDS transmission medium consists of cables or controlled impedance traces on a printed circuit board, the transmission medium must be terminated to its characteristic differential impedance to complete the current loop and terminate the high-speed signals. If the medium is not properly terminated, signals reflect from the end of the cables or traces and may interfere with succeeding signals.

Proper termination also reduces unwanted electro-magnetic emissions and provides the optimum signal quality. To prevent reflections, LVDS requires a terminating resistor that is matched to the actual cables or PCB traces differential impedance.

Commonly a 100 Ω termination is employed. This resistor completes the current loop and properly terminates the signal. This resistor is placed across the differential signal lines as close as possible to the receiver input. The simplicity of the LVDS termination scheme makes it easy to implement in most applications. ECL and PECL (Positive Emitter Coupled Logic) require more complex termination than the one-resistor solution for LVDS [6]. PECL drivers commonly require 220 Ω pull down resistors from each driver output, along with 100 Ω resistor across the receiver input.

2.3.3 LVDS Configurations

LVDS drivers and receivers are commonly used in a point-to-point configuration as shown in Fig. 2.3. However, other topologies/configurations are also possible. The configuration, as shown in Fig. 2.4, allows bi-directional communication over a single twisted pair cable. Data can flow in only one direction at a time. The requirement for two terminating resistors reduces the signal (and thus the differential noise margin), so this configuration should be considered only where noise is low and transmission distance is short (< 10 m). In Fig. 2.5, a multi-drop configuration connects multiple receivers to a driver. These are useful in data distribution applications. They can also be used if the stub lengths are as short as possible (less than 12 mm application dependent). Dedicated point-to-point links provide the best signal quality due to the clear path they provide. LVDS has many advantages that make it likely to become the next famous data transmission standard rates from hundreds to thousands of megabits per second and short haul distances in the tens of meters. In this role, LVDS far exceeds the 20 Kb/s to 30 Mb/s rates of the common RS-232, RS-422, and RS-485 standards.

2.3.4 Cables and Connectors

LVDS was intended to be used on a wide variety of media [7]. The exact medium is not specified in the LVDS standard, as it is intended to be specified in the referencing standard that specifies the complete interface [8]. This includes the media, data rate, length, connectors, function, and pin assignments. In some applications that are very short (< 0.3 m), ribbon cables or flex circuits may be acceptable. In the box-to-box application, twisted pair or twin-ax cables would be a better option due to robustness, shielding and balance. When choosing cables and connectors for LVDS, following tips are important:

z Use controlled impedance media. The cables and connectors should have a differential impedance of about 100 Ω. They should not introduce major impedance discontinuities that cause signal reflections.

z Balanced cables (twisted pair) are usually better than unbalanced cables (ribbon cable, multi-conductor) for noise reduction and signal quality.

Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electro-magnetic radiation as common-mode (not differential-mode) noise, which is rejected by the receiver.

z For cable distances less than 0.5 m, most cables can be made to work effectively. For cable distances less than 10 m, CAT 3 (Category 3) twisted pair cable works well and is readily available and relatively inexpensive.

Other types of cables may also be used as required by a specific application.

This includes twin-ax cables built from separate pairs and ribbon style constructions, which are then coiled.

As the tips that are mentioned above, try to use differential cables such as twisted pair cables, twin-ax cables, or flex circuits with closely coupled differential traces when designing a LVDS compatible I/O interface. Twisted pair cables, which provide

a good, low cost solution with good balance as shown in Fig. 2.6, are flexible, and capable of medium to long runs depending upon the application skew budget. It is offered with an overall shield or with shields around each pair as well as an overall shield. Twisted pair cables such as Category 3 (CAT3) cable is good for runs up to about 10 m, while CAT5 has been used for longer runs. Twin-ax cables, as shown in Fig. 2.7, are flexible, have low skew and shields around each pair for isolation. Since they are not twisted, they tend to have very low skew within a pair and between pairs.

These cables are for long runs and have been commonly deployed in Channel Link and FPD-Link applications. Flex circuits, as shown in Fig. 2.8, is a good choice for very short runs, but it is difficult to be shielded. It can be used as interconnects between boards within systems. The members of differential pairs should be closely coupled (S < W) and use ground shield traces between the different differential pairs.

Connectors are also application dependent and depend upon the cable system being used, the number of pins, the need for shielding and other mechanical footprint concerns. Standard connectors have been used at low to medium data rates, and optimized low skew connectors have been developed for medium to high-speed applications.

2.3.5 Signal Quality

Signal quality may be measured by a variety of means [9]. Eye Patterns is commonly used to determine signal quality. The eye pattern is used to measure the effects of inter-symbol interference (ISI) on random data being transmitted through a particular medium. The prior data bits effect the transition time of the signal. This is especially true for none return to zero (NRZ) data that does not guarantee transitions

to the low pass filter effects of the cable. Fig. 2.9 illustrates the superposition of six different data patterns. Overlaid, they form the eye pattern that is the input to the cable. The right hand side of Fig. 2.9 illustrates the same pattern at the end of the cable. Note the rounding of the formerly sharp transitions. The width of the crossing point is now wider and the opening of the eye is also now smaller.

Fig. 2.10 describes the measurement locations for minimum jitter. Peak-to-peak jitter is the width of the signal crossing the optimal receiver thresholds. For a differential receiver, that would correspond to 0 V (differential). However, the receiver is specified to switch between + 100 mV and – 100 mV. Therefore for a worse case jitter measurement, a box should be drawn between ± 100 mV and the jitter is measured between the first and last crossing at ± 100 mV. If the vertical axis units in Fig. 2.10 were 100mV/division, the worse case jitter is at ± 100 mV levels.

Eye patterns provide a useful tool to analyze jitter and the resulting signal quality as it captures the effects of a random data pattern. They provide a method to determine the maximum cable length for a given data rate or vice versa. Different systems, however, can tolerate different levels of jitter. Commonly 5 %, 10 %, or 20

% is acceptable with 20 % jitter usually being an upper practical limit. More than 20

% jitter tends to close down the eye opening, making error-free recovery of NRZ data more difficult.

2.3.6 Input Common Mode Range of LVDS Receiver

An LVDS receiver can tolerate a maximum of ± 1 V ground shift between the driver’s ground and the receiver’s ground. Note that LVDS has a typical output offset voltage of + 1.2 V, and the summation of ground shifting, output offset voltage and any longitudinally coupled noise is the common mode voltage seen on the receiver input pins with respect to the receiver ground. The common mode range of the

receiver is + 0.2 V to + 2.2 V, and the recommended receiver input voltage range is from ground to + 2.4 V. For example, if a driver has a VOH of 1.4 V and a VOL of 1.0 V (with respect to the driver ground), and a + 1 V ground shift is present (driver ground + 1 V higher than receiver ground), this will become + 2.4 V (1.4 + 1.0) as VIH and + 2.0 V (1.0 + 1.0) as VIL on the receiver inputs referenced to the receiver ground. On the contrary, with a − 1 V ground shift and the same driver levels results as 0.4 V (1.4 − 1.0) VIH and 0.0 V (1.0 − 1.0) VIL on the receiver inputs. This is shown in Fig. 2.11.

2.3.7 Advantages and Applications

LVDS has many advantages as following:

z The LVDS solutions are inexpensive CMOS implementations as compared to custom solutions on elaborate processes.

z High performance can be achieved by using low cost, off-the-shelf CAT3 cables and connectors, or FR4 materials.

z LVDS consumes very little power, so power supplies, fans, etc., can be reduced or eliminated.

z LVDS is a low noise producing, noise tolerant technology – power supply and EMI noise are greatly minimized.

z LVDS transceivers are relatively inexpensive and can also be integrated around digital cores providing a higher level of integration.

z LVDS can move data so much faster than TTL (Transistor-Transistor Logic), so multiple TTL signals can be serialized into a single LVDS channel, reducing board, connector, and cable costs. Fig. 2.12 shows the

of LVDS applications far beyond those for traditional technologies. The applications of LVDS in several aspects are summarized in Table 2.2.

2.3.8 Conclusion

LVDS technology solves the ever increasing data rate problem while decreasing power dissipation and can be widely used in telecom, routers, intelligent hubs, LCD displays, copiers and numerous other exciting applications. LVDS technology eliminates the trade-offs in speed, power, noise, and cost for high performance data transmission applications. This high speed interface allows designers to implement a simple point-to-point link without complex termination issues. Low power dissipation and the use of a core process allows for the integration of PLLs and digital blocks to provide optimized interface single chip solutions. LVDS technology provides solutions when gigabits at milliwatts are required. Merits and drawbacks of different I/O interface technologies are summarized in Table 2.3.

2.4 INTRODUCTION TO RSDS

Following is the detail discussion of reduced-swing differential signaling (RSDS) applications and basic circuits [10].

2.4.1 Scope

Reduced Swing Differential Signaling (RSDS) is a signaling standard that defines the output characteristics of a transmitter and inputs of a receiver along with the protocol for a chip-to-chip interface between flat panel timing controllers and flat panel column drivers. RSDS technology is originated from the LVDS technology.

The RSDS interfaces tend to be used in flat panel display applications with

resolutions between VGA (600 × 480 pixels) and UXGA (1600 × 1200 pixels). The RSDS technology provides many benefits to flat panel display applications which include following items:

z Reduced bus width – enables smaller and thinner flat panel column driver boards.

z Low power dissipation – extends system run time.

z Low EMI generation – eliminates EMI suppression components and shielding.

z High noise rejection – maintains signal image.

z High throughput – enables high resolution flat panel displays.

RSDS is a differential interface with a nominal signal swing of 200 mV. It retains the many benefits of the LVDS interface which is commonly used between the host and the panel for a high bandwidth, robust digital interface. The RSDS applications are within a sub-system, the signal swing is reduced further from LVDS to lower power even further.

2.4.2 Electrical Specifications and Bus Configurations

An RSDS interface circuit is shown in Fig. 2.13. The interface contains three parts: a transmitter, receivers and a balanced interconnecting medium with a termination. The transmitter and receiver are defined in terms of direct electrical measurements in Table 2.4.

The RSDS is a versatile interface that may be configured differently depending upon the end application requirements. Considerations include the location of the timing controller (TCON), the resolution and the color depth of the flat panel displays.

z Type 2 – Multi-drop bus with single end termination.

z Type 3 – Double multi-drop bus with single termination.

In a type 1 configuration, the source (TCON) is located in the middle of the bus via a short stub as shown in Fig. 2.14. The bus is terminated at both ends with a nominal termination of 100 Ω. The interconnecting medium is a balanced coupled pair with nominal differential impedance of 100 Ω. The number of RSDS data pairs is 9 or 12 depending upon the color depth supported. In this configuration, the RSDS driver which is at the output part of the TCON will see a DC load of 50 Ω instead of 100 Ω.

For this case, output drives of the RSDS driver must be adjusted to comply to the VOD

specification with the 50 Ω load presented by the type 1 configuration.

In a type 2 configuration, as shown in Fig. 2.15, the source (TCON) is located at one end of the bus. The bus is terminated at the far end with a nominal termination of 100 Ω. The interconnecting medium is a balanced coupled pair with nominal differential impedance of 100 Ω. The bus may be a single or dual bus depending upon the resolution of flat panel displays. The number of RSDS data pairs is 9 or 12 depending upon the color depth supported for a single bus. Or the number of RSDS data pairs is 18 or 24 depending upon the color depth supported for a dual bus.

In a Type 3 configuration, the source (TCON) is located in the center of the application. There are two buses out of the TCON that run to the right and left

In a Type 3 configuration, the source (TCON) is located in the center of the application. There are two buses out of the TCON that run to the right and left