C O - DESIGNED I/O B UFFERS WITH B OTH LVDS AND RSDS S TANDARDS

4.4.1 Basic Concept

Fig. 4.16 shows the proposed co-designed output buffer with both LVDS and RSDS standards. The output buffer is utilized to transmit preceding serialization

full-swing (3.3 V) data along transmission materials to the receiver with low output voltage swing, such as LVDS standard (+/- 350 mV) or RSDS standard (+/- 200 mV).

The circuit block at the input (VIN) of the co-designed output buffer is to convert single data to differential data. The detailed circuit implementation of the single-ended-to-differential conversion circuit is shown in Fig. 4.17, which is used to switch four MOS switches (the M1 - M4 in Fig. 4.16) in the bridge configuration.

When a logical “1” (3.3 V) signal is arrived at the input of the output buffer, the node 1 and node 2 in Fig. 4.17 are charged to 3.3 V, and then node 3 is discharged to 0 V.

This leads to the VOUTN at logical “0” (0 V) and the VOUTP at logical “1” (3.3 V). On the contrary, when input signal is logical “0” (0V), the circuit causes the VOUTP at logical “0” (0 V) and VOUTN at logical “1” (3.3 V). The core circuit of the output buffer, as shown in Fig. 4.16, is the four MOS switches, which are realized by the typical configuration of two current sources at the top and one current source at the bottom. The output buffer acts as a current source with switched polarity. The appropriate output current flows through the termination resistance in order to correctly establish the differential output voltage swings to meet the LVDS standard or RSDS standard. The polarity of the output current is positive together with the differential output voltage with M2 and M3 switched on, and the output current is negative together with the differential output voltage with M1 and M4 switched on.

Since the data rate of this buffer is up to gigabits-per-second range, the mismatch of impedance between I/O interfaces may cause reflection of signal energy during data transmission which destroys signal quality. Therefore, double termination scheme is used in this co-designed output buffer to minimize signal reflection. However, double termination has the drawback of larger power consumption. The termination resistors

In order to strictly keep the output offset voltage within the voltage range that defined in LVDS and RSDS standards, a common-mode feedback circuit is used in the output buffer. The common-mode voltage is sensed by two high resistors RA1 - RB1 (RA1 = RB1 = 100 kΩ) and compared with a 1.25 V reference by the differential amplifier M8 - M13. Furthermore, the resistor RA2 of 20 kΩ is designed to reduce noise on the common- mode voltage (VCM) that sensed by RA1 - RB1. RB2 (20 kΩ) is added to balance the differential input pair, M8 - M9. A compensation network CC - RC (CC = 6pF and RC = 4 kΩ) is added in the loop of the common-mode feedback circuit to achieve good stability over PVT variations.

Two control pins, LR and EN, are used to determine the co-designed output buffer for applications in the LVDS standard, RSDS standard, or in the sleep mode.

As shown in Fig. 4.16, when the LR is logical “1” (3.3 V) and the EN is logical “1”

(3.3 V), two current mirror circuits provide appropriate current to M5 - M6 in order to establish the differential output voltage swing of LVDS standard. On the contrary, when the LR is logical “0” (0 V) and the EN is logical “1” (3.3 V), the right side current mirror circuit is turned off by M28 and the left side current mirror circuit provide current to M6, which establishes the voltage swing of RSDS standard at the output of the co-designed output buffer. The co-designed output buffer is in sleep mode when the EN is logical “0” (0 V) and the input of the co-designed output buffer is clamped to logical “1” (3.3 V), the two current mirrors are turned off by M28 - M29 with M22 - M27 to further avoid any possible current path except leakage current (measured under µA order). Fig. 4.18 shows the simulated both LVDS standard (top) and RSDS standard (bottom) output differential signals, which are transmitted at 1.2 Gb/s over two 1.44-mm-width, 3-cm-long 50-Ω micro-stripe lines. The thickness of printed circuit board (PCB) is 0.6-mm and the dielectric constant of the PCB is 4.5 to realize such 50 Ω micro-stripe lines. The simulation includes the package model (DIP

28-pin) with parasitic RLC and a 10-pF capacitive loading at differential outputs.

Fig. 4.19 shows the co-designed receiver input buffer with both LVDS and RSDS standards. The input buffer is designed to correctly sense an incoming low-voltage differential signal and convert it to a single-ended full-swing (3.3 V) signal, which can be processed by following circuits. The NMOS differential pair (M1 - M2) is used to sense an incoming low-voltage differential signal of both LVDS and RSDS standards. However, M3 - M4 is a positive feedback circuit which can quickly obtain a larger differential voltage swing at node 1 and node 2. The circuit at the top in Fig. 4.19 is a differential-to-single-ended converter, which can further amplify the differential signal between node 1 and node 2 in Fig. 4.19 and convert it to a single-ended full-swing signal with 50 % duty cycle. The input buffer is in sleep mode when the control pin EN is logical “0” (0 V), and the output of the input buffer is clamped to logical “0” (0 V) by M5. The simulated waveforms are shown in Fig. 4.20, where the dotted line is a differential input pattern provided to the input buffer under the worst case condition (VOD = ± 100 mV). However, the solid line is an output pattern, which can be recovered to a single-ended full-swing (3.3 V) pattern in order to be processed by the following circuits. Both input and output patterns in Fig. 4.20 are simulated with the operating speed of 1.2 Gb/s. Fig. 4.21 is the AC response of the input buffer. It shows that the DC gain of the input buffer is still enough (more than 24.3 dB) at the desired operation data rate (1.2 Gb/s).

4.4.2 Measurement Result

Fig. 4.22 shows the die photo of the I/O buffers which are fabricated in a 0.25-µm 1P5M CMOS process with the 3.3 V power supply. The chip area of the

buffer is shown in Fig. 4.9 except that the differential input is changed to the single input. The measurement setup of the co-designed input buffer is also shown in Fig.

4.9 except that the differential output is changed to the single output. The measurement setup that connects the co-designed output buffer and input buffer is shown in Fig. 4.23. Fig. 4.24 shows the measured LVDS eye diagram of the co-designed output buffer at 840 Mb/s when the control pin LR is switched to logical

“1” (3.3 V). Fig. 4.25 shows the measured RSDS eye diagram of the co-designed output buffer at 840 Mb/s when the control pin LR is switched to logical “0” (0 V).

Figs. 4.26 and 4.27 show the measured LVDS and RSDS eye diagram of the co-designed output buffer at 1.2 Gb/s when the control pin LR is switched to logical

“1” (3.3 V) and logical “0” (0 V). The co-designed output buffer is in sleep mode when the control pin EN is logical “0” (0 V) and the measured current consumption is under µA range with the input of the co-designed output buffer is clamped to logical

“1” (3.3 V). Fig. 4.28 shows the measured output signal of the receiver input buffer at 400 MHz. The input differential signal is at the worst case (VOD = ± 100 mV) defined in LVDS and RSDS standards and the output signal is a single-ended full-swing signal with 50 % duty cycle. Fig. 4.29 shows the measured eye diagram of the receiver input buffer at 400 Mb/s. Fig. 4.30 shows the measured output signal of the receiver input buffer at 600 MHz. Fig. 4.31 shows the measured eye diagram of the receiver input buffer at 600 Mb/s. Fig. 4.32 shows the measured output signal of the receiver input buffer at 840 MHz. Fig. 4.33 shows the measured eye diagram of the receiver input buffer at 840 Mb/s. Fig. 4.34 shows the measured output signal of the receiver input buffer at 1.2 GHz. Due to the capacitive loading of the oscilloscope the output signal voltage swing shrinks as the operation frequency rises. The output signal is clamped to logical “0” (0 V) when the control pin EN is switched to logical “0” (0 V) and the current consumption is measured under µA range. Figs. 4.35, 4.36 and 4.37 show the

measured eye diagram of the I/O buffers which are connected together via two coaxial cables at 300 Mb/s, 400 Mb/s and 600 Mb/s. The measured parameters of the I/O buffers are summarized in Table 4.2.

4.4.3 Conclusion

The co-designed I/O buffers with both LVDS and RSDS standards can be operated at very high speed. They also have variety applications one of which is in the flat panel display systems. The eye diagram which is at 840 Mb/s can support the SXGA (1280 × 1024 pixels) resolution of the flat panel displays and the eye diagram which is at 1.2 Gb/s can support the UXGA (1600 × 1200 pixels) resolution of the flat panel displays. These co-designed I/O buffers can be used in the transmitter which is utilized in the flat panel display systems will be discussed in the later chapter.

Table 4.1

The measured parameters of the LVDS output buffer.

Function LVDS Output Buffer

Operate Voltage 2.5 V

Current Consumption 17.2 mA@840 Mb/s

Power Consumption 43 mW@840 Mb/s

Data Rate Target at 840 Mb/s

(Measured up to 1.2 Gb/s)

Technology VIS 0.25-µm 1P5M CMOS

Table 4.2

The measured parameters of the co-designed I/O buffers.

Function Co-Designed Output Buffer

Operate Voltage 3.3 V

Technology VIS 0.25-µm 1P5M CMOS

Function Co-Designed Input Buffer

Operate Voltage 3.3 V

Data Rate Measured up to 1.2 GHz

Power Consumption 120.6 mW@840 Mb/s

Technology VIS 0.25-µm 1P5M CMOS

Sleep Mode

EN = 0 V, RL = 0 V or 3.3 V

Measured current consumption is under µA range

Fig. 4.1 Schematic of the taper buffer.

Fig. 4.3 The die photo of the taper buffer and the LVDS output buffer.

Fig. 4.4 The measurement setup of the taper buffer.

Fig. 4.5 The output signal of the taper buffer at 120 MHz. The capacitive loading of the oscilloscope is 13 pF (@1 MΩ).

Fig. 4.6 The output signal of the taper buffer at 200 MHz. The capacitive loading of

Fig. 4.7 The output signal of the taper buffer at 280 MHz. The capacitive loading of the oscilloscope is 13 pF (@1 MΩ).

Fig. 4.8 Schematic diagram of the LVDS output buffer.

Fig. 4.9 The measurement setup of the LVDS output buffer.

Fig. 4.10 The measurement setup of the LVDS output buffer which uses two coaxial cables.

Fig. 4.12 The measured eye diagram of the output buffer at 840 Mb/s without coaxial cables. The peak-to-peak jitter is 9.19 % and the worst case jitter is 17 %.

Fig. 4.13 The measured eye diagram of the output buffer at 840 Mb/s with coaxial cables. The peak-to-peak jitter is 10.5 % and the worst case jitter is 21.5 %.

Fig. 4.14 The measured eye diagram of the output buffer at 1.2 Gb/s without coaxial cables. The peak-to-peak jitter is 18.75 % and the worst case jitter is 30 %.

Fig. 4.16 Schematic diagram of the co-designed output buffer with both LVDS and RSDS standards.

Fig. 4.17 The circuit implementation for the single-ended-to-differential conversion circuit.

Fig. 4.18 Simulation of both LVDS standard (top) and RSDS standard (bottom) output voltage swings with a 101101100100 input pattern transmitted at 1.2 Gb/s.

Fig. 4.19 Schematic diagram of the co-designed receiver input buffer with both LVDS and RSDS standards.

Fig. 4.20 Simulation of the co-designed receiver input buffer at 1.2 Gb/s. The dotted line is a 101101100100 differential input pattern provided to the input buffer. The solid line is a recovered single full-swing output pattern.

Fig. 4.21 AC response of the receiver input buffer.

Fig. 4.22 The die photo of the co-designed I/O buffers.

Fig. 4.23 The measurement setup of the co-designed I/O buffers.

Fig. 4.24 The measured eye diagram of the output buffer operating in the LVDS standard at 840 Mbps with 2²³-1 PRBS. The measured power consumption is 42 mW.

The peak-to-peak jitter is 23.6 %.

Fig. 4.25 The measured eye diagram of the output buffer operating in the RSDS standard at 840 Mbps with 2²³-1 PRBS. The measured power consumption is 28 mW.

The peak-to-peak jitter is 26.26 %.

Fig. 4.26 The measured eye diagram of the output buffer operating in the LVDS standard at 1.2 Gbps with 2²³-1 PRBS. The measured power consumption is 44 mW.

The peak-to-peak jitter is 33.75 %.

Fig. 4.27 The measured eye diagram of the output buffer operating in the RSDS

23

Fig. 4.28 The measured output signal of the receiver input buffer at 400 MHz. The output signal is a single-ended full-swing signal with 50 % duty cycle and the input differential signal is at the worst case (VOD = ± 100 mV) defined in LVDS and RSDS standards.

Fig. 4.29 The measured eye diagram of the receiver input buffer at 400 Mb/s. The peak-to-peak jitter is 12.94 %.

Fig. 4.30 The measured output signal of the receiver input buffer at 600 MHz. The output signal is a single-ended full-swing signal with 50 % duty cycle and the input differential signal is at the worst case (VOD = ± 100 mV) defined in LVDS and RSDS standards.

Fig. 4.32 The measured output signal of the receiver input buffer at 840 MHz. The output signal is a single-ended full-swing signal with 50 % duty cycle and the input differential signal is at the worst case (VOD = ± 100 mV) defined in LVDS and RSDS standards.

Fig. 4.33 The measured eye diagram of the receiver input buffer at 840 Mb/s. The peak-to-peak jitter is 48.2 %.

Fig. 4.34 The measured output signal of the receiver input buffer at 1.2 GHz. The output signal is a single-ended full-swing signal with 50 % duty cycle and the input differential signal is at the worst case (VOD = ± 100 mV) defined in LVDS and RSDS standards.

Fig. 4.36 The measured eye diagram of the I/O buffers which are connected together via two coaxial cables at 400 Mb/s. The peak-to-peak jitter is 13.7 %.

Fig. 4.37 The measured eye diagram of the I/O buffers which are connected together via two coaxial cables at 600 Mb/s. The peak-to-peak jitter is 58.2 %.

Chapter 5 Transmitter

5.1 INTRODUCTION

As the high-speed output buffers which are mentioned in the chapter 4 can successfully support the data rate up to 1.2 Gb/s, they can be embedded in the transmitter to have variety applications [20], [21]. In this chapter, a transmitter utilized in the interface that directly connect a graphics card to a liquid crystal display (LCD) timing controller of the flat panel display systems is proposed [22]. Fig. 5.1 shows the block diagram of the transmitter. The transmitter converts 28 bits of TTL data into four LVDS data streams. It means that each LVDS data stream contains seven serial data. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmitted clock, 28 bits of input TTL data are sampled and transmitted. Fig. 5.2 shows the more detail circuit blocks of the transmitter.

5.2 BUILDING BLOCKS OF THE TRANSMITTER

In this section, each component of the transmitter which is shown in Fig. 5.3 will be discussed [23].

random, but is actually a predictable and repeatable sequence with a very long interval, depending upon the pattern. A PRBS is an algorithmically determined bit sequence that has the same statistical characteristics as a truly random sequence and simulates live traffic. The transmitter has a PRBS generator as shown in Fig. 5.4, it uses D-type flip flops and one OR logic gate to realize algorithmically determined bit sequence.

The circuit implementation of the D-type flip-flop which is utilized in the PRBS is true single-phase clock logic (TSPC) as shown in Fig. 5.5. The RESET pin in the PRBS is employed to trigger the PRBS in case of the all zero state and the CLK pin is connected to the external pulse generator in order to generate the same frequency pseudo random patterns as the external clock source. When the RESET pin is logic low, the PRBS is forced to enable. After a while, the RESET pin should be changed to logic high in order to keep the patterns correct. Since the PRBS is not really random but a predetermined sequence of ones and zeroes, the data can be captured and checked for errors. The bit length of the PRBS is 2⁹-1. Fig. 5.6 shows the simulated output signals of the seven PRBS outputs.

5.2.2 Phase-Locked Loop

The architecture of the PLL which is used in the transmitter is almost the same as the one mentioned in the chapter 3. Fig. 5.7 shows the architecture of the PLL. The seven NAND logic gates in the PLL is employed to make a four to three duty cycle of the seven output clocks in order to perform the parallel to serial conversion better. Fig.

5.8 shows the circuit implementation of the phase frequency detector. Fig. 5.9 shows the circuit implementation of the charge pump. Fig. 5.10 shows the circuit implementation of the self-biased replica-feedback bias generator. Fig. 5.11 shows the circuit implementation of the voltage-controlled oscillator. Fig. 5.12 shows the circuit implementation of the differential-to-single-ended converter. The simulated seven

output clocks with four to three duty cycle of the PLL are shown in Fig. 5.13. The simulated and measured parameters of the designed PLL are shown in Table 5.1.

5.2.3 Multiplexer and Co-Designed Output Buffer

Fig. 5.14 shows the circuit implementation of the multiplexer. It receives seven parallel output signals from the PRBS and uses seven phases came from the PLL to perform the parallel to serial conversion. Fig. 5.15 is the timing diagram of the multiplexer. The co-designed output buffer which follows the multiplexer is the same as the one mentioned in the chapter 4. The only difference is that four NMOS switches are used in order to have balance rise time and fall time of the output signals.

Fig. 5.16 shows the circuit implementation of the co-designed output buffer. Fig. 5.17 shows the main function of the transmitter. It can be realized that the data rate of the output signal is seven times higher than the input reference clock.

5.3 MEASUREMENT RESULT

Fig. 5.18 shows the chip photo of the transmitter which is fabricated in a 0.25-µm 1P5M CMOS process with the 3.3-V power supply. The chip area of the transmitter is 1500 µm × 1500 µm. The measurement setup of the transmitter is shown in Fig. 5.19. Fig. 5.20 shows the top view of the testing PCB photo for the transmitter.

One of the four data channels and the PLL channel are tested. Fig. 5.21 shows the bottom view of the testing PCB photo for the transmitter. The measured output signals of the transmitter which is in the LVDS or RSDS mode are shown in Figs. 5.22 and 5.23 respectively. The output signal voltage swings of the LVDS and RSDS mode are

Fig. 5.25 shows the measured RSDS eye diagram of the transmitter at 700 Mb/s. The peak-to-peak jitter is 25.15 %. Fig. 5.26 shows the measured LVDS eye diagram of the transmitter at 840 Mb/s. The peak-to-peak jitter is 31.5 %. Fig. 5.27 shows the measured RSDS eye diagram of the transmitter at 840 Mb/s. The peak-to-peak jitter is 32.8 %. Fig. 5.28 shows the measured LVDS eye diagram of the transmitter at 1.05 Gb/s. The peak-to-peak jitter is 26.25 %. Fig. 5.29 shows the measured RSDS eye diagram of the transmitter at 1.05 Gb/s. The peak-to-peak jitter is 27.89 %. All above eye diagrams are measured with package. In order to have better jitter performance, bare die with bond wires is tested on the PCB. Fig. 5.30 shows the measured LVDS eye diagram of the transmitter at 700 Mb/s by using bare die. The peak-to-peak jitter is 21.87 %. Fig. 5.31 shows the measured LVDS eye diagram of the transmitter at 840 Mb/s by using bare die. The peak-to-peak jitter is 18.4 %. Fig. 5.32 shows the measured LVDS eye diagram of the transmitter at 1.05 Gb/s by using bare die. The peak-to-peak jitter is 19.7 %. It is obvious that the jitter performance of the transmitter is better by using bare die rather than package. Figs. 5.33 and 5.34 show the measured output clock of the PLL at 120 MHz and 150 MHz. The duty cycle of the output

Fig. 5.25 shows the measured RSDS eye diagram of the transmitter at 700 Mb/s. The peak-to-peak jitter is 25.15 %. Fig. 5.26 shows the measured LVDS eye diagram of the transmitter at 840 Mb/s. The peak-to-peak jitter is 31.5 %. Fig. 5.27 shows the measured RSDS eye diagram of the transmitter at 840 Mb/s. The peak-to-peak jitter is 32.8 %. Fig. 5.28 shows the measured LVDS eye diagram of the transmitter at 1.05 Gb/s. The peak-to-peak jitter is 26.25 %. Fig. 5.29 shows the measured RSDS eye diagram of the transmitter at 1.05 Gb/s. The peak-to-peak jitter is 27.89 %. All above eye diagrams are measured with package. In order to have better jitter performance, bare die with bond wires is tested on the PCB. Fig. 5.30 shows the measured LVDS eye diagram of the transmitter at 700 Mb/s by using bare die. The peak-to-peak jitter is 21.87 %. Fig. 5.31 shows the measured LVDS eye diagram of the transmitter at 840 Mb/s by using bare die. The peak-to-peak jitter is 18.4 %. Fig. 5.32 shows the measured LVDS eye diagram of the transmitter at 1.05 Gb/s by using bare die. The peak-to-peak jitter is 19.7 %. It is obvious that the jitter performance of the transmitter is better by using bare die rather than package. Figs. 5.33 and 5.34 show the measured output clock of the PLL at 120 MHz and 150 MHz. The duty cycle of the output