C ONCLUSION

PLLs are analog building blocks used extensively in many analog and digital systems. Although PLLs are highly nonlinear systems, it has been found that when they are in lock, their transient behavior can be reasonably well approximated by linear differential equations. The designed PLL in this chapter has ten different phases of output signals which are 200 MHz. The tuning frequency of the PLL is from 80 MHz to 360 MHz. The main application of the designed PLL is to perform the parallel-to-serial conversion with a multiplexer which is used in a transmitter. The transmitter is utilized to transmit parallel video signals to the flat panel timing controller with high speed in flat panel display systems. In order to obtain a better performance transmitter, the embedded PLL should have good jitter performance and can resist supply and substrate noise.

Table 3.1

The simulated and measured parameters of the designed PLL.

Function PLL

Simulation Results

Operate Voltage 2.5 V

Input Frequency 25 MHz

Output Frequency 200 MHz

Charge Pump Current 50 µA

Loop Bandwidth 1.6 MHz

Extra Zero 0.34 MHz

Extra Pole 7.48 MHz

Natural Frequency 0.754 MHz

Damping Factor 1.1

Power 100 mW@200 MHz

Measurement Results

Technology VIS 0.25-µm 1P5M CMOS

Power 135 mW@200 MHz

Output Clock Jitter (1) 68 ps (long-term peak-to-peak jitter)@200 MHz, < 1.36 % Output Clock Jitter (2) 64 ps (long-term peak-to-peak

jitter)@25 MHz, < 0.16 %

Fig. 3.1 The basic architecture of PLL.

Fig. 3.2 The architecture of the designed PLL. The input reference clock frequency is 25 MHz and the output clock frequency is 200 MHz due to the frequency divider which is divided by eight.

Fig. 3.3 The circuit implementation of the PFD.

Fig. 3.4 The reference signal (Frefin) is earlier than the feedback signal (Fback). The output signal (UPP) is set to ground for a short duration after another output signal

Fig. 3.5 The reference signal (Frefin) and the feedback signal (Fback) are in-phase.

Both output signals (UPP and DOWNB) are altered from their initial states on every cycle in order to eliminate the dead zone region.

Fig. 3.6 The circuit implementation of the charge pump.

Fig. 3.7 Schematic of the loop filter.

Fig. 3.8 The loop filter which consists of one N-well resistor and two MOS capacitors.

Fig. 3.9 Simulation of the MOS capacitor. The Vctrl is 1.12 V when the PLL is

Fig. 3.10 Simulation of the MOS capacitor. The Vctrl is 1.12 V when the PLL is locked and the MOS capacitor C1 is in the accumulation region with the capacitor value 77.78 pF.

Fig. 3.11 The circuit implementation of the self-biased replica-feedback bias generator.

Fig. 3.12 Schematic of the five stages VCO.

Fig. 3.13 The circuit implementation of the individual delay cell.

Fig. 3.14 I-V curve of the symmetric load.

Fig. 3.15 Transfer curve of the VCO.

Fig. 3.16 The circuit implementation of the differential-to-single-ended converter.

Fig. 3.17 The circuit implementation of the divided-by-eight divider which consists of three divided-by-two dividers.

Fig. 3.18 Linear model of the PLL.

Fig. 3.19 The simulation of the PLL open loop using the parameters in Table 3.1.

Fig. 3.20 The SPICE simulation of the PLL closed-loop control voltage Vctrl.

Fig. 3.21 The SPICE simulation of the ten even-spaced output phases of the PLL.

Fig. 3.22 The linear model of the PLL with different noise sources.

Fig. 3.23 The die photo of the PLL.

Fig. 3.24 The measurement setup of the PLL.

Fig. 3.25 The top view of the testing PCB photo.

Fig. 3.26 The bottom view of the testing PCB photo.

Fig. 3.27 Ch1 is the measured signal of the VCO output (120 MHz) and Ch2 is the measured signal of the divider output (15 MHz).

Fig. 3.28 Ch1 is the measured signal of the VCO output (160 MHz) and Ch2 is the measured signal of the divider output (20 MHz).

Fig. 3.29 Ch1 is the measured signal of the VCO output (200 MHz) and Ch2 is the measured signal of the divider output (25 MHz).

Fig. 3.30 Ch1 is the measured signal of the VCO output (240 MHz) and Ch2 is the measured signal of the divider output (30 MHz).

Fig. 3.31 Ch1 is the measured signal of the VCO output (280 MHz) and Ch2 is the measured signal of the divider output (35 MHz).

Fig. 3.32 The jitter histogram of the divider output signal at 25 MHz.

Fig. 3.33 The jitter histogram of the VCO output signal at 200 MHz.

Chapter 4

High-Speed I/O Interface Circuits

4.1 INTRODUCTION

In today’s information-hungry society, how to speed up transmitting data over several inches even meters between computers or information electrical machines is more and more important. The data rate of transceiver is highly dependent on the I/O interface circuit of transceiver and the cable length. For many digital systems, the major performance limiting factor is the interconnection bandwidth between chips to chips or chips to boards. As process technologies continue to scale down, the on-chip data rate moves faster than the off-chip data rate and the interface between systems will become an even more significant bottleneck. Therefore, how to design high-speed I/O interface circuits is an important issue [15]. Besides, as the data rate of system is up to several gigabits-per-second range nowadays, the power consumption is another important issue. The design of high speed I/O interface circuits has led to concern on how to increase performance, decrease power consumption, reduce cost and mitigate noise or EMI. However, the above four factors are trade off to each other.

Four I/O interface circuits are going to be discussed in the following sections.

4.2 TAPER BUFFER

4.2.1 Basic Concept

The simplest circuit design of the I/O interface circuit is the taper buffer. The

taper buffer has several inverters which are connected one after another. It can receive data came from an internal system and transmit it over a connecting medium toward a receiver. The optimal scaling factor between those connected inverters is uopt (uopt = e

= 2.7182) which can achieve the minimum delay when driving different off-chip capacitance. Fig. 4.1 shows the schematic of the taper buffer, u is the scaling factor, CIN, C1 and C2 are the internal parasitic capacitances and CL is the off-chip capacitance.

4.2.2 Measurement Result

Fig. 4.2 shows the circuit design of the taper buffer. There are four inverters connected together. Fig. 4.3 shows the die photo of the taper buffer which is fabricated in a 0.25-µm 1P5M CMOS process with the 2.5 V power supply. The measurement setup of the taper buffer is shown in Fig. 4.4. The pulse generator (HEWLETT PACKARD 8133A) is utilized to generate the input signal of the taper buffer and the oscilloscope (Tektronix TDS 3054B) is used to obverse the taper buffer output signal. Figs. 4.5, 4.6 and 4.7 show the output signal of the taper buffer at 120 MHz, 200MHz and 280 MHz with the 13 pF capacitive loading at the oscilloscope.

According to the measured output signals, the signal amplitude degrades as the operation frequency increases. Besides, the square waveform of the output signal becomes sinusoidal as the operation frequency increases which means that the taper buffer can not be operated at high data rate.

4.2.3 Conclusion

The taper buffer is the simplest design of the I/O interface circuit. However, it

with huge power consumption. Other I/O interface circuits should be utilized instead of taper buffers in order to have better qualities of data transmission in the high speed data link era.

4.3 LVDSOUTPUT BUFFER

4.3.1 Basic Concept

Low voltage differential signaling (LVDS) is one kind of high-speed I/O interface technologies which is already discussed in the chapter 2 of this thesis. It can transmit data with high speed and low power consumption. The circuit implementation of the designed LVDS output buffer is shown in Fig. 4.8 [16], [17]. It behaves as a current source with switched polarity. The output current flows through the load resistance, establishing the correct differential output voltage swing (350 mV typically). It uses the typical configurations with four MOS switches in bridge configuration (M1 - M4), with M1 and M3 switched on, the polarity of the output current is positive together with the differential output voltage. On the contrary, if M2 and M4 are switched on, the polarity of the output current and voltage is reversed.

Since the proposed output buffer is intended for operation in the gigabits-per-second range, the double termination scheme is used and the termination resistors are integrated in the output buffer (RT-T) and in the receiver input buffer (RT-R) [18], [19].

With a nominal 100 Ω load at the front end of the receiver input buffer, both the common-mode voltage and the differential voltage swing at the output should fall within the LVDS standard specifications over the full range of process, supply voltage and temperature variations. Since this design aims at minimizing the PCB complexity and the production costs, external components and voltage references should be avoided together with wafer-level trimming. In order to define the correct output

levels, a simple low-power common-mode feedback control circuit is implemented in the output buffer as shown in Fig. 4.8. The common-mode output voltage is sensed by means of a high resistive divider (RA and RB) and compared with a 1.25 V reference voltage by the differential amplifier M5 - M8. The fraction of the tail current IT

flowing across M7 and M8 is mirrored to MU and ML, respectively, thus forcing VCM

= 1.25 V. In order to develop the correct voltage swing on the 50 Ω load resistance (RT-T // RT-R), the bridge must be biased at IOUT = VOD nom / 50 Ω. To this aim, IT is set equal to IOUT / K, where K is the gain of current mirrors M8 - ML and M7 - MU, a large gain was used in order to make negligible the power consumption of the common-mode feedback circuit. A large stability margin over PVT variations is achieved for the common-mode feedback circuit by means of a pole-zero compensation network, RC - CC.

4.3.2 Measurement Result

Fig. 4.3 shows the die photo of the LVDS output buffer which is fabricated in a 0.25-µm 1P5M CMOS process with the 2.5 V power supply. The chip area of the LVDS output buffer is 230 µm × 400 µm. The measurement setup of the LVDS output buffer is shown in Fig. 4.9. The pulse generator (HEWLETT PACKARD 8133A) is utilized to generate the input differential signal of the LVDS output buffer and the oscilloscope (Tektronix TDS 754D) is used to obverse the differential output signals.

The external trigger source is employed to make the eye diagram of the differential output signal and the external resistor (RT-R) is utilized to be the resistor which is integrated in the front end of the receiver input buffer. The other measurement setup which uses two coaxial cables as connecting media is shown in Fig. 4.10. Fig. 4.11

GHz. Since the coaxial cable has good transmission qualities, it will have little influence on the jitter performance of the LVDS output signals. Figs 4.12 and 4.13 show the measured eye diagrams at 840 Mb/s without and with coaxial cables. Figs 4.14 and 4.15 show the measured eye diagrams at 1.2 Gb/s without and with coaxial cables. The peak-to-peak jitter and worst case jitter of the eye diagram are measured in order to determine the quality of the transmitted output signal. As mentioned in the chapter 2, commonly 5 %, 10 %, or 20 % is acceptable with 20 % jitter usually being an upper practical limit. More than 20 % jitter tends to close down the eye opening, making error-free recovery of NRZ data more difficult. The measured parameters of the output buffer at 840 Mb/s are summarized in Table 4.1.

4.3.3 Conclusion

As mentioned in the chapter 2, LVDS is one kind of I/O technologies, which is utilized to transmit data at very high data rate. It can eliminate trade off between speed, power consumption cost and noise with its low output voltage swing and differential transmission characteristics. It has variety applications, one of which is in the plat panel display system. In the following section, two new I/O buffers with both LVDS and RSDS technologies which are already discussed in the chapter 2 are proposed.

4.4 CO-DESIGNED I/OBUFFERS WITH BOTH LVDS AND RSDS STANDARDS

4.4.1 Basic Concept

Fig. 4.16 shows the proposed co-designed output buffer with both LVDS and RSDS standards. The output buffer is utilized to transmit preceding serialization

full-swing (3.3 V) data along transmission materials to the receiver with low output voltage swing, such as LVDS standard (+/- 350 mV) or RSDS standard (+/- 200 mV).

The circuit block at the input (VIN) of the co-designed output buffer is to convert single data to differential data. The detailed circuit implementation of the single-ended-to-differential conversion circuit is shown in Fig. 4.17, which is used to switch four MOS switches (the M1 - M4 in Fig. 4.16) in the bridge configuration.

When a logical “1” (3.3 V) signal is arrived at the input of the output buffer, the node 1 and node 2 in Fig. 4.17 are charged to 3.3 V, and then node 3 is discharged to 0 V.

This leads to the VOUTN at logical “0” (0 V) and the VOUTP at logical “1” (3.3 V). On the contrary, when input signal is logical “0” (0V), the circuit causes the VOUTP at logical “0” (0 V) and VOUTN at logical “1” (3.3 V). The core circuit of the output buffer, as shown in Fig. 4.16, is the four MOS switches, which are realized by the typical configuration of two current sources at the top and one current source at the bottom. The output buffer acts as a current source with switched polarity. The appropriate output current flows through the termination resistance in order to correctly establish the differential output voltage swings to meet the LVDS standard or RSDS standard. The polarity of the output current is positive together with the differential output voltage with M2 and M3 switched on, and the output current is negative together with the differential output voltage with M1 and M4 switched on.

Since the data rate of this buffer is up to gigabits-per-second range, the mismatch of impedance between I/O interfaces may cause reflection of signal energy during data transmission which destroys signal quality. Therefore, double termination scheme is used in this co-designed output buffer to minimize signal reflection. However, double termination has the drawback of larger power consumption. The termination resistors

In order to strictly keep the output offset voltage within the voltage range that defined in LVDS and RSDS standards, a common-mode feedback circuit is used in the output buffer. The common-mode voltage is sensed by two high resistors RA1 - RB1 (RA1 = RB1 = 100 kΩ) and compared with a 1.25 V reference by the differential amplifier M8 - M13. Furthermore, the resistor RA2 of 20 kΩ is designed to reduce noise on the common- mode voltage (VCM) that sensed by RA1 - RB1. RB2 (20 kΩ) is added to balance the differential input pair, M8 - M9. A compensation network CC - RC (CC = 6pF and RC = 4 kΩ) is added in the loop of the common-mode feedback circuit to achieve good stability over PVT variations.

Two control pins, LR and EN, are used to determine the co-designed output buffer for applications in the LVDS standard, RSDS standard, or in the sleep mode.

As shown in Fig. 4.16, when the LR is logical “1” (3.3 V) and the EN is logical “1”

(3.3 V), two current mirror circuits provide appropriate current to M5 - M6 in order to establish the differential output voltage swing of LVDS standard. On the contrary, when the LR is logical “0” (0 V) and the EN is logical “1” (3.3 V), the right side current mirror circuit is turned off by M28 and the left side current mirror circuit provide current to M6, which establishes the voltage swing of RSDS standard at the output of the co-designed output buffer. The co-designed output buffer is in sleep mode when the EN is logical “0” (0 V) and the input of the co-designed output buffer is clamped to logical “1” (3.3 V), the two current mirrors are turned off by M28 - M29 with M22 - M27 to further avoid any possible current path except leakage current (measured under µA order). Fig. 4.18 shows the simulated both LVDS standard (top) and RSDS standard (bottom) output differential signals, which are transmitted at 1.2 Gb/s over two 1.44-mm-width, 3-cm-long 50-Ω micro-stripe lines. The thickness of printed circuit board (PCB) is 0.6-mm and the dielectric constant of the PCB is 4.5 to realize such 50 Ω micro-stripe lines. The simulation includes the package model (DIP

28-pin) with parasitic RLC and a 10-pF capacitive loading at differential outputs.

Fig. 4.19 shows the co-designed receiver input buffer with both LVDS and RSDS standards. The input buffer is designed to correctly sense an incoming low-voltage differential signal and convert it to a single-ended full-swing (3.3 V) signal, which can be processed by following circuits. The NMOS differential pair (M1 - M2) is used to sense an incoming low-voltage differential signal of both LVDS and RSDS standards. However, M3 - M4 is a positive feedback circuit which can quickly obtain a larger differential voltage swing at node 1 and node 2. The circuit at the top in Fig. 4.19 is a differential-to-single-ended converter, which can further amplify the differential signal between node 1 and node 2 in Fig. 4.19 and convert it to a single-ended full-swing signal with 50 % duty cycle. The input buffer is in sleep mode when the control pin EN is logical “0” (0 V), and the output of the input buffer is clamped to logical “0” (0 V) by M5. The simulated waveforms are shown in Fig. 4.20, where the dotted line is a differential input pattern provided to the input buffer under the worst case condition (VOD = ± 100 mV). However, the solid line is an output pattern, which can be recovered to a single-ended full-swing (3.3 V) pattern in order to be processed by the following circuits. Both input and output patterns in Fig. 4.20 are simulated with the operating speed of 1.2 Gb/s. Fig. 4.21 is the AC response of the input buffer. It shows that the DC gain of the input buffer is still enough (more than 24.3 dB) at the desired operation data rate (1.2 Gb/s).

4.4.2 Measurement Result

Fig. 4.22 shows the die photo of the I/O buffers which are fabricated in a 0.25-µm 1P5M CMOS process with the 3.3 V power supply. The chip area of the

buffer is shown in Fig. 4.9 except that the differential input is changed to the single input. The measurement setup of the co-designed input buffer is also shown in Fig.

4.9 except that the differential output is changed to the single output. The measurement setup that connects the co-designed output buffer and input buffer is shown in Fig. 4.23. Fig. 4.24 shows the measured LVDS eye diagram of the co-designed output buffer at 840 Mb/s when the control pin LR is switched to logical

“1” (3.3 V). Fig. 4.25 shows the measured RSDS eye diagram of the co-designed output buffer at 840 Mb/s when the control pin LR is switched to logical “0” (0 V).

Figs. 4.26 and 4.27 show the measured LVDS and RSDS eye diagram of the co-designed output buffer at 1.2 Gb/s when the control pin LR is switched to logical

“1” (3.3 V) and logical “0” (0 V). The co-designed output buffer is in sleep mode when the control pin EN is logical “0” (0 V) and the measured current consumption is under µA range with the input of the co-designed output buffer is clamped to logical

“1” (3.3 V). Fig. 4.28 shows the measured output signal of the receiver input buffer at 400 MHz. The input differential signal is at the worst case (VOD = ± 100 mV) defined in LVDS and RSDS standards and the output signal is a single-ended full-swing signal with 50 % duty cycle. Fig. 4.29 shows the measured eye diagram of the receiver input buffer at 400 Mb/s. Fig. 4.30 shows the measured output signal of the receiver input buffer at 600 MHz. Fig. 4.31 shows the measured eye diagram of the receiver input buffer at 600 Mb/s. Fig. 4.32 shows the measured output signal of the receiver input buffer at 840 MHz. Fig. 4.33 shows the measured eye diagram of the receiver input buffer at 840 Mb/s. Fig. 4.34 shows the measured output signal of the receiver input buffer at 1.2 GHz. Due to the capacitive loading of the oscilloscope the output signal voltage swing shrinks as the operation frequency rises. The output signal is clamped

“1” (3.3 V). Fig. 4.28 shows the measured output signal of the receiver input buffer at 400 MHz. The input differential signal is at the worst case (VOD = ± 100 mV) defined in LVDS and RSDS standards and the output signal is a single-ended full-swing signal with 50 % duty cycle. Fig. 4.29 shows the measured eye diagram of the receiver input buffer at 400 Mb/s. Fig. 4.30 shows the measured output signal of the receiver input buffer at 600 MHz. Fig. 4.31 shows the measured eye diagram of the receiver input buffer at 600 Mb/s. Fig. 4.32 shows the measured output signal of the receiver input buffer at 840 MHz. Fig. 4.33 shows the measured eye diagram of the receiver input buffer at 840 Mb/s. Fig. 4.34 shows the measured output signal of the receiver input buffer at 1.2 GHz. Due to the capacitive loading of the oscilloscope the output signal voltage swing shrinks as the operation frequency rises. The output signal is clamped