Chapter 1 Introduction ….…
2.4 Summary
High performance SPC poly-Si TFT integrated with Pr2O3 gate dielectric and TiN metal gate has been successfully demonstrated for the first time. This work provides the thinnest EOT of 6.5-nm from the high gate capacitance density of Pr2O3
film. The electrical characteristics of Pr2O3 TFT can be effectively improved compared to those of TEOS TFT, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, and higher driving current capability, even without additional hydrogenation treatment or advanced phase crystallization techniques. Therefore, the proposed Pr2O3 TFT is a good candidate for high performance TFT with low operation voltage.
Reference
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High-k process
● 500-nm thermal oxidation at 980oC
● 100-nmα-si deposition at 550oC by LPCVD
● SPC at 600oC for 24h in N2 ambient (α-Si Î poly-Si)
● Define active region
Buried Oxide ( 500nm) Si Substrate
Undoped Poly-Si (100nm)
● 33.6-nm Pr2O3film deposition by e-gun evaporation system
● Furnace annealing at 600oC for 30 min in N2ambient
● 200-nm TiN film by PVD
● Define gate electrode
Pr2O3gate dielectric (33.6nm) TiN gate electrode (200nm)
Buried Oxide ( 500nm) Si Substrate
Undoped Poly-Si (100nm)
● Self-aligned source/drain implantation (P+ 5x1015 90keV)
● Dopant activation at 600oC for 30min in N2 ambient
P+ion implantation
Buried Oxide ( 500nm) Si Substrate
N+ N+
TiN
● 300-nm passivation oxide SiO2by PECVD
● Define contact hole, two-step wet-etching process
● 400-nm Al pads
● N2/H2sintering at 400oC for 30min
Passivation (300nm) Al (400nm)
Buried Oxide ( 500nm) Si Substrate
TiN
N+ N+
Fig. 2.1 Schematic diagram of the combined TiN gate and Pr2O3 gate dielectric TFT.
T iN G a te E le c tr o d e
P r
2O
3(3 3 .6 n m )
P o l y -S i (9 7 n m )
In t e r f a c ia l la y e r ( 1 .5 n m )
Fig. 2.2 TEM image of the proposed gate stack structure.
Gate Votalge (V)
-4 -2 0 2 4
C/A (nF/cm
2)
0 100 200 300 400 500 600
κ = 26.2
EOT = 6.5 nm Cacc = 532 nF/cm2
Reverse switching with
repeating 100 cycles Initial forward switching - 4 V to + 4 V + 4 V to - 4 V
Fig. 2.3 Typical C–V characteristics of the Pr2O3 gate dielectric demonstrating the negligible hysteresis characteristics after repeating 100 forward and reverse cycles.
Gate Field (MV/cm)
0 2 4 6 8 10 12 14 16
Gate Current Densit y ( A /cm
2)
10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1
Area = 1.52X10-3cm2
Physical thickness = 33.6nm T=25oC
Fig. 2.4 J-E characteristic of the capacitors with Pr2O3 gate dielectric.
Binding Energy (eV)
920 930
940 950
960 970
Inte ns ity (a .u.)
Pr 3d
Pr 3d
3/2Pr 3d
5/220 eV
Fig. 2.5. Pr 3d photoelectron spectrum for Pr2O3.The inset also shows the O 1s photoelectron Spectrum which clearly indicates the presence of Pr2O3.
526 528
530 532
534 536
538 540
In te ns ity (a .u .)
Binding Energy (eV)
O 1S Pr-O
-2 0 2 4 6 8
Fig. 2.6 (a) Typical transfer characteristics (IDS-VGS) and (b) mobilityof the proposed TiN metal gate and high-κ Pr2O3 gate dielectric poly-Si TFT. (W/L=2µm/2µm)
Fig. 2.7 Typical output characteristics (IDS-VDS) of the proposed TiN metal gate and high-κ Pr2O3 gate dielectric poly-Si TFT. (W/L=2µm/2µm)
Pr2O3 TFT TEOS TFT
(VGS - VTH) = 1V to 4V Step = 1V
W/L = 2 m/2
0 1 2 3 4
0 20 40 60 80 100
Drain Cur rent, I
DS( µA)
Drain Voltage, V
DS(V)
35 nm/
Table 2.1 Comparison of device characteristics of the HfO2, LaAlO3, TEOS and Pr2O3
gate dielectric SPC poly-Si TFTs.
35 nm/ X
Table 2.2 Improvement of device characteristics of the TEOS and Pr2O3 gate dielectric SPC poly-Si TFTs.
Width = 2µm V
DS= 0.1 V
Gate Length (µm)
0 2 4 6 8 10
Threshold Voltage, V
TH(V)
0 1 2 3 4 5 6
Pr
2O
3TFT TEOS TFT
Fig. 2.8 Threshold-voltage rolloff of poly-Si TFTs with Pr2O3 and TEOS at VDS=0.1V
Chapter 3
Fluorine-Ion Implanted Poly-Si TFTs with High-κ Pr
2O
3Gate Dielectric
3.1 Introduction
The peripheral driving ICs of AMLCDs which is one of the major applications of poly-Si TFTs have the electrical characteristics requirement of low operation voltage, low threshold voltage, and high driving current. However, conventional solid-phase crystallization (SPC) poly-Si TFT with SiO2 as gate dielectric can not satisfy the needs. In order to address this issue, several high-κ gate dielectrics including HfO2 and LaAlO3 were proposed to increase the gate capacitance density for better gate controllability with keeping the thickness of physical gate dielectric [1-2]. In this thesis, we choose Praseodymium oxide (Pr2O3) high-κ material as the gate dielectric and its excellent performance was discussed in Chapter 2.
On the other hand, the detrimental GIDL current from the grain boundaries trap states was observed in the unhydrogenated poly-Si TFT [3]. Hence, in order to obtain desirable characteristics of polysilicon TFTs, many techniques had been employed to improve the device performance by reducing the trap-state density or increasing the grain size of the polysilicon. Hydrogenation is a popular method to improve the TFT performance[4-6]. However, H2-plasma treatment will loss their the passivation effect when the passivated samples are subjected to high temperature (>
500℃) annealing. Also, it had been found that the H2-plasma applied on a MOS
capacitor creates positive charges in the oxide, hence, causing an undesirable flat band voltage shift of the device [7-8]. Furthermore, it was reported that [9-10] TFTs suffer a low hot carrier endurance after the H2-plasma passivation. For the H2-plasma passivation, it is easy to passivate dangling bonds in grain boundaries to reduce the midgap deep states, while it needs a very long hydrogenation time (> 4 h) to passivate the strain-bond-related tail states [6]. However, it has been reported that the fluorine can break strained bonds, likely the strained Si-0-Si bonds and the Si-Si bonds to cause local strain relaxation [11-13] and to reduce the interface states [12]. Also, it was reported that fluorine may break a weak Si-H bond or a weak Si-OH bond to form a strong Si-F bond in its place at the Si/SiO2 interface. With the fluorine implantation in the Si/SiO2 interface, an MOS has a better irradiation and hot-carrier resistance . Recently, H. Kitajima et al. had found that F+ implantation is effective to increase the ON-current of polysilicon TFTs by improving their subthreshold swings [14]. In this chapter, we examine the effect of fluorine implantation incorporated Pr2O3 gate dielectic and TiN metal gate on the performance of TFTs, in particular Vth, On-current, driving current, mobility, active energy and trap state density. Finally, the reliability of TFT such as hot carrier stress will be measured to proof that fluorine implantation on high-κ material will be improved effectively
3.2 Experimental
The cross-section fabrication process of the proposed TFT device is shown in Figure 3.1 and the self-aligned TiN gate and high-κ Pr2O3 gate dielectric poly-TFTs with fluorine ions implantation were describe as follows. Undoped amorphous silicon (α-Si) films of 50 nm thickness were initially deposited on thermally oxidized silicon wafers by an low-pressure chemical vapor deposition (LPCVD) system at 550oC
followed by fluorine ions implantation into the α-Si film. The projected range of fluorine ions were set at the middle of a-Si layer and the implantation was performed without any pad oxide on a-Si. The dosage and ion accelerating energy was 5 × 1012 cm−2 and 11 keV, respectively. The F-implanted α-Si layer was subsequently recrystallized by a solid-phase crystallization (SPC) annealing at 600 οCfor 24 h in N2
ambient, and then patterned into the device active region. Next, a 40-nm Pr2O3 film was deposited by e-gun evaporation system as gate dielectric, followed by a furnace treatment at 600 οCfor 30 min in N2 ambient to improve the gate dielectric quality. A 200-nm TiN film was sequentially deposited by physical vapor deposition (PVD) and patterned to form the gate electrode. A self-aligned phosphorous ion implantation was applied at the dosage and energy of 5× 1015 cm-2 and 80 keV, respectively, followed by dopant activation annealing at 600oC for 30min in N2 ambient and a deposition of 300-nm plasma-enhanced CVD (PECVD) passivation layer. Subsequently, a two-step wet-etching process is used to open the contact holes. The passivation SiO2 and Pr2O3
film were etched away by buffered oxide etch (BOE) and H2SO4/H2O solution separately, which has rather high selectivity of Pr2O3/SiO2. Finally, a 400-nm Al film was deposited and patterned as the metal pad. Finally, the devices were sintered at 400 οC for 30 min in N2 ambient. For comparison, the control TFTs without fluorine ion implantation were prepared with the same process flow. No deliberate hydrogenation was performed, so that the “intrinsic” performance of the TFTs can be measured. For comparison, the control TFTs without the Nitrogen ion implantation were prepared with the same process flow. The electrical and reliability characteristics were performed by using HP 4156B.
The proposed TiN metal gate and Pr2O3 gate dielectric TFT structure is confirmed by transmission electron microscopy (TEM), as shown in Figure 3.2 which shows a physical thickness of Pr2O3 film around 40-nm. A high gate capacitance density of 463 nF/cm2 is obtained from capacitance-voltage (Cg-Vg) measurement, as shown in Figure 3.3. Therefore, a thin equivalent-oxide thickness (EOT) of 6-nm was extracted from the Pr2O3 thin film.
Many references show the SIMS (secondary ion mass spectroscopy) profiles of the fluorinated poly-Si films. The SIMS profile exhibit the substantial amount of fluorine were introduced into the poly-Si layer by Fluorine ion implantation. The SIMS analysis also shows a notably high concentration of fluorine atoms piling up near the SiO2/poly-Si interface, instead of in the deep poly-Si layer. Those results indicated that by employing this Fluorine implanted-treatment technique not only the fluorine atoms were introduced into the poly-Si but also the Si-F bonds were formed in the SiO2/poly-Si interface.
Therefore, these results figure that trap states in both grain boundaries and the SiO2/poly-Si interface were reduced by using Fluorine implanted treatment, which resulting the great improvement in the device performance. Based on these results, a schematic cross section view of the SiO2/poly-Si interface is illustrated in Figure 3.4.
It is suggested that strong Si-F bonds replace the dangling and strain bonds for the fluorinated poly-Si films, and thus improve the device performance.
Typical transfer characteristics IDS-VGS of the integrated TiN gate and high-κ Pr2O3 TFTs with and without Fluorine implanted treatment are shown in Figure 3.5.
The drawn channel length (L) and channel width (W) are 5µm and 10µm, respectively.
The measurements were performed at two different drain voltage of VDS=0.1 and 1V.
According to the method of parameter extraction in Chapter 1, the Vth and S.S. of the
fluorinated poly-Si TFT were found to be 0.735V and 200mV/dec. extracted from Figure 3.5, which are superior to those of the control one (1.54V and 278mV/dec.).
It’s know that the Vth and S.S. are strongly influenced by the deep trap states, associated with dangling bonds in the channel, which have energy states near the middle of the silicon band gap. Therefore, one can infer that Fluorine implanted treatment can terminate the dangling bonds in the poly-Si and SiO2/poly-Si interface.
Additionally, the ION , IOFF and ON/OFF current ratio of the fluorinated TFT are also better than those of the control TFT, because Fluorine implantation can cause the decrease of trap states which can assist the carrier generation in the depletion layer and increase the leakage current in the OFF state and capture carriers and form potential barriers, resulting in reduction of the carrier mobility and degradation of the ON current in the ON state.
Besides, while the applied gate voltage was toward negative, the fluorinated poly-Si TFT show smaller leakage current compared with that of the control TFT, i.e.
GIDL effect is suppressed. It is know that under a high electric field leakage current of the poly-Si TFT mainly comes from the trap-assisted band to band tunneling near the drain edge [15]. This observation suggest that there must be fewer trap states existed in the fluorinated poly-Si TFT, and thus the leakage current under a high electric field is reduced.
Figure 3.6 shows field-effect mobility versus the gate voltage of control and fluorinated poly-Si TFTs. The field-effect mobility was calculated from the value of transconductance at VDS=0.1V. The Fluorinated poly-Si TFT shows approximately 41% enhancement in the maximum field-effect mobility. Note that the filed-effect mobility is significantly affected by the tail states near the band edge, which is resulted from the strain bond in the poly-Si and SiO2/poly-Si interface [16]. These
results imply that Fluorine implanted treatment may not only terminate the dangling bonds, but also relieve the strain bonds.
Figure 3.7 shows the typical IDS-VDS output characteristics for the integrated TiN gate and Pr2O3 gate dielectric with Fluorine implanted -treated TFTs and control TFTs. The devices have a drawn channel length (L) of 5 µm and a channel width (W) of 10 µm, respectively. Clearly, the driving current of Fluorine implanted-treated TFT (about 150 µA/µm) is larger than that of control TFTs (about 95 µA/µm) at VDS = 4 V and VGS = 4 V. This is due to the higher mobility and smaller threshold voltage of the fluorinated poly-Si TFT. This large driving capability is desirable for high-speed display IC’s application resulted from the high gate capacitance density.
Figure 3.8 shows that the kink-point voltage (i.e. the voltage of kink-effect (also named “floating-body effect) occurred) versus different gate voltage extracted from Figure 3.7, and its mechanism is explained as follows [17-18]. For short gate length and high drain bias, the lateral electric field causes impact ionization near the drain, generating electron-hole pairs. These electrons contribute to the drain current, whereas the holes drift from the drain and gate regions toward the source and polysilicon-SiO2 interface regions. The presence of these holes raises the body potential, which may become large enough to forward bias the body-source diode.
When this occurs, the hole current flowing into the source results in injection of electrons into the body. These electrons flow along the field into the drain region, and the entire process repeats. This causes an increase in the drain current and a decrease in threshold voltage, as observed. By Fluorine ion implantation, the kink-effect can be reduced owing to the decrease of the trap state which is the location usually occurred impact ionization in the poly-Si bulk, and then the kink-point voltage will be raised as shown in the Figure 3.8.
The grain boundary trap state densities (NT) of the conventional and fluorinated high-κ gate dielectric poly-Si TFTs were estimated by Levison and Proano method [19-20] and we have demonstrated in Chapter 1. Figure 3.9 exhibits the plots of the ln[ID/(VGS-VFB)] versus 1/(VGS-VFB)2 curves at low VDS and high VGS. The fluorinated Pr2O3 high-κ gate dielectric poly-Si TFT exhibits a Nt of 4.58×1012 cm-2, whereas the control TFT has 14.4×1012 cm-2. This result implies that the Fluorine implantation treatment can terminate the grain boundary trap state in the poly-Si film.
To further study the fluorine passivation effect near the interface, the effective interface trap states densities (NIT) near the SiO2/poly-Si interface were also calculated. Form Chapter 1, we have known the effective interface trap states density equation which can be expressed as: NIT=[(S.S./ln10)(q/KT)-1](Cox/q). The NIT of the control TFT and the fluorinated high-κ gate dielectric TFT are 10.6×1012 cm-2 and 6.81×1012 cm-2, respectively. The value of grain boundary trap state densities (NIT) reflects trap states near the SiO2/poly-Si interface.
The key parameters were summarized in the Table. 3.1. Comparing with conventional TFTs, the TFT by utilizing Fluorine implanted treatment is performed prior high-κ deposition, Vth decreased from 1.54V to 0.735V, S.S. decreased from 278 mV/dec to 200 mV/dec, Ion/Ioff increased from 1.98×106 to 9.27×106 while VDS=1V grain boundary traps densities decreased from 14.4×1012cm-2 to 4.58×
1012cm-2, and interface trap states decreased from 10.6×1012 cm-2 to 6.81×1012 cm-2. Figure 3.10 exhibits the activation energy (Ea) versus the gate voltage for the control and fluorinated poly-Si TFTs at VDS=0.1V. In Off-region (low VGS), the value of Ea reflects the required energy for carriers to leak by means of traps, whereas in On-region (high VGS), the value of Ea reflects the carriers transport barrier caused by
the trap states within the poly-Si channel [21]. Compared with the control TFT, the extracted activation energy (Ea) of the fluorinated poly-Si TFT decreases in On-region and increases in Off-region. That is to say, for fluorinated poly-Si TFT, fluorine atoms can passivate the trap states and hence reduce the barrier height for carrier transport when device is turned on. On the other hand, in Off-region fewer trap states after fluorinating process resulting in the increasing of Ea and thus the trap-assisted leakage current is suppressed. Moreover, in the subthreshold region, a steeper profile can be found for the fluorinated TFT, which proves that the interface quality of the fluorinated TFT is much better than that of the control TFT.
Additionally, the hot carrier stress was carried out to examine the reliability pf the device. The drawn channel length (L) and channel width (W) are 10µm and 10µm,
Additionally, the hot carrier stress was carried out to examine the reliability pf the device. The drawn channel length (L) and channel width (W) are 10µm and 10µm,