Chapter 1 Introduction ….…
1.1 Brief Overview of Poly-Si Thin-Film Transistors
A thin-film transistor (TFT) is that a field-effect transistor is deposited on insulating substrate, and it utilizes a semiconductor thin film as its channel. For the channel using Silicon thin films, they are divided into amorphous silicon (α-Si) TFTs and polycrystalline silicon (poly-Si) TFTs.
Amorphous silicon (α-Si) TFTs have some issues. For example, their mobility are extremely low because the low temperature process results in mobile leaking from source to gate or scatters at the interface, and the grain boundaries cause mobile scattering during transport. In recent years poly-Si TFTs are considered that they are better candidates than α-Si TFTs due to their higher mobility (ranging from 10 to 300cm2/V-s) [1]. Therefore, polycrystalline silicon (poly-Si) thin film transistors (TFTs) have been widely used in a active-matrix liquid crystal displays (AMLCDs)[2].
The major application of poly-Si TFTs in AMLCDs lies in integrating the peripheral driving ICs, and the pixel switching elements on the glass substrate to realize system-on-panel (SOP) purpose[3]. Pixel TFTs need to operate at high voltages with low gate-leakage currents to drive the liquid crystal. In contrast, high-speed display circuits require that TFTs operate at low voltages and high driving currents with a low threshold voltage (Vth).
However, trap states of carriers at the poly-Si grain boundary cause the
degradation of electrical performance. In the ON state, the grain boundary traps capture carriers and form potential barriers, resulting in reduction of the carrier mobility. The effect will increase the threshold voltage and degrade the ON current as compared with single-crystalline Si MOSFET. In the OFF state, the grain boundary traps assist the carrier in generating in the depletion layer, and increase the leakage current. Therefore, reduction of trap states density in poly-Si channel is essential for fabricating high performance TFTs.
1.2 The Techniques of Performance Improvements
In order to obtain desirable characteristics of polysilicon TFTs, the major techniques had been employed to improve the device performance by reducing the trap state density or increasing the grain size of the polysilicon.. There are several methods to increase the grain size through SPC (solid phase crystallization)[4], ELA (excimer laser annealing)[5-6] and MILC (metal induced lateral crystallization)[7].
Furthermore, there are also many ways to reduce the trap-state density, such as plasma treatments or ion implantation. Various plasma such as H2[8], NH3[9], N2O[10], O2[11]
and CF4 plasma[12] have been intensely investigated in recent years. Besides, ion implantation, such as F+[13], N+[14], are incorporated into TFT poly-Si channel to terminate the poly-Si defects and then improve the performance.
Moreover, novel structure design is another approach to fabricate high-performance poly-Si TFTs. These techniques focus on reduction of the electrical field near the drain junction, and thus suppress the device's Off-state leakage current.
Many structures including multiple channel structures [15], offset drain/source [16-17], lightly doped drain (LDD) [18], gate-overlapped LDD [19-21], field induced drain [22] and vertical channel [23] have been proposed and investigated intensively.
1.3 Incorporating High-κ Gate Dielectric
Generally speaking, using a thin gate oxide can increase the driving current of TFTs. Unfortunately, for a conventional gate dielectric (i.e., SiO2 or Si3N4), a thinner gate dielectric may induce higher gate-leakage current and degrade the TFT characteristics significantly [24]. To preserve the physical gate-dielectric thickness while increasing the gate capacitance density and then improving the mobile carrier density in the channel region, high-κ gate-dielectric materials were suggested, such as Al2O3 [25], Ta2O5 [26], HfO2 [27].
The relation between gate capacitance and dielectrics constant and equivalent oxide thickness (EOT) is shown:
ox the relative permittivity of high-κ, tox is the oxide thickness, thigh-κ is the high-κ dielectric thickness.
Using the high-κ materials replace conventional oxide gate dielectric, attempts have been made to maintain these material amorphous even after post-deposition high temperature processing, in order to avoid surface roughness and grain boundary induced leakage current. In this thesis, we choose the excellent alternative which is the praseodymium oxide films[28].
1.4 Motivation
We choose the high-κ Pr2O3 material as the gate dielectric due to the high gate capacitance density and it can result in improving the mobile carrier density in the
channel region which is discussed in Chapter 2.
The trap states which are in the poly-Si TFT's channel and on the Si/poly-Si interface can trap carriers to form potential barriers, and thuss affect the current transport [29]. Moreover, the Off-current in poly-Si TFTs is associated with the amount of trap states in the drain depletion region. It can be attributed to thermionic emission at a low electric field and the field-enhanced emission (i.e. F-P emission or trap-assisted band-to-band tunneling) at a high electric field [30]. Hence trap states can lead to a poor device performance, such as low field-effect mobility, large leakage current, bad subthreshold slope and high threshold voltage.
Plasma treatments are believed to be the most effective methods to reduce trap states in the poly-Si. Many kinds of plasma such as H2/N2 mixture plasma [31], nitrogen implantation with H2 plasma [32], pre-oxidation NH3 annealing with H2
plasma [33], NH3 plasma [34] and H2/O2 plasma [35] have been proposed. Generally, hydrogen-based plasma is mostly adopted, because the hydrogen atoms can easily restore the trap states at the poly-Si/SiO2 interface and in the grain boundaries.
However, it is known that hydrogenated poly-Si TFTs have a troublesome issue in the device reliability [36-37]. The device performance degrades seriously under a long-term electrical stress. It is known that the poor device reliability of the hydrogenated TFTs is due to the weak Si-H and Si-Si bonds, which might be broken easily during the electrical stress and thus cause the creation of trap states in the poly-Si channel [38]. Recently, fluorination and technique has been proposed. It can improve both the device performance and also reliability, because the Si-F bonds are stronger than Si-H bonds [39-44]. So fluorine ion implantation (FII) technique is mostly adopted to introduce fluorine atoms into the poly-Si. Besides, the incorporation of nitrogen into the gate-dielectrics by different process has been widely
investigated to improve reliability [45-50]. The improved reliability is mainly due to the fact that most of the incorporated nitrogen can pile up at the gate-SiO2/Si interface to make the interface more robust and then to improve the hot-carrier immunity.
Moreover, the incorporation of nitrogen can also suppress boron penetration from the p+-polysilicon gate due to the formation of gate oxynitrides. In Chapter 3, we investigate the improvement by fluorine implantation incorporated Pr2O3 high-κ gate dielectric and TiN metal gate.
However, the method of ion implantation may be not suitable for large-area electronics. Moreover, a subsequent high temperature process, required to activate implanted atoms and recover the damage created by implantation, is an issue for the current AMCLD fabrication process. Therefore, effective and process-compatible techniques introduce fluorine atoms into the poly-Si channel are needed to be developed. In Chapter 4, an effective and process-compatible fluorine incorporated technique is proposed by fluorine-based plasma treatment. We have successfully combined TiN gate, Pr2O3 high-κ gate dielectric, and CF4 plasma to fabricate high-performance poly-Si TFTs.
1.5 Method of Device Parameter Extraction
In this thesis, we use HP 4156B-Precision Semiconductor Parameter Analyzer to measure the electrical characteristics of proposed poly-Si TFTs. Furthermore, we utilize FIB and TEM to see the cross-section view. The methods that we extract the characteristic parameters of poly-Si TFTs are described in this section.
1.5.1 Determination of Threshold Voltage
length-width and series resistance measurements. However, VTH is not uniquely defined. Various definitions have been proposed and the reason can be found in IDS-VGS curves. In this thesis, we use a simple method to determinate the Vth called constant drain current method. The voltage at a specified threshold drain current is taken as the Vth. This method is adopted in the most studied papers of poly-Si TFTs.
It canbe given a threshold voltage close to that obtained by the complex linear extrapolation method. Typically, the threshold current is specified at ID=(W/L)×100nA for VDS=0.1V and IDS=(W/L)×100nA for VDS=5V, where W and L is channel width and channel length, respectively.
1.5.2 Determination of Subthreshold Swing
Subthreshold swing (S.S) is a typical parameter to describe the control ability of gate toward channel, which reflects the turn on/off speed of a device. It is defined as the amount of gate voltage required to increase/decrease drain current by one order of magnitude.
The S.S. should be independent of drain voltage and gate voltage. However, in reality, the S.S. increase with drain voltage due to channel shortening effect such as charge sharing , avalanche multiplication and punch through effect. The subthreshold swing is also related to gate voltage due to undesirable and inevitable factors such as the serial resistance and interface states.
In this thesis, the S.S is defined as one-third of gate voltage required to decrease the threshold current by two order of magnitude. The threshold current is specified to be the drain current when the gate voltage is equal to threshold voltage.
1.5.3 Determination of Field Effect Mobility
The field-effect mobility is usually extracted from the maximum value of transconductance (Gm) at low drain bias (VD=0.1V). The drain current in the linear region (VDS < VGS-VTH) is expressed as the following equation
The transconductance Gm is gived by
D
Therefore, the field-effect mobility is
( ) DS
1.5.4 Determination of ON/OFF Current Ratio
On/off current ratio is one of the most important parameters of poly-Si TFTs since a high-performance device exhibits not only a large on-current but also a small off-current (leakage current). The leakage current mechanism in poly-Si TFTs is not like that in MOSFET. In MOSFET, the channel is composed of single crystalline Si and the leakage current is due to the tunneling of minority carrier from drain region to accumulation layer located in channel region. However, in poly-Si TFTs, the channel is composed of poly-Si. A large amount of trap state densities in grain structure attribute a lot of defect states in energy band gap to enhance the tunneling effect.
Therefore, the leakage current is much larger in poly-Si TFTs than in MOSFET. When the voltage drops between gate voltage and drain voltage increases, the band gap width decreases and the tunneling effect becomes much more severe. Normally we can find this effect in typical poly-Si TFTs’ IDS-VGS characteristics where the magnitude of leakage current will reach a minimum and then increase as the gate
There are a lot of ways to specify the on and off-current. In this thesis, take n-channel poly-Si TFTs for examples, the on-current is defined as the drain current when gate voltage at the maximum value and drain voltage is 1V. The off-current is specified as the minimum current when drain voltage equals to 1V.
V
1.5.5 Extraction of Grain Boundary Trap State Density
The Trap State Density (Nt), which can be determined by the theory established by Levinson et al. [51], which is based on Seto’s theory [52].
For poly-Si TFTs, the drain current IDS can be given as following:
⎟⎟
µFE : field-effect mobility of carriers q : electron charge
k : Boltzmann’s constant
εSi : dielectric constant of silicon T : temperature
Nt : trap-state density per unit area Lc : channel thickness
This expression, first developed by Levinson et al., is a standard MOSFET’s equation with an activated mobility, which depends on the grain-boundary barrier height. Levinson et al. assumed that the channel thickness was constant and equal to the thickness of the poly-Si film (t). This simplifying assumption is permissible only
for very thin film (t < 10nm). The trap-state density can be obtained by extracting a straight line on the plot of ln(IDS/VGS) versus 1/VGS at low drain voltage and high gate voltage.
Proano et al. [53] thought that a barrier approximation is to calculate the gate induced carrier channel thickness by solving Poisson’s equation for an undoped material and to define the channel thickness (Lc) as a thickness in which 80% of the total charges were induced by the gate. Doing so, one obtains
(
GS fb)
which varies inversely with (VGS−Vfb). This predicts, by substituting Eq.1.7 into Eq.1.6, that ln[IDS/(VGS−Vfb)] versus 1/(VGS−Vfb)2. We use the gate voltage at which minimum leakage current occurs as flat-band voltage (Vfb). Effective trap-state density (Nt) can be determined from the square root of the slope.
|
| slope q
Nt = Cox ………...(Eq.1.8)
1.5.6 Extraction of interface State Density
The effective interface trap states densities near (NT) the SiO2/Poly-Si interface were calculated from S.S. By neglecting the depletion capacitance in the active layer, the Nt can be expressed as [54]:
)
Where the Cox is the capacitance of the gate oxide and the S.S is subthreshold swing.
The Nt value reflect both interface states and grain boundary trap states near the SiO2/poly-Si interface.
1.5.7 Extraction of Active Energy
First, we measure the drain current versus the gate voltage for temperatures varying from 25 to 105℃. Then, we draw a plot of nature logarithm of drain current versus 1/KT at a fixed gate voltage and extract the absolute value of slope, i.e. the active energy EA. In this case, the thermal dependence of drain current is given by:
⎟⎠
1.6 Organization of the Thesis
This thesis is organized as follow:
In Chapter 1, the overview of poly-Si TFTs, the method of device parameter extraction, the reason for high-κ extraction and motivations of this thesis are described.
In Chapter 2, we discuss the advantage of Pr2O3 high-κ material and TiN metal gate. Furthermore, Pr2O3 high-κ gate dielectric perform significant improvements in the device performance, such as lower threshold voltage, improved subthreshold swing, enhanced field effect mobility, and higher ON/OFF current ratio can be achieved as compared to the TEOS TFT even without other hydrogenation treatment.
In Chapter 3, the fabrication process of poly-Si TFTs combined with Pr2O3
gate dielectric, TiN gate and fluorine ion implantation will be proposed. Then, we research into the improvement degree of electrical characteristic and reliability.
In Chapter 4, the electrical characteristics and fabrication process of the
solid-phase-crystallized (SPC) poly-Si TFTs with CF4 plasma treatment combined with Pr2O3 gate dielectric and TiN gate will be proposed. Also we explore its performance and reliability.
In Chapter 5, we will make conclusions and future works.
Reference
[1] S. Zhang, C. Zhu, J. Sin, J. Li and P. Mok, "Ultra-thin elevated channel poly-Si TFT technology for fully-integrated AMLCD system on glass," Electron Devices, IEEE Transactions on, vol. 47, pp. 569-575, 2000.
[2] T. Nishibe, “Low-temperature poly-Si TFTs by excimer laser annealing,” in Proc.
Mater. Res. Soc. Symp., 2001, vol. 685E, pp. D6.1.1–D6.1.5.
[3] B.-D. Choi, H.-S. Jang, O.-K. Kwon, H.-G. Kim, and M.-J. Soh, “Design of poly-Si TFT-LCD panel with integrated driver circuits for an HDTV/XGA projection system,” IEEE Trans. Consum. Electron., vol. 21, no. 3, pp. 100–103, Mar. 2000.
[4] Nakamura, F. Emoto, E. Fujii, A. Yamamoto, Y. Uemoto, H. Hayashi, Y. Kato and K.
Senda, "A high-reliability, low-operation-voltage monolithic active-matrix LCD by using advanced solid-phase-growth technique," Electron Devices Meeting, 1990.Technical Digest., International, pp. 847-850, 1990.
[5] G. Giust, T. Sigmon, J. Boyce and J. Ho, "High-performance laser-processed polysilicon thin-film transistors," Electron Device Letters, IEEE, vol. 20, pp. 77-79, 1999.
[6] N. Kusumoto, T. Inushima and S. Yamazaki, "Characterization of polycrystalline-Si thin film transistors fabricated by excimer laser annealing method," IEEE Trans.
Electron Devices, vol. 39, pp. 1876–1879, 1994.
[7] S. W. Lee, T. H. Ihn, S. K. Joo, S. Co and K. Do, "Fabrication of high-mobility p-channel poly-Si thin film transistors by self-aligned metal-induced lateral crystallization," Electron Device Letters, IEEE, vol. 17, pp. 407-409, 1996.
[8] A. Yin and S. Fonash, "High-performance p-channel poly-Si TFTs using electron cyclotronresonance hydrogen plasma passivation," Electron Device Letters, IEEE, vol. 15, pp. 502-503, 1994.
[9] C. K. Yang, T. F. Lei and C. L. Lee, "The combined effects of low pressure NH 3-annealing and H 2 plasma hydrogenation on polysilicon thin-film transistors,"
Electron Device Letters, IEEE, vol. 15, pp. 389-390, 1994.
[10] J. W. Lee, N. I. Lee, J. I. Kan and C. H. Han, "Characteristics of polysilicon thin-film transistor with thin-gate dielectric grown by electron cyclotron resonance nitrous oxide plasma," Electron Device Letters, IEEE, vol. 18, pp. 172-174, 1997.
[11] K. C. Moon, J. H. Lee and M. K. Han, "Improvement of polycrystalline silicon thin film transistor using oxygen plasma pretreatment before laser crystallization,"
Electron Devices, IEEE Transactions on, vol. 49, pp. 1319-1322, 2002.
[12] C. S. Lai, W. C. Wu, K. M. Fan, and T. S. Chao , “Effects of Post CF4 Plasma Treatment on the HfO2 Thin Film”, Jpn. J. Appl. Phys. Part1, 2005, Vol. 44, No. 4B, 2307-2310.
[13] H. N. Chern, C. L. Lee and T. F. Lei, "The effects of fluorine passivation on polysilicon thin-film transistors," Electron Devices, IEEE Transactions on, vol. 41, pp. 698-702, 1994.
[14] C. K. Yang, T. F. Lei and C. L. Lee, "Characteristics of top-gate thin-film transistors fabricated on nitrogen-implanted polysilicon films," Electron Devices, IEEE Transactions on, vol. 42, pp. 2163-2169, 1995.
[15] T. Unagami and O. Kogure, "Large on/off current ratio and low leakage current poly-Si TFTs with multi-channel structure," Electron Devices, IEEE Transactions on, vol. 35, pp. 1986-1989, 1988.
[16] B. H. Min, C. M. Park and M. K. Han, "A novel offset gated polysilicon thin film transistor without an additional offset mask," Electron Device Letters, IEEE, vol. 16, pp. 161-163, 1995.
[17] Z. Xiong, H. Liu, C. Zhu and J. Sin, "Characteristics of high-κ spacer offset-gated
polysilicon TFTs," IEEE Trans. Electron Devices, vol. 51, pp. 1304-1308, 2004.
[18] P. S. Shih, C. Y. Chang, T. C. Chang, T. Y. Huang, D. Z. Peng and C. F. Yeh, "A novel lightly doped drain polysilicon thin-film transistor withoxide sidewall spacer formed by one-step selective liquid phase deposition," Electron Device Letters, IEEE, vol. 20, pp. 421-423, 1999.
[19] K. Y. Choi and M. K. Han, "A novel gate-overlapped LDD poly-Si thin-film transistor," Electron Device Letters, IEEE, vol. 17, pp. 566-568, 1996.
[20] A. Bonfiglietti, M. Cuscuna, A. Valletta, L. Mariucci, A. Pecora, G. Fortunato, S.
Brotherton and J. Ayres, "Analysis of electrical characteristics of gate overlapped lightly doped drain (GOLDD) polysilicon thin-film transistors with different LDD doping concentration," Electron Devices, IEEE Transactions on, vol. 50, pp.
2425-2433, 2003.
[21] Y. Mishima and Y. Ebiko, "Improved lifetime of poly-Si TFTs with a self-aligned gate-overlapped LDD structure," Electron Devices, IEEE Transactions on, vol. 49, pp. 981-985, 2002.
[22] H. C. Lin, C. M. Yu, C. Y. Lin, K. L. Yeh, T. Y. Huang and T. F. Lei, "A novel thin-film transistor with self-aligned field induced drain," Electron Device Letters, IEEE, vol. 22, pp. 26-28, 2001.
[23] C. S. Lai, C. L. Lee, T. F. Lei and H. N. Chern, "A novel vertical bottom-gate polysilicon thin film transistor with self-aligned offset," Electron Device Letters, IEEE, vol. 17, pp. 199-201, 1996.
[24] A. Takami, A. Ishida, J. Tsutsumi, T. Nishibe and N. Ibaraki, "Threshold voltage shift under the gate bias stress in low-temperature poly-silicon TFT with the thin gate oxide film," Proc.Int.Workshop AM-LCD, pp. 45–48,
[25] Z. Jin, H. Kwok and M. Wong, "High-performance polycrystalline SiGe thin-film
transistors using Al2O3 gate insulators," Electron Device Letters, IEEE, vol. 19, pp.
502-504, 1998.
[26] M. Y. Um, S. K. Lee and H. J. Kim, "Characterization of Thin Film Transistor using Ta 2 O 5 Gate Dielectric," Proc.Int.Workshop AM-LCD, pp. 45–46,
[27] Chia-Pin Lin, Bing-Yue Tsui, Ming-Jui Yang, Ruei-Hao Huang, and Chao-Hsin Chien,” High performance poly-silicon thin film transistors using HfO2 gate dielectrics” Electron Device Letters, IEEE, vol. 27, 2006.
[28] H. Osten, J. Liu, P. Gaworzewski, E. Bugiel, P. Zaumseil and F. IHP, "High-κ gate dielectrics with ultra-low leakage current based on praseodymium oxide," Electron Devices Meeting, 2000.IEDM Technical Digest.International, pp. 653-656, 2000.
[29] G. Y. Yang, S. H. Hur and C. H. Han, "A physical-based analytical turn-on model of polysilicon thin-film transistors for circuit simulation," Electron Devices, IEEE Transactions on, vol. 46, pp. 165-172, 1999.
[30] K. Olasupo and M. Hatalis, "Leakage current mechanism in sub-micron polysilicon thin-film transistors," Electron Devices, IEEE Transactions on, vol. 43, pp.
1218-1223, 1996.
[31] M. J. Tsai, F. S. Wang, K. L. Cheng, S. Y. Wang, M. S. Feng and H. C. Cheng,
"Characterization of H2/N2 plasma passivation process for poly-Si thin film transistors (TFTs)," Solid State Electronics, vol. 38, pp. 1233-1238, 1995.
[32] C. K. Yang, T. F. Lei and C. L. Lee, "The combined effects of low pressure NH 3-annealing and H 2 plasma hydrogenation on polysilicon thin-film transistors,"
Electron Device Letters, IEEE, vol. 15, pp. 389-390, 1994.
[33] C. K. Yang, T. F. Lei and C. L. Lee, "The combined effects of low pressure NH
[33] C. K. Yang, T. F. Lei and C. L. Lee, "The combined effects of low pressure NH