Chapter 1 Introduction
1.2 Motivation
In the advanced integrated circuit technology, the channel length of MOSFET has been scaled down which require to reduce junction depth of source and drain minimize short channel effect. Into nanometer regime, the performance and electrical properties of CMOS will to support more difficulties. In next generation, high-k/metal gate stack technology is promising become to trend beyond the 45nm CMOS device, although it is need to be overcome more issue. The conventional junction of S/D required activation at high temperature annealing, but higher thermal budget will cause to affect the dopant concentration profile and the high-k dielectric crystallized. However, low temperature activation is required that formation ultra shallow junction for future CMOS technology. The formation shallow, abrupt, and activation junction is one of the main challenges for future minimize transistor dimension [21].
The Hf-base is possible alternative candidate for high-k dielectric in near term. The high-k dielectric will be crystallized at high temperature process, result in the gate leakage current increased. Since thermal reliability is playing an import role for high-k/metal gate stack, so we lead in NiSi to form metal gate material because of the NiSi has low and wide process windows. It is not only low process windows moreover would be to employ characteristic of NiSi to formation shallow and activation junction. In addition, the NiSi is a good diffusion source which the silicide as diffusion source (SADS) process has been proposed for the formation of silicide contacted shallow junction [22].
In parallel with the gate dielectric engineering to improve the thermal reliability of high-k dielectric, we are interesting in the project about low temperature activation. If the process temperature after gate dielectric formation can be lowered, the issue of high-k dielectric crystallized in process integration can also be minimized. We combined the concept of implant into silicide (IIS) and solid phase epitaxial regrowth (SPER) to control junction depth and junction activation. To make silicides with shallow junctions are to implant dopant through a deposited metal layer or silicided layer, called the implant into silicide. SPER works on the principle that dopants in an amorphous silicon region will activate to a level above the equilibrium solid solubility during crystalline regrowth.
These two methods lower the dopant activation temperature through the concept of change the surface energy of silicon and pile up the dopant concentration in NiSi/Si interface by dopant segregation and/or higher the solubility of the dopant in Si through the Si re-crystallization process.
Details about these two methods with our experiment will be discussed in the following chapters.
1.3 Organization of the Thesis
In this thesis, we concentrate our efforts on the activation of B and P implant through silicide by RTA process. However, studies the fabrication and characterization of the NiSi contacted NiSi/p+n and NiSi/n+p shallow junction diodes and NiSi/n+n and NiSi/p+p ohmic contact formed by implant into silicide.
In chapter 1, brief introduction metal-silicide technology history evolution
and the motivation of this thesis are mentioned.
In chapter 2, Formation of NiSi/p+n, NiSi/n+p Shallow Junction and NiSi/p+p, NiSi/n+n Metal-Semiconductor (MS) Junction.
In chapter 3, present Electrical Characteristics and Physical Properties of NiSi/p+p, NiSi/n+n Metal- Semiconductor (MS) Junction Using Implant Into Silicide.
In chapter 4, discuss Electrical Characteristics of NiSi/n+p, NiSi/p+n ultra shallow Junction Using Implant Into Silicide.
In chapter 5 is conclusions and future works.
1.4 References
[1] B. J. Pawl, R.Lindsay, R. Surdeanu, B. Dieu, L. Geenen, I. Hoflijk, O.
Richard, R. Duffy, TClarysse, B. Brijs, W. Vandervorst, C. J. J. Dachs, J. Vac.
Sci. Technol. B 22(1), Jan/Feb 2004, p.297-301.
[2] K. C. Saraswat and F. Mohammadi, IEEE Trans. Electron Devices, ED-29(1982) 645.
[3] D. B. Scott, W. R. Hunter and H. Shichijo, IEEE Trans. Electron Devices, ED-29(1982) 651.
[4] H. Berger and S. –Y. Lin, in S. Broydo and C. M. Osburn (eds.), ULSI Science and Technology, Vol. 87-11, Electrochemical Soc., Inc., Pennington, NJ, 1987, p.434.
[5] J. P Gambino, E. G. Colgan, Materials Chemistry and Physics 52 (1998) 99-146.
[6]. J. B. Lasky, J. S. Nakos, O. J. Cain and P. J. Geiss, IEDM Trans.
Electron Devices, ED-3458 (1991) 262.
[7] T. B. Massalski (ed.), Binary Alloy Phase Diagrams, ASM International, Materials Park, OH, 1990.
[8] K.Maex, Mater. Sci. Eng. Rev., R11 (1993) 53.
[9] J. K. Kittl, Q. Z. Hong, H. Yang, N. Yu, S. B. Samavedam, and M. A.
Gribelyuk, Thin Solid Films, 332, 404 (1998).
[10] K. Maex, A. Lauwers, P. Besser, E. Kondoh, M. de Potter, and A.
Steegen, IEEE Trans. Electron Devices, ED-46, 1545 (1999).
[11] J. B. Lasky, J. S. Nakos, O. J. Cain and P. J. Geiss, IEDM Trans.
Electron Devices, ED-3458 (1991) 262.
[12]T. Ohguro, S. Nakamura, E Morifuji, M. Ono, T. Yoshitomi, M. Saito, H.
S. Momose and H. lwai Tech. Dig. Int. Electron Devices Meet. 1995, 453.
[13] A. Lauwers, A. Steegen, M.de Potter, R. Lindsay, A. Satta, H. Bender and K. Maex, J. Vac. Sci. Technol. B. B19, 2026 (2001).
[14] C.-Y. Lu, J. J. Sung, R. Liu, N.-S. Tsai, R. Sing, S. J. Hillenius, and H.
C. Kirsch, IEEE Trans. Electron Devices 38, 246, (1991).
[15] Q. Wang, C. M. Osburn, C. A. Canovai, IEEE Trans. Electron Devices 39, 2486, (1992).
[16] R. Angelucci, S. Solmi, A. Armigliato, S. Guerri, M. Merli, A. Poggi, and R. Canteri, J. Appl. Phys. 69, 3962, (1991).
[17] B. S. Chen and M. C. Chen, IEEE Trans. Electron Devices 43, 258, (1996).
[18] R. Lindsay, S. Severi, B. J. Pawlak, K. Henson, A. Lauwers, X. Pages, A. Satta, R. Surdeanu, H. Lendzian, and K. Maex, IEEE 2004, p.70-75.
[19] S. Severi, B. J. Pawlak, R. Duffy, E. Augendre, K. Henson, R. Lindsay, and K. De Meyer, IEEE Electron Devices Letters, Vol. 28, NO. 3, March 2007, p.198-200.
[20] R. Duffy, M. Aboy, V. C. Venezia, L. Pelaz, S. Severi, B. J. Pawlak, P.eyben, T. Janssens, W. Vandervorst, J. Loo and F. Roozeboom, IEEE Trans. Electron Devices Vol. 53, NO. 1, January 2006, p.71-77.
[21] R. Lindsay, K. Henson, W. Vandervorst, and K. Maex, B. J. Pawlak, R.
Duffy, R. Surdeanu, and P. Stolk, J. A. Kittl, S.Giangrandi, X.Pages and K.
van der Jeugd, J. Vac. Sci. Technol. B 22(1), Jan/Feb 2004, p.306-311.
[22] C. C. Wang, C. J. Lin, M. C. Chen, Electrochemical Society, 150 (9) G557-G562 (2003).
Chapter 2
Formation of NiSi/p
+n, NiSi / n
+p Shallow Junction and NiSi/p
+p, NiSi/n
+n Metal-Semiconductor (MS) Junction
2.1 Introduction
Conventional p-n junctions were formed by ion implantation dopant into Si substrate followed by high temperature furnace annealing for dopant activation and implantation damage annihilation. Therefore, channeling effect and high temperature dopant diffusion limit the formation of shallow junction. This is particularly important for the p+n junction because boron is a light element and diffuses fast in silicon. Consequently, low temperature activation technique is more important in nanometer regime. In recent years, many advanced junction formation techniques have been studied, such as, preamorphization [1, 2, 3], low energy implantation [4, 5], gas-immersion laser doping (GILD) [6, 7], decaborane (B4H10) implantation [8, 9], implant into silicide (IIS) [13-16] and solid phase epitaxial regrowth (SPER) [17-21].
These new methods are briefly reviewed as follows:
(1) Pre-amorphization of silicon substrate before dopant implantation
Pre-amorphization has been widely used to control the channeling behavior of implanted dopant atoms. After the pre-amorphization of the silicon substrate surface layer, dopant implantation was performed followed
by crystal regrowth and annealing process for the junction formation. Many heavy atoms have been used as pre-amorphization species, such as Si and Ge.
Solid phase epitaxial (SPE) scheme can be used to regrow the crystal from the amorphous layer at a temperature as low as 550 ℃. The growth rate depends on the element used for pre-amorphization as well as the dopant implanted following the pre-amorphization. A careful annealing process is needed to annihilate the massive defects and dislocation induced by the pre-amorphization.
(2) Low energy ion implantation
This is an extension of the conventional ion implantation technique. The implantation energy is lower than 1 keV and the implantation dose is typically from 1×1014 to 5×1014 cm-2. The major disadvantage of this method is that no commercial implantation system of such a low energy ion beam is available for high throughput mass production with reasonable cost.
(3) gas-immersion laser doping (GILD)
The gas immersion laser doping (GILD) process is a candidate technology for shallow junction formation. Gaseous dopant precursors (BCl3) are chemisorbed on the silicon surface, and partially incorporated during the melting / recrystallisation of the Si top layer induced by an UV laser pulse (λ = 308 nm, pulse duration » 25 ns) [10]. The resulting thickness and dopant concentration of the doped layer depend on the laser energy density and the number of chemisorption / laser-induced incorporation cycles (up to 200). For the GILD technique both to eliminate the problems associated with ion implantation, and the unwanted diffusions that occur during the dopant activation anneals. Hence, GILD both have issues of Non-equilibrium phase
transformations and Strong dependence of recrystallized structure on the applied energy density.
(4) decaborane (B4H10) implantation
For CMOS scaling to nanometer region, particularly PMOSFET fabrication becomes more serious due to the difficulty of low energy boron ion implantation for source/drain (S/D). It can suppression of the boron diffusion which is caused by both transient enhanced diffusion (TED) and thermal diffusion (TD) that occur during the activation annealing. Therefore, implant boron atoms by conventional ion implantation is difficulty.
Decaborane implantation technology has been proposed using boron cluster [11, 12]. The cluster contain n boron atoms, only one charge per cluster is required to accelerate n boron atoms. Clusters can be transported at relatively high energy for shallow junction, due to low impact energy per boron atom. Decaborane are contains 10 boron atoms where the energy per boron atom is about 1/11 that of the energy of the molecule. Therefore, decaborane technology can to achieve forms a shallow junction with a low temperature RTA to prevent thermal diffusion after deep S/D formation with a relatively high temperature RTA to maintain a high gate capacitance (Cgox) and low contact resistance (Rc).
About above-mentioned methods, consideration high cost, massive defects and dislocation induced, high throughput mass production with reasonable cost and instrument and so on problems that make us inclined to use simpler, less damages and reach high dopant activation technology such as IIS and SPER. IIS and SPER technology were already discussed in chapter 1. Therefore, we conduct these two kinds of technology to formation
shallow junction in the experiment. IIS and SPER have played an important role while formation shallow junction in the future. IIS and SPER process potential advantages are more simples and effectively enhance activation than other method for formation of shallow junction. Briefly discuss advantages for IIS and SPER process. First, metal silicides have a larger nuclear stopping power than silicon for the implanted dopant and thus can reduce the channeling effect. Second, to formation shallow junction can greatly reduce ion implantation damages, due to ion implantation damages almost stay in the metal silicide. Third, silicides/silicon interface has thin amorphous silicon during silicidation process, in this time, we employ characteristic of SPER to raise dopant activation for shallow junction. In conventional process often make to pre-amorphous step which will increases more damages for shallow junction.
In this chapter, we investigate fabrication of NiSi/p+p, NiSi/n+n MS junction and NiSi/p+n, NiSi/n+p shallow junction. We would combine the dopant pile-up characteristic of IIS at interface and the ability of SPER to achieving the formation of shallow junction.
2.2 Experiment procedures
Samples were fabricated on p-type/n-type (100) oriented Si wafers. After a standard RCA clean process. Following, a 300 nm isolation oxide was grown on the wafer by wet oxidation at 1000℃ for 35 min. The active area regions were defined by the photolithography and etched by BOE (buffered oxide etchant) solution. Next, standard clean was used again to fully remove
the contamination. Following, a 200 Å Ni deposited on the wafer in a Dual E-gun Evaporation system with a base pressure of less than 2×10-6 torr, using a Ni target in vacuum ambient with a deposition rate of about 0.8- 1.2 Å/sec. After the Ni film deposition, the samples were rapid thermal annealed (RTA) at 400℃ for 30 sec in N2 ambient to form NiSi. The unreacted Ni film was selectively etched using a solution of H2SO4 : H2O2 = 3 : 1 at 75~85℃ for 45 sec. Then, the sample of NiSi were implanted with BF2+/P+ ions at an energy of 20 to a dose of 5×1013 cm-2. We deposited Ti on NiSi with lift-off technology. Before samples were coated the Ti 50nm by Dual E-gun Evaporation system which used photolithography to define the four-point probe measuring pads, next to removed PR by ACE. Samples were deposited TaN 150nm by DC sputtering system on backside. Finally, followed by rapid thermal anneal (RTA) at 450 to 600℃for 60 sec in N2 ambient for the activation dopant, as shown in Fig. 2.1. Process recipe is listed in Table 2.1 and Table 2.2.
2.3 References
[1] M. C. Ozturk, J. J. Wortman, C. M. Osburn, A. Ajmera, G. A. Rozgonyi, E. Frey, W. –K. Chu, and C. Lee, IEEE Trans. Electron Devices Lett., vol.
35, p. 659, 1998.
[2] C. –M. Lin, A. J. Steckl, and T. P. Chow, IEEE Electron Device Letters, vol. 9, p. 594, 1998.
[3]M. Minondo, J. Boussey, G. Kamarinos, and A. Mounib, IEE colloquium
on Advanced MOS and Bi-Polar Devices, 1995.
[4] S. Talwar, G. Verma, and K. H. Weiner, 1998 International Conference on Ion Implantation Technology Proceedings, vol. 2, p. 1171, 1998.
[5] K. –I Goto, J. Matsuo, Y. Tada, T. Tanaka, Y. Momiyama, T. Sugii, and I. Yamada, 1997 Technical Digest. International Electron Devices Meeting, p. 471, 1997.
[6] P. G. Carey, K. H. Weiner, and Thomas W. Sigmon, IEEE Electron Device Letters, vol. 9, p.542, 1988.
[7] E. Ishida and L. Larson, University/Convernment/Industry Microelectronics Symposium, 1995. , Proceedings of the Eleventh Biennial, p. 105, 1995.
[8] M. A Foad, R. Webb, R. Smith E. Jones, A. Al-Bayati, M. Lee, V.
Agrawal, S. Banerjee, J. Matsuo and I. Yamada, 1998 International Conference on Ion implantation Technology Proceedings, vol. 1, p. 106, 1998.
[9] K. Goto, J. Mastuo, T. Sugii, H. Minakata, I. Yamada, and T. Hisatsugu, 1996 International Electron Devices Meeting, p. 435, 1996.
[10] G. Kerrien, J. Boulmer, D. Débarre, D. Bouchier, A. Grouillet., D.
Lenoble, Appl. Surf. Sci. 186 (2002) 45
[11] M. A. Foad, J. England, S. Moffatt, and D. G. Armour, Proc. 11th Inr.
Conf On Ion Imp. Tech. -1996, IEEE, p.603,1997.
[12] K-I. Goto, J. Matsuo, T. Sugii, H. Minakata, I. Yamada, and T.
Hisatsugu, Novel shallow junction technology using decaborane (B10H14) IEDM Tech. Dig., pp.435-438, 1996.
[13] C.-Y. Lu, J. J. Sung, R. Liu, N.-S. Tsai, R. Sing, S. J. Hillenius, and H.
C. Kirsch, IEEE Trans. Electron Devices 38, 246, (1991).
[14] Q. Wang, C. M. Osburn, C. A. Canovai, IEEE Trans. Electron Devices 39, 2486, (1992).
[15] R. Angelucci, S. Solmi, A. Armigliato, S. Guerri, M. Merli, A. Poggi, and R. Canteri, J. Appl. Phys. 69, 3962, (1991).
[16] B. S. Chen and M. C. Chen, IEEE Trans. Electron Devices 43, 258, (1996).
[17] B. J. Pawlak, R. Lindsay, R. Surdeanu, B.Dieu, L. Geenen, I. Hoflijk, and O. Richard, R. Duffy, T. Clarysse, B. Brijs, and W. Vandervorst, C. J. J.
Dachs, J. Vac. Sci. Technol. B 22(1), Jan/Feb 2004, p.297-301.
[18] R. Lindsay, K. Henson, W. Vandervorst, and K. Maex, B. J. Pawlak, R.
Duffy, R. Surdeanu, and P. Stolk, J. A. Kittl, S.Giangrandi, X.Pages and K.
van der Jeugd, J. Vac. Sci. Technol. B 22(1), Jan/Feb 2004, p.306-311.
[19] R. Lindsay, S. Severi, B. J. Pawlak, K. Henson, A. Lauwers, X. Pages, A. Satta, R. Surdeanu, H. Lendzian, and K. Maex, IEEE 2004, p.70-75.
[20] S. Severi, B. J. Pawlak, R. Duffy, E. Augendre, K. Henson, R. Lindsay, and K. De Meyer, IEEE Electron Devices Letters, Vol. 28, NO. 3, March
2007, p.198-200.
[21] R. Duffy, M. Aboy, V. C. Venezia, L. Pelaz, S. Severi, B. J. Pawlak, P.eyben, T. Janssens, W. Vandervorst, J. Loo and F. Roozeboom, IEEE Trans. Electron Devices Vol. 53, NO. 1, January 2006, p.71-77.
Chapter 3
Electrical Characteristics and Physical Properties of NiSi/p
+p, NiSi/n
+n Metal- Semiconductor (MS) Junction Using Implant
Into Silicide.
3.1 Surface morphology by AFM inspection
In 1986, Binning et al. introduced another apparatus for surface characterization in atomic scale, the atomic force microscope (AFM). Since it can be applied to any types of material and environment, AFM has thus been used widely in surface characterization. Owing to its atomic scale resolution capability, AFM is also powerful equipment for nano-structure fabrication. We want to inspect the surface morphology of NiSi/ Si interface by AFM. Because of the roughness between the NiSi/ Si interface related to the junction leakage. We want to know the impact on roughness of temperature.
Fig. 3.1 AFM image shows NiSi/Si interface morphology by 2nd RTP annealing (a) 400℃ (b) 500℃ (c) 600℃ (d) 700℃ for 30 sec. Samples (n-type substrate, phosphorous doped) without 2nd RTA and with 2nd RTA 30sec at different temperatures (400, 500 ,600, and 700 ℃) are prepared.
The AFM inspection results for these samples (Area: 10μm x 10μm), and all RMS values are around 1nm. For the 2nd annealing sample, the interface roughness at 700℃ 30sec is smoother than others sample. Therefore 2nd
annealing may improve interface roughness.
3.2 Electrical measurements
The electrical properties of the silicide-contacted shallow junction diodes fabricated by the IIS scheme are dependent on a number of factors, including the dopant activation level, implantation damage recovery, silicide/silicon interface roughness, and the distance between the silicide/silicon interfaces to the junction position. All of these are closely related to the energy and dosage of the dopant ion implantation as well as the dopant activation ability and the drive-in diffusion during the subsequent annealing process; this is especially important for the case of low thermal budget and low energy implantation for the IIS scheme.
3.2.1 I-V measurements
The current transport in metal-semiconductor contacts is mainly due to majority carriers, in contrast to p-n junction, where the minority carriers are responsible. Fig. 3.2 shows four basic transport processes under forward bias.
The four processes are explains as following:
(1) Transport of electrons from the semiconductor over the potential barrier into the metal that the dominate process for Schottky diodes with moderately doped semiconductors such as Si with ND ≤ 1017cm-3 operated at moderate temperatures.
(2) Quantum-mechanical tunneling of electrons through the barrier height.
This is important for heavily doped semiconductors and responsible for
most ohmic contacts.
(3) Recombination in the space-charge region (SCR) that identical to recombination process in a p-n junction.
(4) Hole injection from the metal to the semiconductor that equivalent to recombination in the neutral region [1].
With the SCR width being proportional to ND-1/2, it is obvious that highly doped semiconductors have narrow SCR widths. For metal-semiconductor contacts with narrow SCR widths, electrons can to easy tunnel from the metal to the semiconductor and from the semiconductor to the metal. The conduction mechanisms for a metal to n-type semiconductor are illustrated in Fig. 3.3. For lowly doped semiconductors the current flows as a result of thermionic emission (TE) as show in Fig. 3.3(a) with electrons thermally excited over the barrier. In the intermediate doping range thermionic-field emission (TFE) dominates. The carriers are thermally excited to an energy barrier where the barrier is sufficiently narrow for tunneling to take place.
For high doped densities, the barrier is sufficiently narrow at near the bottom of the conduction band for the electrons the tunneling directly, know as field emission (FE) [2].
Fig. 3.4 shows the forward ID-VD characteristic curves of the NiSi/Si junction diode with 2nd RTA 60 sec by (a) BF2+ implantation and (b) P+ implantation. We observe the activation of P+ implantation is more linear than BF2+ implantation, comparison between (a) and (b). Therefore, the P+ implantation curve presents the ohmic contact the linear curve to pass through 2nd RTA 60 sec. The forward currents rise along with the annealing temperature, nevertheless, after 550 ℃ and 500℃ maximize starts to reduce
along with the temperature rise for BF2+ and P+ implantation. According to the extrapolation: NiSi/Si interface damage is recovered and roughness repaired at 500 ℃~550 ℃. This is assumes that as a result of the formation of dislocation above these temperature. In this temperature, forward bias currents are actually decreases. Some atoms that were already on substitutional site are believed to precipitate on or near these dislocations [3].
Fig. 3-5 shows ID-VD characteristic curves of the NiSi/Si junction diode with 2nd RTA 60 sec by (a) BF2+ implantation and (b) P+ implantation. The ID-VD characteristic curves approximate linear for P+ implantation. We knew schottky contact turns ohmic contact after the annealing process. Fig. 3-6 Forward bias current density versus annealing temperature for the NiSi/Si junction diodes fabricated with (a) BF2+ and (b) P+ implantation at various annealing time. Forward bias current density drops along with the time and the temperature rise. High thermal budget may promote interface state, causes the tunneling current is reduction [4-5].
3.2.2 Reverse leakage current density
Fig. 3-7 shows the reverse bias current density (JR) versus annealing temperature for the NiSi / Si junction diodes with an area of 0.0009 cm2 (300
× 300 µm) measured at a reverse bias of －2 V. The reverse bias current density (JR) is determined by directly dividing the measured current by the diode’s area. Roughness of the silicide/Si interface in a shallow junction may lead to the formation of localized Schottky contacts or the agglomeration-induced local silicide spiking, resulting in the increase of reverse bias current. After annealing at temperature above 550 60 sec℃
with BF2+ implantation, reverse bias currents are actually decrease. We extrapolation the roughness of NiSi/Si interface related to junction leakages.
With temperature rise the roughness of NiSi/Si interface is smoother, there is sufficient thermal budget to recovery defect and without agglomeration occur [6].
3.2.3 Current-Temperature measurement
We can obtain the activation level of M/S junction from current-temperature measurement. Fig. 3.8 and Fig. 3.9 shows the ID-VD characteristic curves of the M/S junction diode with 2nd RTA 60 sec by BF2+ implantation and P+ implantation which measure temperature at 25, 45, 85 and 105℃, respectively. The BF2+ implantation curve presents the schottky contact to pass through 2nd RTA 60 sec at room temperature measured. The schottky contact characteristic conversion to ohmic contact characteristic with measure temperature rise. For RTA 450 and 500℃ samples by BF2+ implantation, are tend to thermionic emission characteristic due to the current of M/S junction is sensitive to temperature. About RTA 550 and 600℃ samples by BF2+ implantation are trend to filed emission
We can obtain the activation level of M/S junction from current-temperature measurement. Fig. 3.8 and Fig. 3.9 shows the ID-VD characteristic curves of the M/S junction diode with 2nd RTA 60 sec by BF2+ implantation and P+ implantation which measure temperature at 25, 45, 85 and 105℃, respectively. The BF2+ implantation curve presents the schottky contact to pass through 2nd RTA 60 sec at room temperature measured. The schottky contact characteristic conversion to ohmic contact characteristic with measure temperature rise. For RTA 450 and 500℃ samples by BF2+ implantation, are tend to thermionic emission characteristic due to the current of M/S junction is sensitive to temperature. About RTA 550 and 600℃ samples by BF2+ implantation are trend to filed emission