Activation energy measurement

The temperature dependence of reverse junction current IR can provide insight into the leakage mechanism. The temperature dependence of reverse current I_R is given by

Where Ea is activation of the junction, k is the Boltzmann constant, and T is the temperature at measurement. The value of Ea can be extracted from the slope of the semilogarithmic plot of log(I_R/T³) versus 1000/T. The value of Ea is close to the bandgap of silicon Eg when the reverse current is dominated by the diffusion current and will be close to Eg /2 when the reverse current is dominated by the generation current [6].

Fig. 4.12 shows the Arrhenius plots for the NiSi/P⁺N and NiSi/N⁺P junction fabricated by BF₂⁺ implantation and P⁺ implantation. The measurement was conducted at 2V reverse bias. Fig. 4.13 shows the activation energy of NiSi/ P⁺N and NiSi/N⁺P junction versus RTA temperature. We can observe E_a is close to E_g at the SPER process is completely (450℃ for N-sub, 500℃ for P-sub samples) among all samples, which the reverse current is dominated by minority carrier diffusion current.

After the SPER is finished, the Ea is reduces with the temperature increase,

and the reverse current is dominated by generation current. Compare Fig. 4.8 and Fig. 4.13, can to explain before extrapolation: because some atoms hold sufficient thermal budget that were already on subsitiutional site are to precipitate induce defects after super-saturation. The defects may be derive from amorphous region where is not entire recrystallized due to low thermal budget or low activation like at 2^nd 450℃-500℃ for P-sub samples.

4.4 References

[1] K. M. Chang, J. H. Lin, C. H. Yang: accepted to the Fifth International Symposium on Control of Semiconductor Interface, (2007).

[2] S. M. Sze, Physics of Semiconductor Devices, 3^rd ed., John Wiley &

Sons, Taipei, (2007)

[3] C. H. Yang, “Research of Dopant Activation at the Interface between Nickel Silicide and Silicon during Nickel Silicide Formation”, NCTU(2007).

[4] C. C. Wang, Y. K. Wu, W. H. Wu and M. C.Chen, Japanese Journal of Applied Physics, Vol. 44, No 1A, 2005, pp. 108-113.

[5]S. Wolf, and R.N. Tauber: “Silicon processing for the VLSI era”, second edition, Lattice press, Vol. 1, Chapter 10, 2000.

[6] B. S. Chen and M. C. Chen, IEEE Trans. Electron Devices 43, 258, (1996).

Chapter 5

Conclusions and Future Work

In this thesis, we have been investigated the activation of B and P implant into silicide (IIS) by RTA process. With the device scale down, the shallow junction would be important because shallow junction formation can effectively suppress short channel effect (SCE). P⁺ implantation samples shows more like ohmic contact behaviors than BF2+ implantation samples about P⁺/P and N⁺/N junction. Based on the IIS dopant segregation pile-up at interface and SPER, our experiment would achieve the high dosage activation and using low temperature annealing, and combine the I-V and C-V measurement to know SPER behavior of IIS method. We could find the best recipes for the device fabrication in the future. After SPER process finished, samples may cause defect formation and dopant deactivation phenomenon with higher thermal budget treatment above 450 and 500℃.

With increasing 2^nd RTA temperatures, the SPER process continuous going, and the Joff currents decreased, but SPER process is completely at 2^nd RTA 450℃ and 500℃ 60s treatment for N-sub and P-sub samples. The point of SPER process is completely to hold the most high on/off ratio among all samples in this study. All in all, we achieved our purposes by means of the experiment and the results were beneficial.

In order to improve the shallow junction properties, we could make some experiments to revise it in the future. We could use Spreading Resistance Profiling (SRP) to check the junction depth and the doping density.

According to the actuality junction depth, we could also know that our fabricated junction does conform to the shallow junction condition or not. In

addition, we could also find the optimum value of annealing temperature. As long as the doping activation density and leakage current can attain our expectation at low annealing temperature, we can replace the high temperature fabrication.

Fig. 1.1 Continuation of Moor’s Law from intel’s high-k/metal gate announcement (2003)

Fig. 1.2 Schematic of issue associated with silicide process.

38

Resistivity

(μΩ-cm)

Silicidation

Temperature

( )℃

Silicon

Consumption

Moving

Species

Film

Stress (dyn/cm2)

1.5×10¹⁰

TiSi2 12-15 800-950 0.9× T Si

CoSi - 375-500 0.91× T Si -

1.2×10¹⁰

CoSi₂. 18 550-900 1.04× T Co

6×10⁹

NiSi 15-16 350-700 0.82× T Ni

NiSi2 35-50 700-850 - Ni -

T stands for thickness of silicide formed

Table 1.1 Compare the characteristics of Ti, Co and Ni silicides.

Fig. 1.3 With/without bridging phenomenon of metal silicides.

40

-Fig. 1.4 Standard deviation of sheet resistance vs silicidation temperature.

P-type / N-type (100) Si sub.

z RCA clean

P-type / N-type (100) Si sub.

SiO₂ 300nm z Thermal Wet Oxidation 300nm

P-type / N-type (100) Si sub.

SiO2 SiO2 z Define active area region (300μm x 300μm)

42

-z Ni film 20nm deposited by E-gun

P-type / N-type (100) Si sub.

SiO2 SiO2

z Silicidation by 1^st RTA (400℃ 30s)

z Selectively etch

(H₂SO₄ : H₂O₂ = 3 : 1 ) 45 sec for unreact Ni

P-type / N-type (100) Si sub.

SiO₂ SiO₂

NiSi

z BF2 / Phosphorous ion implantation

P-type / N-type (100) Si sub.

SiO2 SiO2

NiSi

P-type / N-type (100) Si sub. after coat PR next to remove PR.

(lift-off)

z Activation and junction formation by 2^nd RTA

-SiO₂

Ti Top View

Fig. 2.1 Process flow of P⁺/P, N⁺/N and P⁺/N and N⁺/P junction samples of silicide contact for I-V and C-V electrical properties measurement.

Implanted ion 1st RTA 2nd RTA

P substrate BF₂⁺/20 keV/5E13 cm^-2 P^P+/20 keV/5E13 cm^-2

400℃/60 sec

450 ~ 600℃

60 sec N substrate P^P+/20 keV/5E13 cm^-2

BF2+

/20 keV/5E13 cm^-2

400℃/60 sec

450 ~ 600℃

60 sec

Table 2.1 Process recipe of P⁺/P, N⁺/N and P⁺/N and N⁺/P junction by IIS scheme.

Implanted ion 1st RTA 2nd RTA

P substrate BF₂⁺/28 keV/5E15 cm^-2 400℃/60 sec 450 ~ 600℃

60 sec N substrate P^P+/43 keV/5E15 cm^-2 400℃/60 sec 450 ~ 600℃

60 sec

Table 2.2 Process recipe of P⁺/P, N⁺/N and P⁺/N and N⁺/P junction at backside by IIS scheme.

46

-(a) (b)

(c) (d)

Fig. 3.1 AFM image shows NiSi/Si interface morphology by 2^nd RTP annealing (a) 400 (b) 500 (c) 600 (d) 700 for 30 sec.℃ ℃ ℃ ℃

Fig. 3.2 Four basic transport process under forward bias.

Fig. 3.3 Depletion-type contacts to n-type substrates with increasing doping concentrations. The electron flow is schematically indicated by the electrons and their arrows.

48

-0 1 2

Fig. 3.4 The forward ID-V_D characteristic curves of the M/S junction diode with 2^nd RTA 30 sec by (a) BF₂⁺ implantation and (b) P⁺ implantation.

-2 -1 0 1 2

Fig. 3.5 The I_D-V_D characteristic curves of the M/S junction diode with 2^nd RTA 60 sec by (a) BF2+ implantation and (b) P⁺ implantation.

50

-450 500 550 600 0.1

1 10 100

Forward Current Density (A/cm2 )

Temperature (^oC)

RTA 60 sec RTA 120 sec IF at -1V

(a)

450 500 550 600

0.1 1 10 100

Forward Current Density (A/cm2 )

Temperature (^oC)

RTA 60 sec RTA 120 sec IF at 1V

(b)

Fig. 3.6 The forward bias current density versus annealing temperature for the NiSi / Si junction diodes fabricated with (a) BF₂⁺ and (b) P⁺ implantation at various annealing time.

450 500 550 600

Fig. 3.7 The reverse bias current density versus annealing temperature for the NiSi / Si junction diodes fabricated with (a) BF₂⁺ and (b) P⁺ implantation at various annealing time.

52

--2 -1 0 1 2

Fig. 3.8 The ID-V_D characteristic curves of the M/S junction diode with 2^nd RTA 60 sec by BF₂⁺ implantation and measure temperature at 25, 45, 85 and 105℃, respectively.

-2 -1 0 1 2

Fig. 3.9 The ID-V_D characteristic curves of the M/S junction diode with 2^nd RTA 60 sec by P⁺ implantation and measure temperature at 25, 45, 85 and 105℃, respectively.

54

--2 -1 0 1 2 0

500 1000 1500

Capacitance (pF)

V_D (Volts)

w/o 2nd RTA

-2 -1 0 1 2

0 50 100 150 200 250

Capacitance (pF)

V_D (Volts) w/o 2nd RTA

Fig. 3.10 The capacitance-voltage characteristics of Schottky junction diodes implanted (a) BF₂⁺ and (b) P⁺ without 2^nd RTA.

Fig. 4.1 Abrupt p-n junction in thermal equilibrium. (a) Space-charge distribution. Dashed lines indicate corrections to depletion approximation.

(b) Electric-field distribution. (c)Potential distribution where Vbi(Ψ_bi) is the built-in potential. (d) energy-band diagram.

56

--2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 Slope α 1/Ν

Voltage (volt) 1/C2

V_intercept=ψ_bi-2kT/q

Fig.4.2 A 1/C²-V plot can yield the built-in potential and doping density.

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0

2.0x10¹⁵ 4.0x10¹⁵ 6.0x10¹⁵ 8.0x10¹⁵ 1.0x10¹⁶

1/C2 (cm4 /F2 )

V_R (Volt) Measure Data Linear Fit of Data

Fig.4.3 Actually measure 1/C²-V plot.

450 500 550 600 0.7

0.8 0.9

Vbi (volt)

Temperature (oC) RTA 60s

(a)

450 500 550 600

0.7 0.8 0.9 1.0 1.1

Vbi (Volt)

Temperature (oC)

RTA 60s

(b)

Fig.4.4 Ψbi (a)N-sub samples (b)P-sub samples.

58

-450 500 550 600

Fig.4.5 The dopant activation density of IIS at MS interface (a)Boron doping density for N-sub samples (b)Phosphorous doping density for P-sub samples.

Dopant distribution

N i S i

S u b .

(a) Junction

interface

N i S i

S u b .

(b)

(c)

N i S i

S u b .

Fig. 4.6 Illustration of the dopant activation. The P/N junction interface becomes deeper away from M/S interface with 2^nd RTA temperature.

60

-450 500 550 600 1.0

1.2 1.4 1.6 1.8 2.0

ideal factor

Temperature(^oC) RTA 60s

(a)

450 500 550 600

1.0 1.2 1.4 1.6 1.8 2.0

RTA 60s

ideal factor

Temperature(^oC)

(b)

Fig. 4.7 ideality factor (a)N-sub samples (b)P-sub samples.

400 450 500 550 600 650

Fig. 4.8 Ion - I_off relation graphics (a)N-sub samples (b)P-sub samples (I_on: Forward bias at 1V and I_off: Reverse bias at 2V).

62

-450 500 550 600

Fig. 4.9 The reverse current density curves of the P/N junction diode with 2^nd RTA 60 sec by (a) BF₂⁺ implantation (b) P⁺ implantation.

0.0 0.5 1.0 1.5 2.0

Fig. 4.10 Compare to the forward current density curves of the P/N junction diode with 2^nd RTA 60 sec by BF₂⁺ implantation (a) 20keV/5E13cm^-2 (b) 50keV/5E15cm^-2

64

--2.0 -1.5 -1.0 -0.5 0.0

Fig. 4.11 Compare to the forward current density curves of the P/N junction diode with 2^nd RTA 60 sec by P⁺ implantation (a) 20keV/5E13cm^-2 (b) 30keV/5E15cm^-2

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4

Fig. 4.12 Arrhenius plot for NiSi/Si interface (a) P⁺/N junction fabricated by BF₂⁺ implantation. (b) N⁺/P junction fabricated by P⁺ implantation.

The measurement was conducted at 2V reverse bias.

66

-450 500 550 600

Fig. 4.13 The activation energy of NiSi/Si interface (a) P⁺/N junction fabricated by BF₂⁺ implantation. (b) N⁺/P junction fabricated by P⁺ implantation.

在文檔中 以離子植入矽化物技術製作在矽化鎳與矽介面處低溫摻雜活化的相關研究 (頁 47-80)