C-V measurement introduction - Electrical Characteristics of NiSi/n + p, NiSi/p + n ultra

Chapter 4 Electrical Characteristics of NiSi/n + p, NiSi/p + n ultra

4.1.1 C-V measurement introduction

The effective dopant activation estimated that silicide dopant segregation and pile-up at interface by capacitance-voltage (C-V) measurement. The measured capacitance was made up through three different capacitances in series, contain silicide/silicon junction capacitance, P-N junction depletion capacitance and backside contact capacitance. In silicide/silicon junction capacitance part, base on chapter three we can know where more likely to ohmic contact behavior. Consequently, we think that have high dopant concentration in silicide/silicon interface result in large capacitance. Let us can neglect the silicide/silicon capacitance in our analysis. About backside contact capacitance part, because of the area of contact is occupy wafer size which is larger than P-N junction area, therefore we also neglect backside contact capacitance term in our analysis [1]. As a result, the mainly measured capacitance was depletion capacitance and the model was shows in Fig. 4.1. The depletion-layer capacitance per unit area is defined as Cj = dQ/dV, where Qis the incremental depletion charge on each side of the junction upon an incremental charge of the applied voltage dV [1]. For

one-side abrupt junctions, the capacitance per unit area is given by:

where V is positive/negative for forward/reverse bias. Rearrange the above Eq.(1):

It is clear from Eq.(2) that by plotting 1/C² versus V, a straight line should result from a one-sided abrupt junction as shows in Fig. 4.2. The slope gives the impurity concentration of the substrate (NB), and 1/C =0 gives (Ψ

bi-2kT/q). Rearrange the above Eq.(2), we can obtain impurity concentration at depletion layer edge.

)]

Rearrange the above Eq.(4) which we can obtain the interface doping density can be estimate as following [2]:

4.1.2 Result and Discussion of C-V

The substrate doping density can be obtained from the different C-V data.

We used Eq.(3) to plot the relationship between depletion capacitance and reverse bias voltage as shows in Fig. 4.3, and the building voltage of N⁺/P and P⁺/N junction can be obtained from 1/C²-V curve where 1/C²=0 as shows in Fig. 4.4. From linearly 1/C²-V curve implies that the linear abruptness junction is obtained. The results combined Eq.(3), Eq.(5) and Eq.(6) to estimate the doping density of N⁺/P and P⁺/N interface from average substrate doping density and building voltage as shows in Fig. 4.5 [3]. About above the results, at temperature above 500℃, doping density and building voltage of N⁺/P and P⁺/N interface are decrease with the temperature rise. The results were not conformed to us expect. Because the C-V measurement was measure the N⁺/P and P⁺/N junction interface, therefore, the junction interface went away from M/S junction interface with the annealing temperature increase as shows in Fig. 4.6. Moreover, the doping concentration was started to activation from the pile-up interface of MS junction. The measured result would exhibit the junction interface characteristic so that the higher temperature annealing showed the lower doping density.

4.2 I-V Measurement

4.2.1 I-V Measurement Introduction

For analyze the junction forming behavior, I-V measurement are adapted.

The measuring sweep voltage was from forward bias to reverse bias for N-sub and P-sub samples. From the I-V curve, we could estimate the ideal factor by:

Rearrange the above Eq.(7):

⎥⎥

Where η is called the ideality factor. The value of η is close to 1, when the forward current is dominated by diffusion current and is close to 2 when forward current is dominated by depletion recombination current. When both the diffusion current and recombination current are similar, the η is between 1 and 2.

4.2.2 Result and Discussion of I-V

The ideality factor can be determined from the slope of the linear segment of the I-V curve plotted on semilogarithmic coordinates [4]. The current range took to between 0.4 and 0.04 for N-sub samples which were between -0.4 and -0.04 for P-sub samples. The ideality factor of N⁺/P and P⁺N junction are exhibited in Fig. 4.7. The ideal factor would be affected by below factors: (1) contact resistance (2)generation-recombination current (3) substrate series resistance (4) high level injection. For the contact resistance, because high activation in junction, the MS interface would conversion from schottky contact to ohmic contact. For series resistance, cross to IR voltage bias of neutral region usually is smaller than KT/q so that can neglect this factor. And take current range does not the high level injection region so this does not dominate reason. We extrapolate the dominated factor might be due to defect induce generation-recombination current.

The on-off ratio as Jon (at VF = 1V) and Joff (at VR = 2V) of N⁺/P and P⁺N diode are exhibited in Fig. 4.8. The reverse bias current is the minimum at 2^nd RTA 450℃ 60s and 500℃ 60s treatment for N-sub and P-sub samples.

Because exist defects in NiSi/Si interface result in higher reverse bias current. The defects may be derive from NiSi/Si interface (amorphous region) where is not entire recrystallized due to low thermal budget or low activation like at 2^nd 450℃ for P-sub samples. With increasing 2^nd RTA temperatures, the SPER process continuous going, and the Joff currents decreased, but SPER process is completely at 2^nd RTA 450℃ and 500℃ 60s treatment for N-sub and P-sub samples. The point of SPER process is completely to hold the most high on/off ratio. Although, the forward bias current is not mainly

factor for on/off ratio, but can be observed by the relative ideality factor which has the minimum ideality factor due to the forward bias is dominated by the diffusion current. After SPER is finished, with increasing 2^nd RTA temperature, the reverse bias current will be reduces. The defect induce this results, due to SPER would be activation to a level above the equilibrium solid solubility during crystalline regrowth. While provide more thermal budget would be some atoms that were already on substitutional site are believed to precipitate on or near these dislocations after super-saturation.

Another may be reason, dislocations start to form at the temperature range from 500 to 600℃ [5], itself or by some defect induced dopant deactivation at the P⁺/N and N⁺/P interface. The reverse bias current is mainly factor to affect on/off ratio at RTA temperature 550℃ to 600℃ for BF2+ implantation, as show in Fig. 4.8(a). We extrapolation the defects start to dissolve in EOR regime at RTA temperature 600℃, result in the reverse bias current to drop.

Another possible reason, because the behavior of junction is trend to Schottky-like region with doping layer width decrease under the fixed dopant concentration. Therefore, the reverse bias current will reduce due to the behavior is trend to PN-like at RTA temperature 600℃.

The current of PN junction was determined by minority carrier diffusion.

However, the current of Schottky barrier diode was determined by thermionic majority carrier overcome potential barrier. The typical of generation current density of silicon PN junction is approximately 10^-7 A/cm², nevertheless, this is less than that of 2-3 order for the reverse current density of Schottky barrier diode, as shows as Fig. 4.9. In addition, threshold voltage of Schottky barrier diode is less than that of PN junction, as shows as Fig. 4.10 and Fig. 4.11. We clearly to know have Schottky barrier diode

characteristic with low energy and dose of ion implantation, due to high energy and dose of ion implantation to cause amorphous silicon region to deepen.

4.3 Activation Energy Measurement

The temperature dependence of reverse junction current IR can provide insight into the leakage mechanism. The temperature dependence of reverse current I_R is given by

Where Ea is activation of the junction, k is the Boltzmann constant, and T is the temperature at measurement. The value of Ea can be extracted from the slope of the semilogarithmic plot of log(I_R/T³) versus 1000/T. The value of Ea is close to the bandgap of silicon Eg when the reverse current is dominated by the diffusion current and will be close to Eg /2 when the reverse current is dominated by the generation current [6].

Fig. 4.12 shows the Arrhenius plots for the NiSi/P⁺N and NiSi/N⁺P junction fabricated by BF₂⁺ implantation and P⁺ implantation. The measurement was conducted at 2V reverse bias. Fig. 4.13 shows the activation energy of NiSi/ P⁺N and NiSi/N⁺P junction versus RTA temperature. We can observe E_a is close to E_g at the SPER process is completely (450℃ for N-sub, 500℃ for P-sub samples) among all samples, which the reverse current is dominated by minority carrier diffusion current.

After the SPER is finished, the Ea is reduces with the temperature increase,

and the reverse current is dominated by generation current. Compare Fig. 4.8 and Fig. 4.13, can to explain before extrapolation: because some atoms hold sufficient thermal budget that were already on subsitiutional site are to precipitate induce defects after super-saturation. The defects may be derive from amorphous region where is not entire recrystallized due to low thermal budget or low activation like at 2^nd 450℃-500℃ for P-sub samples.

4.4 References

[1] K. M. Chang, J. H. Lin, C. H. Yang: accepted to the Fifth International Symposium on Control of Semiconductor Interface, (2007).

[2] S. M. Sze, Physics of Semiconductor Devices, 3^rd ed., John Wiley &

Sons, Taipei, (2007)

[3] C. H. Yang, “Research of Dopant Activation at the Interface between Nickel Silicide and Silicon during Nickel Silicide Formation”, NCTU(2007).

[4] C. C. Wang, Y. K. Wu, W. H. Wu and M. C.Chen, Japanese Journal of Applied Physics, Vol. 44, No 1A, 2005, pp. 108-113.

[5]S. Wolf, and R.N. Tauber: “Silicon processing for the VLSI era”, second edition, Lattice press, Vol. 1, Chapter 10, 2000.

[6] B. S. Chen and M. C. Chen, IEEE Trans. Electron Devices 43, 258, (1996).

Chapter 5 Conclusions and Future Work

In this thesis, we have been investigated the activation of B and P implant into silicide (IIS) by RTA process. With the device scale down, the shallow junction would be important because shallow junction formation can effectively suppress short channel effect (SCE). P⁺ implantation samples shows more like ohmic contact behaviors than BF2+ implantation samples about P⁺/P and N⁺/N junction. Based on the IIS dopant segregation pile-up at interface and SPER, our experiment would achieve the high dosage activation and using low temperature annealing, and combine the I-V and C-V measurement to know SPER behavior of IIS method. We could find the best recipes for the device fabrication in the future. After SPER process finished, samples may cause defect formation and dopant deactivation phenomenon with higher thermal budget treatment above 450 and 500℃.

With increasing 2^nd RTA temperatures, the SPER process continuous going, and the Joff currents decreased, but SPER process is completely at 2^nd RTA 450℃ and 500℃ 60s treatment for N-sub and P-sub samples. The point of SPER process is completely to hold the most high on/off ratio among all samples in this study. All in all, we achieved our purposes by means of the experiment and the results were beneficial.

In order to improve the shallow junction properties, we could make some experiments to revise it in the future. We could use Spreading Resistance Profiling (SRP) to check the junction depth and the doping density.

According to the actuality junction depth, we could also know that our fabricated junction does conform to the shallow junction condition or not. In

addition, we could also find the optimum value of annealing temperature. As long as the doping activation density and leakage current can attain our expectation at low annealing temperature, we can replace the high temperature fabrication.

Fig. 1.1 Continuation of Moor’s Law from intel’s high-k/metal gate announcement (2003)

Fig. 1.2 Schematic of issue associated with silicide process.

Resistivity

(μΩ-cm)

Silicidation

Temperature

( )℃

Silicon

Consumption

Moving

Species

Film

Stress (dyn/cm2)

1.5×10¹⁰

TiSi2 12-15 800-950 0.9× T Si

CoSi - 375-500 0.91× T Si -

1.2×10¹⁰

CoSi₂. 18 550-900 1.04× T Co

6×10⁹

NiSi 15-16 350-700 0.82× T Ni

NiSi2 35-50 700-850 - Ni -

T stands for thickness of silicide formed

Table 1.1 Compare the characteristics of Ti, Co and Ni silicides.

Fig. 1.3 With/without bridging phenomenon of metal silicides.

-Fig. 1.4 Standard deviation of sheet resistance vs silicidation temperature.