Motivation

The only stored charges at the nanocrystals adjacent to the defect leak through the tunneling dielectric, compared to huge charge loss of conventional Flash memory due to the lateral charge transport. This signifies that the NC memory has the ability to alleviate the scaling limitations of conventional Flash memory as well as extended the retention time.[32] Various materials have been used to form NCs, such as silicon [33, 34], germanium (Ge) [35] and metal [36], as the charge storage layer for nonvolatile memories.

In this thesis, we proposed a novel sol-gel spin coating method to fabricate high-κ material combined thin film, and annealing for driving the sol-gel film transformed into NCs. The sol-gel solution provided colloidal solvents or precursor compounds when metal halides were hydrolyzed under controlled conditions in a beaker. In the sol-gel reaction, hydrolysis, condensation, and polymerization steps occurred to form metal-oxide networks in the colloid liquid. The most interesting feature of sol-gel processing in the solution was its ability to synthesize new types of materials that were known as “inorganic-organic hybrids.”[24] The film formation with sol-gel spin coating method was a simpler than ALD, PVD, or CVD technologies due to its cheaper precursors and tools. In addition, the film can be fabricated in the normal pressure environment instead of high vacuum system.

The crystallization of transferring the charge trapping thin film into the NC phase during thermal annealing was dependent on the composition of sol-gel solution, preparation solvent, and annealing temperature. The formation of coexisting hafnium silicate and zirconium silicate NC memory had been previously published.[37, 38]

However, the effect of annealing temperature that controlled the formation of NC, degree of crystallization, interfacial energy, and charge retention in the sol-gel derived

memory was still unclear. The formation mechanism to explain the growth of nanocrystal was also still unclear. In the thesis, we had clarified the questionable point with physical and electrical characteristics studies.

Finally, we utilized the best NC formation condition to prepare charge trapping layer for a memory device. We expected the sol-gel derived nanocrystal memory devices with superior electrical characteristics in terms of large memory windows, high write/erase speed, long retention time, good disturbs, and excellent endurance performance.

Chapter 2

Nanocrystal Memory Device principles and operations

2.1 Fundamentals of the NC memory

Nonvolatile memory devices based on the charge storage in discrete charge traps such as semiconductor and metal nanocrystals (NCs) have recently attracted much attention in view of their potential application for high-density nonvolatile memory (NVM) devices.[39] The use of discrete charge-trap of nanocrystals offers an advantage of preventing lateral charge movement, thereby enhances the data retention characteristic.[40] The nonvolatile metal nanocrystal memory devices were extensively investigated over semiconductor nanocrystals because of several advantages, such as stronger coupling with the conduction channel, higher density of states (transport perspectives) than semiconductor (i.e., better charge storage), and a
wide range of available work functions (faster programming speed and better data
retention).[6]

2.2 NC Memory characteristics

2.2.1 Basic program/erase principle

The basic principle of programming the memory is that electrons or holes inject into the charge trapping layer and hence cause the threshold voltage shift. Figure 2.1(a)

shows the cross-section scheme of the nanocrystal memory device. The electrons/holes from channel are injected through tunneling oxide due to the horizontal field of controlling gate to Si-substrate, and therefore trapped into the nanocrystall. Two major mechanisms has been proposed to explain the program of the flash memory, that is, Fowler-Nordheim (FN) tunneling and channel hot-electron injection (CHEI). The energy bands of the nanocrystal memory device at program and erase are illustrated in Figure 2.1(b) and 2.1(c), respectively. During the program process, a positive gate voltage is applied to inject channel inversion-layered electrons into the nanocrystals. During the erase process, a negative gate bias is applied to cause the accumulation layered holes to inject into the nanocrystal and recombine with the trapped electrons..[8] The program and erase process result in the shifting of the threshold voltage, which is proportional to the quantities of trapped charges.

Program

The CHEI mechanism is generally used in flash memories, where a lateral electric field (from drain to source) “heats” the electrons and a transversal electric field (from controlling gate to channel) injects the hot carriers through the oxide. The physical mechanism of CHEI is relatively simple depicted in Fig 2.3. An electron traveling from the source to the drain gains energy from the lateral electric field and loses energy to the lattice vibrations (acoustic and optical phonons).[41] At large drain bias, the minority carriers that flow in the channel are heated by the large electric fields occurred at the drain side of the channel and their energy distribution is shifted higher. For fields exceeding this value, electrons are no longer in equilibrium with the lattice, and their energy relative to the conduction band edge begins to

conduction band edges. For an electron to overcome this potential barrier, three conditions must hold.[42]

(1) Its kinetic energy has to be higher than the potential barrier.

(2) It must be directed toward the barrier.

(3) The field in the oxide should be collecting it.

Erase

Charge-trapping memory is erased by band-to-band tunneling hot hole (BBHH) injection, under which condition the drain is positively biased and the gate negatively biased. Due to the hot hole injection mechanism, BBHH injection has the advantage of a lower voltage bias and a faster erasing speed than the FN tunneling.[42]

During the erase operation, holes are injected from the p-type substrate into the charge trapping layer valence band. These holes “trap” at the top oxide interface because of the large barrier height. Electrons may tunnel from an n⁺ gate into charge trapping layer and combine with the injected holes. Band-to-band tunneling process that occurs in the deeply depleted n⁺ surface region under gate-to-drain overlap area is another method used to erase the SONOS memory device. This mechanism is to simultaneously apply a negative voltage to the gate and a positive voltage to the drain.

Then the hot holes are injected through the bottom oxide and recombine with the stored electrons. Figure 2.4 illustrates the hot holes injection generated by band-to-band tunneling process.

2.2.2 Basic reliability principle 2.2.2.1 Retention

As in any nonvolatile memory technology, Flash memories are specified to retain

layer must be as minimal as possible.[3] Possible causes of charge loss are: (1) defects in the tunnel oxide; (2) defects in the interpoly dielectric; (3) mobile ion contamination; and (4) detrapping of charge from insulating layers surrounding the charge-trapping layer. During the retention mode, the electrons inside the nanocrystal can not be stored in the conduction band for several reasons.[43] The generation of defects in the tunnel oxide can be divided into an extrinsic and an intrinsic one. The former is due to defects in the device structure; the latter to the physical mechanisms that are used to program and erase the cell. The electrons can subsequently detrap with time, especially at high temperature. The charge variation results in a variation of the charge-trapping layer potential and thus in cell decrease, even if no leakage has actually occurred. This apparent charge loss disappears if the process ends with a thermal treatment able to remove the trapped charge.

The retention capability of flash memories has to be checked by using accelerated tests that usually adopt screening electric fields and hostile environments at high temperature.

2.2.2.2 Endurance

Cycling is known to cause a fairly uniform wear-out of cell performance, which eventually limits Flash memory endurance.[44] As the experiment was performed applying constant pulses, the variations of program and erase threshold voltage levels are described as “program/erase threshold voltage window closure” and give a measure of the tunnel oxide aging. In particular, the reduction of the programmed threshold with cycling is due to trap generation in the oxide and to interface state generation at the drain side of the channel, which are mechanisms specific to

The initial lowering of the erase is due to a pile-up of positive charge which enhances tunneling efficiency, while the long-term increase of the erase is due to a generation of negative traps. A typical result of an endurance test on a single cell is illustrated in Figure 2.5.

2.2.2.3 Disturbance

The first failure phenomenon, “program disturbance,” often takes place under the electrical stress applied to those neighboring un-programmed cells during programming a specific cell in the array. Two types of program disturbances, gate (word-line, or WL) disturbance and drain (bit-line, or BL) disturbance need be considered.[3] In Figure 2.6, shows the schematic circuitry of the memory array.

During programming cell A, gate disturbance occurs in the cell B and same for those cells connected with the same word-line because the gate stress is applied to the same word-line. During programming cell A, drain disturbance occurs in the cell C and same for those cells connected with the same bit-line because the drain stress is applied to the same bit-line. For the cell reading, the unwanted electron injection would happen while the word-line voltage and bit-line voltage are under read operation. This phenomenon would result in a significant threshold voltage shift of our selected reading cell. This is call read disturbance.

Figure 2.1 (a) Schematic cross-section of nanocrystal memory device structure; (b) illustration of write process: inversion- layer electron tunnels into the nanocrystal; (c) illustration of erase process: accumulation layer hole tunnels into the nanocrystal, electron in nanocrystal can tunnel back to the channel.

(a)

(b)

(c)

Figure 2.2 Id–Vg curves of an FG device when there is no charge stored in the FG (neutral) and when a negative charge is stored in the FG (charged).

V _G I _D

V_G

V_D VS

NEUTRAL

“1”

VG

V_D V_S

CHARGED

“0”

V

△V

V

Figure 2.3 The procedure of hot electrons injection.

Figure 2.4 The hot holes injection generated by band-to-band tunneling.

B B

Figure 2.5 Threshold voltage window closure as a function of program/erase cycles on a single cell.

Figure 2.6 The schematic illustrates the disturb condition. Cell A is the programming cell. Cell B and Cell C perform the gate disturb and drain disturb, respectively.

Chapter 3

Nanocrystallization and interfacial tension of charge trapping layer

3.1 Introduction

In the recent years, the emphasis of material design has dramatically changed towards a general understanding and control of the fundamental connections between the chemistry on a molecular level and material properties on the macroscopic scale.

Looking towards the 21^st century, advances in information processing, communication (microelectronics), medicine etc. require miniaturized materials with superior properties and performance. “Nanotechnology”, which is essentially material science on a nanometer scale, is a subject that combines the efforts of scientists in interdisciplinary research (physicists, chemists and material scientists).

According to the International Technology Roadmap for Semiconductors, there are critical limitations for aggressively scaling the conventional nonvolatile floating-gate memories below sub-70-nm node. For conventional SONOS, erase saturation and vertical stored charge migration[45] are the major drawbacks; while for nanocrystal memories good enough charge keeping capability of the discrete storage nodes and the formation of nanocrystals with constant size, high density and

memories and nanocrystal memories have recently attracted much attention for the application in the next-generation nonvolatile memories[35, 47, 48] because of their great potential for achieving high program/erase (P/E) speed, low programming voltage and low power performance.

The conventional floating gate (FG) nonvolatile memory (NVM)[39, 49] suffers
from a charge loss problem as the feature size of the device continues to shrink.[50] A discrete nanocrystal (NC) memory was then proposed as a replacement of the conventional FG memory. The NC memory is expected efficiently to preserve the trapped charge due to the discrete charge storage node, while also demonstrate excellent features such as fast program/erase speeds, low programming potentials, and high endurance. We have proposed a sol-gel spin-coating method to fabricate the charge trapping film that can be fabricated in a normal atmospheric pressure instead of high-vacuum system. Many methods to fabricate nanocrystals (NCs) have been widely investigated recently such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and ion beam synthesis. In addition to these deposition methods, a NC formation process by using sol–gel spin-coating method has been reported by our group.[38] Compare to others, the benefit of sol–gel spin-coating method is relatively cheap, simple, and can be fabricated in a normal atmospheric pressure instead of high-vacuum system. In addition, the ability to synthesize new type of materials that are known as “inorganic–organic hybrids” will induce various application of the sol–gel processing.

Sol-gel process contains fractal geometry and percolation theory in physics, hydrolysis and poly-condensation mechanism in chemistry, sintering and structural relaxation in ceramics, and so on. When sol is prepared with starting materials of molecular unit, a solid fractal network is obtained through hydrolysis and

removing inhomogeneity in materials through the control of chemical reaction concerning with inorganic polymerization.[51] Transition metal oxides are widely used in many important technological applications such as solar energy conversion, catalysis, magnetic recording, sensors, and ceramics. Yet compared to the intensive study of nanocrystals of semiconductors and metals, relatively little work has been done on the metal oxides.[24, 52]

The crystallization of transferring the charge trapping thin film into the NC phase during thermal annealing is dependent on the sol-gel composition, preparation solvent, and annealing temperature. The formation of coexisting hafnium silicate and zirconium silicate NC memory has been previously published.[37] In general, the NC formation is related to the solid phase segregation induced seeding effect.[53]

However, the effect of annealing temperature that controls the formation of NC, degree of crystallization, interfacial energy, and charge retention in the sol-gel derived memory is still unclear.

3.2 Experimental

3.2.1 Formation of sol-gel derived thin film/nanocrystals

Prior to various annealing treatments, the sol-gel thin film was deposited by the spin-coating method from the precursors of zirconium tetrachloride, hafnium tetrachloride, and silicon tetrachloride. The sol-gel solution was prepared as the experiment procedure flow which was shown in Figure 3.1. The solution were synthesized by the sol-gel method using the precursors of the analytical reagent graded zirconium tetrachloride (ZrCl4, 99.5%, Aldrich, USA), hafnium tetrachloride (HfCl ,99.5%, Aldrich, USA), and silicon tetrachloride (SiCl , 99.5%, Aldrich, USA).

hydrochloric acid serving as the catalyst was added into the solution for hydrolysis and condensation. Then, we mixed ZrCl4, HfCl4, and SiCl4 solutions together for preparing the sol-gel solution for following experiment. The concentration of molar ratio for ZrCl4, HfCl4, SiCl4, and ethanol in the sol-gel solution was 1:1:1:1000. The mixed solution was stirred for 0.5 hr at room temperature. After well mixed, we spin coated the sol-gel solution on the silicon substrates at rotation speed of 3000 rpm for 60 sec at room temperature by using a Tokyo Electron Limited (TEL) system (Clean Track Model-MK8). Afterwards, these samples were subjected to rapid thermal annealing (RTA) treatment at various temperatures for 60 sec under an O2 ambient.

Finally, the samples were subjected to XPS, TEM, AFM, and interfacial energy analyses.

3.2.2 Memory device fabrication

The fabrication of sol-gel spin-coating NC memory was started with local oxidation of Si process on a p-type (100) silicon substrate. A 10 nm tunneling oxide film was thermally grown at 925 °C in a furnace. The sol-gel film was then formed through sol-gel spin coating and RTA process mentioned above. The 20 nm blocking oxide was deposited by plasma enhanced chemical-vapor deposition (PECVD) tetraethylorthosilicate (TEOS). Followed by a 200-nm-thick amorphous Si gate was deposited. Finally, gate pattering, source/drain (S/D) implanting, and the rest of the subsequent metal-oxide-semiconductor (MOS) processes were used to fabricate the NC-NVM devices.

3.3 Results and discussion

3.3.1 RTA temperature effect of sol-gel film transformation

The high resolution structural characterization of the NCs was carried out by the high-resolution transmission electron microscopy (HRTEM, JEOL2100F) operated at 300 kV. The cross-sectional TEM images of the sol-gel derived thin films samples that annealed at 400, 600, and 900 °C were illustrated in Figure 3.2. The sample in Figure 3.2(a) by 400 °C RTA treatment exhibited a continuous and smooth film. This observation suggested the annealing temperature at 400 °C has no effect on the film’s morphology. As to the sample annealing at 600 °C, Figure 3.2(b) revealed the morphology of thin film was discontinuous and uneven. If the annealing temperature was elevated to 900 °C, the film illustrated in Figure 3.2(c) was complete transferred into isolated NCs. Each crystal size of the TEM image was estimated to be 6–10 nm.

Literature had proposed the spinodal decomposition effect[31] to explain the annealing effect for formation of zirconium silicate. We inferred that the darker NCs in Figure 3.2(c) were formed from the high–molecular–weight hafnium silicate, and the bright NCs were from the low–molecular–weight zirconium silicate.[37] Figure 3.3 shows the elemental composition of the binary metal oxides NCs which were estimated by energy dispersive X-ray spectroscopy (EDS).

The nature of the chemical bonding for the transformation of thin film into NC was characterized by using x-ray photoelectron spectroscopy (XPS) analysis. Figure 3.4 provided a comparison of the XPS results for (a) Si 2p, (b) Zr 3d, (c) Hf 4f, and
(d) O 1s bonding for samples annealed at different temperatures. Figure 3.4(a) showed the increasing of binding energy of Si 2p from 100.40 eV (400 °C RTA) to 100.95 eV (900 °C RTA) with various annealing temperature. This observation related to the

and Hf 4f shown in Figs. 3.4(b) and (c) exhibited the shifting to the higher energies upon increasing the annealing temperature. This observation suggested that the oxygen atoms of Zr–O and Hf–O bonds reacted with their nearby Si atoms, forming hafnium and zirconium silicate.[54] As to the O 1s spectra in Figure 3.4(d), each peak can be deconvoluted into two peaks, i.e., the higher and lower energy peaks, which were respectively attributed to the SiO2 and metal-rich silicate.[6] If the annealing temperature was increased, the intensity ratio of lower energy peak to higher energy peak was increased. This result indicated the hafnium and zirconium silicates were toward the bonding of metal-rich silicate. This finding was also consistent with the observation of Hf 4f and Zr 3d spectra.

3.3.2 Interfacial tension analysis

Figure 3.5 showed the interfacial tension (interfacial energy per unit area) of the hafnium and zirconium silicates as a function of annealing temperature. The surface free energy was evaluated using van Oss and Good’s three-liquid acid-base method.

According to this approach (refer to equation (1)), the surface free energy of a solid, γ^s, can be calculated from a combination of three factors:

(1)

Where γ^LW is the Liftshitz/van der Waals component, γsAB is the acid-base component, γ⁺ is the Lewis acid component, and γ^－ is the Lewis base component. Values of γsLW, γs+, and γs^－ can be calculated from equation (2) after measuring the liquid-solid contact angles (θ) of these three characterizing liquids.

In equation (2), γL is the surface tension of the liquid, and subscripts S and L refer to solid and liquid, respectively. Diiodomethane was selected as the apolar liquid, and water and ethylene glycol were selected as the polar liquid pair. The surface

of the thin films follow similar trends to those observed for the advancing contact angles.

(2)

As Figure 3.5 depicted, the interfacial energy of sol-gel spin coated film that abruptly increases from 400 °C to 600 °C annealing, and then slightly decreases from 600 °C to 1050 °C. The advancing contact angle of the polymer surface was measured by using Krüss GH-100 goniometer with deionized water, ethylene glycol, and diiodomethane as the standard solution to measure the surface free energy of the sol-gel film. The sol-gel thin film is thermodynamically not stable due to their high surface energy, therefore it nucleate whereby it is stabilized with the surface energy decrease.

As Figure 3.2 (a) mentioned, the surface at 400 °C RTA is still smooth and

As Figure 3.2 (a) mentioned, the surface at 400 °C RTA is still smooth and