Chapter 4: Phase separation of charge trapping layer
4.3.2 Phase separation mechanism of sol-gel thin film
The mechanism responsible for the formation of NCs was well known to be the transformation of crystalline silicate into spinodal decomposition through high temperature RTA treatment.[62] Stemmer and coworkers[31] proposed the metastable phase diagram for the zirconium silicate and hafnium silicate. They concluded the film approached the driving force for a thermodynamically metastable state of the spinodal decomposition under annealing temperature at 900 °C, showed in Figure 4.3.
Therefore, we depicted a pathway in Figure 4.4 for explaining the thickness phenomenon of spinodal decomposition on sol-gel thin film. As to the thinner film, a series of phase separation steps depicted in Figure 4.4(a). The first step showed initial stage of sol-gel deposited film before annealing. The second step illustrated the film was continuous and smooth, and retained the similar morphology under low temperature annealing (400 °C). Upon 600 °C annealing in step 3, the film started to perturb, and became not only discontinuous but uneven. Finally, at 900 °C annealing, the film approached the driving force for a metastable state of the spinodal decomposition region in the phase diagram.[31] The phase transformed by spinodal decomposition induced the completely isolated NCs. Figure 4.4(b) illustrated different preparation solvent of IPA derived phase separation mechanism. On the contrary, the morphology in the thicker film became more three-dimensional and interconnected at 900 °C annealing. We presumed that the solvent property played an important role on deciding the sol-gel film thickness due to the dispersion condition and the viscosity.
The spin coating film thickness effected the film transformation into interconnected or discrete NCs.
memory devices. The electrical characteristics of the samples were performed by HP4156 to observe I-V characteristics. The normalized Vth shift in percentage was defined as the ratio of Vth shift at the time of interest and at the beginning (t=1 sec).
For ethanol system sample at 25 °C measurement, the retention times showed in Figure 4.5(a) was extrapolated up to 106 sec with less than 5% charge loss. At 85 °C measurement, the retention times to 106 sec demonstrated less than 10% charge loss.
Compare to the IPA system sample at 85 °C measurement, a significant amount of 15% charge loss at 106 sec was observed. This result indicated the extent of nanocrystal isolation in the charge trapping layer was beneficial for data retention.
Therefore, the trapped electrons by isolated NCs were not easily to loss. Additionally, in Figure 4.6, ethanol system performed a relatively large memory window of about 10 V, larger than IPA system sample (~ 3V). We suggested the ethanol system with initially thinner film was beneficial for the better charge trapping performance on tunneling electrons due to isolated NCs formation of spinodal decomposition.
4.4 Summary
In conclusion, we compared the sol-gel film thickness factor that affected the morphology of NCs after annealing. The solvent for dissolving precursors played an important role on controlling viscosity of the sol-gel solution and thickness of the sol-gel spin coated film. The IPA system was more viscous than ethanol system for sol-gel solution under the same concentration preparation. The thinner film formed by ethanol system led to the isolated NCs, while the interconnected NCs morphology was observed of IPA system. The sol-gel derived isolated NCs of ethanol system exhibited better charge trapping performance and memory window.
Table 4.1 Dependence of viscosity and film thickness as a function of compositional molar ratio of sol-gel solutions.
Composition of precursor Concentration (in molar ratio)
Viscosity (cP)
ZrCl
4+HfCl
4+SiCl
4+Ethanol 1:1:1:1000 1.15
ZrCl
4+HfCl
4+SiCl
4+Ethanol 1:1:1:500 1.19
ZrCl
4+HfCl
4+SiCl
4+Ethanol 1:1:1:100 1.47
ZrCl
4+HfCl
4+SiCl
4+IPA 1:1:1:1000 2.45
ZrCl
4+HfCl
4+SiCl
4+IPA 1:1:1:500 precipitate
ZrCl
4+HfCl
4+SiCl
4+IPA 1:1:1:100 precipitate
Figure 4.1 The cross-sectional TEM images of the NCs transformation by (a) Ethanol system and (b) IPA system.
10 nm
(a)
10 nm
(b)
Figure 4.2 (a) Ethanol system (b) IPA system sample elemental composition of the binary metal oxides NCs were estimated by energy dispersive X-ray spectroscopy (EDS).
(a)
(b)
0.0 0.2 0.4 0.6 0.8 1.0
Figure 4.3 The metastable extensions of spinodal region in ZrO2–SiO2 phase diagram.
Figure 4.4 Phase separation mechanism of sol-gel derived nanocrystal on (a) ethanol system and (b) IPA system.
Figure 4.5 Retention characteristics of (a) ethanol system (b) IPA system derived NC memories at measurement temperatures of 25 and 85 °C.
10
010
110
210
310
410
510
6
Figure 4.6 Id-Vg curves of (a) ethanol system (b) IPA system derived NC memories in the programmed state of Vd=10V, Vg=15V, pulse time 10ms.
2 4 6 8 10 12 14
Chapter 5
Application of novel sol–gel spin coating method in SONOS-type flash memory
5.1 Introduction
Memory storage is an important technology that enables the growth in the information world. With the rapid growth of the internet, wireless communication products, personal digital assistants (PDAs), digital cameras, digital camcorders, digital music players, and computers, there is continually a demand for superior information storage technology. The development of portable consumer electronics has spurred the need for high-density nonvolatile memory with low power consumption for system on-chip applications. Considering the flexibility-cost plane, it turns out that the flash memory offers the best compromise between these two parameters, since they have smaller cell size and excellent flexibility (they can be electrically written on field more than 100,000 times, with byte programming and sectors erasing).[3] In recent years, flash memories based on charge storage in nitride traps, such as poly-silicon/SiO2/Si3N4/SiO2/semiconductor (SONOS) structures have been investigated intensively. However, the conventional SONOS memory still suffers from erase saturation and insufficient charge-trapping efficiency, which markedly degrade its performance.[63, 64]
was proposed in the early 1990s by Tiwari et al.[7]. The only stored charges at the nanocrystals adjacent to the defect leak through the tunneling dielectric, compared to huge charge loss of conventional flash memory due to the lateral charge transport.[65]
The possibility of exceeding the performance limits of the conventional floating-gate device spurred many subsequent investigations on this approach. Only the electrons stored on the nanocrystal directly above the defect chain will be affected since the nanocrystals are separated from each other. The tunnel oxide thickness of the nanocrystal memory device can be reduced to allow faster programming and lower voltage operation.[8]
Various techniques have been developed to form the nanocrystals in the gate oxide. For example, Gerardi et al.[66] employed the low pressure chemical vapor deposition (LPCVD) to fabricate Si nanocrystals for density up to 2×1012 cm-2 ,and then, utilized Si nanocrystals as the memory cell. King et al.[67] fabricated Ge nanocystals by oxidation of a Si1-xGex layer formed by ion implantation, and demonstrated quasi-nonvolatile memory operation with a 0.4 V threshold-voltage shift. Lin et al.[46] reported co-sputter technique to fabricate high density HfO2
nanocrystals and utilized to nanocrystal memories with about 4V threshold-voltage shift performance. In this thesis, we proposed a sol-gel spin-coating method to fabricate the charge trapping film or NC for the memory. This approach is relatively cheap, simple, and can be fabricated in a normal atmospheric pressure instead of high-vacuum system. We have successfully achieved the nanocrystal memories with superior characteristics in terms of considerably large memory window, high speed P/E, long retention time, and excellent endurance.
5.2 Experimental
The fabrication of a sol–gel spin-coating derived SONOS-like NC memory was started with a local-oxidation of silicon (LOCOS) isolation process on p-type (100) silicon substrate. At the beginning, a 10-nm tunneling oxide was thermally grown at 925 oC by furnace oxidation. The charge trapping layer was prepared by a sol-gel spin coating method and annealed at high temperature. The precursors utilized for the preparation of the sol-gel solution were zirconium tetrachloride (ZrCl4, 99.5%, Aldrich), hafnium tetrachloride (HfCl4, 99.5%, Aldrich), and silicon tetrachloride (SiCl4, 99.5%, Aldrich), all of analytical reagent grade. Ethanol (EtOH) was used as the solvent to dissolve the precursors to fabricate the starting sol-gel solution.
Hydrochloric acid was added to the solution as a catalyst because acid-catalyzed gels are therefore aggregates of very small ultimate particles. The solution after preparation was stirred for 0.5 hr for well mixing. Initially, we prepared a solution for which the molar ratio of HfCl4:ZrCl4:SiCl4:EtOH equal to 1:1:1:1000. The sol-gel thin film was deposited by spin coating at 3000 rpm for 60 sec at 25 oC. After spin coating, the wafer was under rapid thermal annealing (RTA) at 900 oC temperatures for 60 sec in O2 ambient to form sol-gel derived nanocrystal. Then, the 20-nm-thick blocking oxide was deposited by plasma enhanced chemical vapor deposition (PECVD) tetraethoxysilane (TEOS) oxide. Prior to deposit 200-nm a-Si gate, the TEOS oxide was densified in N2 ambient at 900 ◦C for 30 s anneal to repair the defects and decrease the number of traps. Finally, gate pattering, source/drain (S/D) implanting, and the rest of the subsequent metal-oxide-semiconductor processes were used to fabricate the NC-NVM devices. Figure 5.1 showed the structure of the fabricated device. The memory characteristics reported in this thesis with device W/L=10μm /0.35μm.
5.3 Results and discussion
Figure 5.2 showed the cross-sectional HRTEM image of sol-gel derived nanocrystals with the sol-gel solution of ZrCl4:HfCl4:SiCl4:EtOH=1:1:1:1000 spin coating at rotation speed of 3000rpm for 60 sec. The insert image showed the lattice fringe image of NC to confirm the crystalline result. We utilized the sol-gel derived NC as charge tapping layer in NC memory devices. The crystal size was estimated to be 6–10 nm in diameter. We inferred that the darker NCs in Figure 5.2 are formed from the high-molecular-weight hafnium silicate, and the bright NCs are from the low-molecular-weight zirconium silicate.
5.3.1 Program/Erase characteristics
In this thesis, the programming scheme was executed by using channel hot electron injection (CHEI) to inject charge into the trapping layer. Figure 5.3 showed the Id-Vg curve of NC memory under the programming state of Vg=10V, Vd=15V, 10ms pulse time and the Vth shift after programming can be up to 10 V. Figure 5.4 shows programming speed of the sol-gel derived NC flash memory. The program conditions were (i) Vg= 5V, Vd= 5V; (ii) Vg= 7V, Vd= 7V; (iii) Vg= 9V, Vd= 9V, respectively. The Vth shift increased as increasing the applied gate voltage because of more “hot” electrons generated and tunneled gate oxide to reach the trapping layer.
The hot electrons were trapped by charge trapping layer and caused Vth shift.
Relatively high speed (10μs) programming performance can be achieved with a memory window of about 2.2 V. Figure 5.5 displayed the erase characteristics as a function of various operation voltages. We used band-to-band hot hole (BTBHH) to erase, and the erase conditions were (i) Vg= -9V, Vd= 9V; (ii) Vg= -7V, Vd= 9V; (iii)
More important, there was only a very small amount of overerase observed.
5.3.2 Reliability characteristics Retention characteristic
The charge retention characteristic of the sol-gel derived NC memory device demonstrated in Figure 5.6. The normalized Vth shift was defined as the ratio of Vth
shift at the time of interest and at the beginning. Using the Vth shift as an indicator, the charge loss for the nanocrystal memory was exhibited. At 25 °C measurement, the retention times was extrapolated up to 106 sec for only ~5% charge loss, while less then 10% charge loss at 85 °C measurement. The 900 °C annealed sample retained its good retention characteristics for less than 25% charge loss at higher temperature measurement of 125 oC. This result explained the importance of NC formation for the sol-gel derived memory device. The NC discretely dispersed in the charge trapping layer, which alleviated the charge loss problem when defects existed in the tunneling oxide. The trapped electrons in the sol-gel-derived nanocrystal devices were not easily to escape, and the exhibited charge loss percentage was quite low in our device.
Endurence characteristic
The endurance characteristics after 104 P/E cycle was shown in Figure 5.7. The programming and erasing conditions are Vg=Vd=10V for 10ms and Vg=-6V, Vd=10V for 1s, respectively. Despite the occurrence of significant memory window narrowing, a memory window of about 6V was sustained even after 104 P/E cycles.
The origin of the narrowing over cycling, mainly coming from the increase of Vth in erased state, might be due to two factors: The first is the mismatch between the localized spatial distributions for injected electrons and holes by using channel
electrons will then cause the Vth to increase gradually over P/E cycling. The other is the stress-induced electron traps generated in the tunnel oxide during cycling. The result illustrated our device has excellent endurance performance.
Disturbance characteristic
Figure 5.8 showed the gate disturb characteristics. We measured the gate disturb on erase state devices and applied Vg=9V or 10V with Vd=Vs=Vb=0V to the device.
After 104 sec at 25 °C, small extent of less than 0.3V gate disturbs were found. Figure 5.9 illustrated the read disturb characteristics at 25 oC measurement. We measured the read disturb on erase state devices and operated at Vg=4V, Vd=2V with Vs=Vb=0V, the memory cell almost without any disturb. While at Vg=4V, Vd=4V operate, small read disturb of less than 0.5V were found after 104 sec measurement. Finally, we displayed the drain disturb on programmed state and applied Vd=5V or 10V with Vg=Vs=Vb=0V to the device, showed in Figure 5.10. The drain disturb of Vth shift after 104 sec operation was less than 0.3V at Vd=5V measurement, and less than 0.5V at Vd=10V measurement.
5.4 Summary
In this thesis, we utilized sol-gel spin coating method to fabricate the charge trapping layer of memory device. After high temperature annealing at 900 oC, the sol-gel thin film transferred into isolation nanocrystals. The size of the sol-gel derived nanocrystal was estimated to be about 6-10 nm. We verified the device performance such as the program/erase speed, charge retention, endurance and disturbs. The quality of the nanocrystals formed by the sol-gel spin coating method and RTA
retention time, excellent disturbs, and good endurance. Compare to other memory devices that ever reported on national journal paper, our device has excellent performance of memory window, data retention, and high write/erase speed.
Figure 5.1 Schematic diagram of the device structure for the spin coating charge
20 nm 20 nm
Figure 5.2 Cross-sectional TEM view of sol-gel derived nanocrystals. (Insert: lattice fringe of nanocrystal)
0 2 4 6 8 10 12 14 10
-1110
-1010
-910
-810
-710
-610
-5I
d(A)
V
g(V) Fresh Program Erase
Figure 5.3 Id-Vg curves of sol-gel derived NC memory in the programmed state (Vd=10V, Vg=15V, 10ms).
~10 V
Figure 5.4 Program speed of sol-gel derived NC memory device.
Figure 5.5 Erase speed of sol-gel derived NC memory device.
10
010
110
210
310
410
5Figure 5.7 Endurance of sol-gel derived memory device. The memory window is
Figure 5.8 Gate disturb characteristics of sol-gel derived memory.
Figure 5.9 Read disturb characteristics of sol-gel derived memory.
10
010
110
210
310
4Figure 5.10 Drain disturb characteristics of sol-gel derived memory.
Table 5.1 Comparison of various nanocrystal memory devices. SONOS[45]
1.2V~5.2V >106 P: >10-6
E: >10-5 Vertical
Chapter 6
Conclusions
We proposed a novel sol-gel spin-coating method utilized to deposit charge trapping layer for SONOS-like memory. The film formation with a spin coating is a more simple method than ALD, PVD, or CVD due to its cheaper precursor and tool.
In addition, the film can be fabricated in the normal pressure system instead of high-vacuum system.
In Chapter 3, we discussed the NCs formation of the sol-gel spin-coating thin film at various annealing temperatures. The XPS characterization indicated the annealing treatment under oxygen ambient activated the formation of metal silicates.
Together with the TEM images and interfacial energies, we proposed a mechanism to explain the transformation of sol-gel thin film to NCs. At 400 °C annealing, there was no effect occurred on sol-gel film. At 600 °C annealing, the sol-gel film started to be unstable. While annealing temperature was up to 900 °C, phase separation took place on the sol-gel film and made the thin film transformed to nanocrystals. During phase change, the sample surface had higher interfacial energy, and was minimized after crystallize to NCs. According to the data retention, we concluded that using the sol-gel derived NCs (900 oC annealing sample) as charge trapping layer exhibited better memory performance than thin film (600 oC annealing sample).
In Chapter 4, we investigated the sol-gel film thickness factor with respective to
solution precursors played an important role on the solution viscosity and film thickness. The IPA as solvent for sol-gel solution was more viscous than ethanol under the same concentration. For this reason, ethanol system can deposit thinner sol-gel film by spin coating method. The thinner film of ethanol system led to form the isolated NCs, while the interconnected NCs was observed in the thicker film of IPA system. The sol-gel derived isolated NCs of ethanol system exhibited better charge trapping performance and memory window.
In view of the sol-gel spin coating method was mature enough in our research. In Chapter 5, we utilized the best condition of sol-gel spin coating method for forming isolated NCs as charge trapping layer of a memory device. The sol-gel spin coating thin film transformed to nanocrystals after high temperature annealing (900 oC RTA) for phase separation of spinodal decomposition. The size of NCs was estimated to be 6-10 nm. We verified the NC memory device performance of the P/E speed, charge retention, endurance and disturbs. The quality of the NCs formed by the sol-gel spin coating method and RTA treatment exhibited excellent properties in terms of larger memory window, long retention time, good endurance, and superior disturbs.
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