Chapter 2 Characteristics of Low Temperature Poly-Si TFTs on FSG Buffer
2.5 Summary
A process-compatible scheme for fabricating poly-Si TFTs on an FSG buffer layer is proposed. Significant improvements in the device performance and uniformity were successfully demonstrated with fluorine incorporation in the poly-Si layer. This is attributed to the reduction of the trap state density in poly-Si and SiO2 interface.
Additionally, the incorporation of fluorine atoms also promotes the hot-carrier immunity due to the formation of the strong Si-F bonds. Fabricating poly-Si TFTs on FSG buffer layers with appropriate fluorine content improves not only the electrical performance and uniformity but also the reliability.
References:
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698-702, May 1994.
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Tanina, Y. Inoue, T. Nishimura and N. Tsubouchi, “Performance and reliability improvement in poly-Si TFT’s by fluorine implantation into gate poly-Si,” IEEE Trans. Electron Devices, vol. 42, pp. 1106-1112, Jun. 1995.
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Thermal Oxide Si Wafer
(a) Thermal oxidation grown by furnace.
Thermal Oxide Si Wafer FSG Layer
(b) FSG layer deposited by PECVD.
Thermal Oxide Si Wafer
FSG Layer
a-Si
(c) Amorphous Si (a-Si) deposited by LPCVD.
Thermal Oxide Si Wafer
FSG Layer
Poly-Si Channel
(d) Recrystallization of a-Si film into poly-Si channel by ELA, active region defined.
Thermal Oxide Si Wafer
FSG Layer
Poly-Si Channel TEOS Gate Oxide
Poly-Si Gate
(e) Deposition of TEOS gate oxide by PECVD and poly-Si gate by LPCVD.
Thermal Oxide Si Wafer
FSG Layer
Poly-Si Channel
Phosphorous self-aligned ion implantation
(f) The gate electrode defined and self-align phosphorous ion implantation.
Thermal Oxide Si Wafer
FSG Layer
Poly-Si
n
+n
+n
+(g) Dopant activation by excimer laser annealing.
Thermal Oxide Si Wafer
FSG Layer
Poly-Si
n
+n
+n
+(h) Deposition of passivation oxide, contact holes opened and metal pads formation.
Fig. 2-1 Process flow of the proposed poly-Si TFTs on a FSG buffer layer.
Table 2-1 Summary of different deposition conditions of FSG buffer layer.
Table 2-2 Summary of device parameters of the conventional and the proposed poly-Si TFTs (W/L = 40μm/10μm) with different FSG layer deposition conditions.
101 102 103 104 105
0.05 0.1 0.15 0.2 0.25
Control FSG1 FSG2 FSG3
Secondary Ion Counts (a.u.)
Depth (µm)
Buffer Layer
Fig. 2-2 SIMS profiles of the FSG layer as-deposited samples with different FSG layer deposition conditions.
10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3
-10 -5 0 5 10 15 20 25
FSG3 Control FSG1 FSG2
Dr a in Curr en t, I
D(A )
Gate Voltage, V
G
(V)
V
DS=5V
W/L = 40µm/10µm
Oxide thickness = 100nm
Fig. 2-3 Transfer characteristics of the conventional and the proposed poly-Si TFTs with different FSG layer deposition conditions.
0 20 40 60 80 100
-10 -5 0 5 10 15 20 25
Control FSG1 FSG2 FSG3
Field Effect Mobility,
µ
eff (cm2 /V.sec)Gate Voltage, V
G (V) W/L = 40µm/10µm
Oxide thickness = 100nm
VDS=0.1V
Fig. 2-4 Field effect mobility of the conventional and the proposed poly-Si TFTs with different FSG layer deposition conditions.
1017 1018 1019 1020 1021
0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7
Control FSG1 FSG2 FSG3
F Concentration (cm-3 )
Depth (
µm
)Oxide Poly-Si Buffer
Oxide Substrate
Fig. 2-5 SIMS profiles of the conventional and the proposed poly-Si TFTs with different FSG layer deposition conditions.
-17 -16 -15 -14 -13 -12
0 0.005 0.01 0.015 0.02 0.025
Control FSG1 FSG2 FSG3
y = -12.252 - 392.15x R= 0.99345 y = -12.109 - 188.04x R= 0.99922 y = -11.714 - 193.92x R= 0.99991 y = -11.827 - 235.27x R= 0.999
ln [ I DS/(V GS-V FB) ] (Ω-1 )
1/(VDS-V
FB)2 (V-2) Nt=5.64x1012cm-2
Nt=3.91x1012cm-2 Nt=3.97x1012cm-2
Nt=4.01x1012cm-2
Fig. 2-6 Trap state density extraction of the conventional and the proposed poly-Si TFTs with different FSG layer deposition conditions.
Buffered FSG Oxide
(a) Field effect mobility distribution
Buffered FSG Oxide
(b) Leakage current distribution
`
Buffered FSG Oxide
control FSG1 FSG2 FSG3
Threshold Voltage (V)
4.0 4.5 5.0 5.5 6.0 6.5 7.0
(c) Threshold voltage distribution
Fig. 2-7 Distribution of (a) filed-effect mobility and (b) leakage current of the poly-Si TFTs on different buffer layers. The vertical bars indicate the minimum and maximum values of the devices characteristics and the squares are the average values.
-35
(a) On-current degradation with stress time
0
(b) Threshold voltage degradation with stress time
-70 -60 -50 -40 -30 -20 -10 0 10
0 200 400 600 800 1000
Control FSG1 FSG2 FSG3 µ eff Variations (%)
Stress time (s) Stress condition
VG=10V ; V
D=20V
(c) Field effect mobility degradation with stress time
Fig. 2-8 (a) on-current, (b) threshold voltage, and (c) field effect mobility degradation as a function of stress time under hot-carrier stress.
Chapter 3
Electrical Characteristics and Reliability of Multi-channel Poly-Si TFTs
3.1 Introduction
It is known that the existence of grain boundaries within the poly-Si channel region has great influence on the electrical characteristics of poly-Si TFTs [1][2]. In some previous research reports, it has been demonstrated that there are a large number of grain boundary trap states in the poly-Si channel, and localized potential barriers are produced for the transportation of carriers from grain to grain [3-5].
Many suggestions have been proposed and revealed that poly-Si TFTs with narrow channel width have better performance such as lower threshold voltage [6], smaller subthreshold swing [7], and effective kink effect suppression [8][9] due to the reduction of grain boundary trap states. It has been concluded that the grain boundary trap states existed in the channel near the pattern edge is much lower than elsewhere [6]. As the channel width is scaled down, the effect of the poly-Si pattern edge become dominant. Additionally, it has also been reported that kink effect can be enhanced with the existence of grain boundary trap states [8][9]. The larger grain boundary trap state causes the severer impact ionization, and results in pronounced kink effect.
Moreover, the gate electrode across the channel may induce side-channels in both sides of the channel region and these side-channels will increase the effective channel width. Especially, when channel width scaled down, the side-channel effect
might be more distinct. The average carrier concentration in the channel region of the poly-Si gate electrode corner is increased by the electrostatic focusing from the top gate and both side gates of the stripes [10]. It is believed that the gate control capability was improved obviously in narrow width devices. Accordingly, poly-Si TFTs with narrow and multiple channels have been proposed to enhance the electrical characteristics [10-13]. However, there is no complete reliability analysis in the poly-Si TFTs with narrow and multiple channels.
In this chapter, we demonstrate that the fabrication process and electrical characteristics of n-channel ploy-Si TFTs with different narrow channel stripes. We can see that poly-Si TFTs with multiple channels have better performance than that of the conventional TFTs. Finally, we make a complete discussion about the reliability issue of poly-Si TFTs with multiple channels.
3.2 Experimental
Figure 3-1 shows the process flow of the proposed poly-Si TFTs. First, 500-nm-thick thermal oxide was grown on the Si wafer by using a furnace system. All the experimental devices in this study were fabricated on thermally oxidized Si wafers.
Then, 100-nm-thick amorphous silicon layers were deposited on the thermal oxide layer using a low-pressure chemical vapor deposition (LPCVD) system at 550°C.
Then, amorphous silicon films were recrystallized by solid phase crystallization (SPC) method at 600°C for 24 hours in an N2 ambient to form poly-Si films. Poly-Si films were patterned into active regions by transformer couple plasma (TCP) etching system using mixture gases of Cl2 and HBr.
After RCA cleaning procedure, a 100-nm-thick TEOS oxide was deposited by LPCVD with TEOS and O2 gases at 695°C to form the gate insulator. A 200-nm-thick
poly-Si was deposited to serve as the gate electrode by LPCVD at 595°C. Then, the poly-Si film was patterned and etched by TCP etching system to form the gate electrode and the gate oxide on source/drain was removed using dilute HF solution.
The regions of source, drain, and gate were doped by a self-aligned phosphorous ion implantation at the dosage and energy of 5×1015ions/cm-2 and 40keV, respectively.
The dopant activation was performed by rapid thermal annealing (RTA) system at 700°C for 20sec, followed by a deposition of 400nm-thick passivation oxide using PECVD system at 350°C and the definition of contact holes. Finally, a 500-nm-thick Al was deposited by sputter and patterned for metal pads, and devices were passivated by NH3 plasma treatment for 2 hours at 300°C.
Figure 3-2 presents the cross-section of the conventional and multi-channel poly-Si TFTs, which is parallel to the direction of the source and drain electrode.
Figure 3-3 depicts the cross-section perpendicular to the direction of the source and drain electrode. In next section, we will discuss the transfer characteristics of the conventional and proposed TFTs with single, 8, 20, and 40 stripes of the same total channel width, as shown in Fig. 3-4. The detailed data of these structures were summarized in Table 3-1. Moreover, we will also discuss the reliability issue of the conventional and proposed TFTs with different stripes of channel.
3.3 Results and Discussion
3.3.1 Characteristics of Poly-Si TFTs with Multiple Channels
Figure 3-5 shows the transfer characteristics (IDS-VGS) for the conventional and proposed TFTs with different stripes of channel. Table 3-2 summarizes the measured and extracted parameters from the devices. The threshold voltage, subthreshold swing, on-state current (VGS=20V) and the off-state current (VGS=-5V) were measured at
VDS=1V. As can be seen, the electrical characteristics of the poly-Si TFTs with multiple channels are significantly improved. The threshold voltage and subthreshold swing decreased with the stripes of channel.
It has been reported that the grain boundary trap state density in the channel regions near the pattern edge is much lower than elsewhere in the poly-Si channel [6][7]. In order to verify if the trap state density reduced or not, the effective trap state density (Nt) was calculated. Figure 3-7 shows the effective trap state density of the poly-Si TFTs with various stripes of channel. The effective trap state density for S1, M8, M20, and M40 are 5.80×1012cm-2, 5.71×1012cm-2, 5.40×1012cm-2, and 5.06×1012cm-2, respectively. Actually, the Nt is calculated from transfer characteristics.
Therefore, we deduce that the improved Nt, threshold voltage, and subthreshold swing were owing to the improvement in the gate control capability in the TFT with various stripes. This is because the better gate control capability causes the lower potential barrier locating at the grain boundary.
Moreover, as in Fig. 3-5 and Fig. 3-6, the on-state current and field effect mobility are also improved as the stripes of poly-Si channel increase. Generally, the increase of effective channel width due to additional sidewall may result in the enhancement of on-stated current. However, from Fig. 3-8, we can see that the increase ratios of the on-state current for M8, M20, and M40 are 7.45%, 24.9%, and 36.3%, respectively, and they are much larger than the increase ratio of the effective channel width. Therefore, it can be concluded that the channel sidewall effect was not the dominant factor to improve the electrical characteristics of multiple channel poly-Si TFTs. The improvements on the on-stated current and field effect mobility were contributed to the increasing average carrier concentration due to the enhancement of gate control capability [10], because the electrostatic focusing from the top gate and both side gates of the stripes caused the average carrier concentration
in the channel region of the poly-Si gate electrode corner to increase.
Figure 3-9 shows the output characteristics of the conventional and proposed poly-Si TFTs with different stripes of channel under VG－Vth=0.5; 2; 3.5V. It can be seen that the kink effect was suppressed with the increase of the stripes of poly-Si channels. The better gate control ability, the larger depletion region existed in the channel, and therefore the fewer holes accumulated within the channel region. So, it can be concluded that the kink effect suppression was attributed to the improvement of gate control capability.
Figure 3-10 presents the on-state current, field effect mobility, and threshold voltage as a function of different gate length with the number of channel stripes. We can see that the threshold voltage, field effect mobility, and on-state current were improved with increasing the number of channel stripes. This result can be found in every channel length. However, it can also be seen that the field effect mobility decreased with the increase of channel length. We attribute this phenomenon to the increase of series resistance.
3.3.2 Reliability of Poly-Si TFTs with Multiple Channels
Finally, the reliability issue of the conventional and the proposed poly-Si TFTs with single, 2, 4, 10, and 20 stripes of the same total channel width were discussed.
The hot-carrier stress test was performed at VD,stress=15V, VG,stress=10V, and source electrode grounded for 200sec to investigate the device reliability. Figure 3-11 shows the variations of the on-state current (Ion) and threshold voltage (Vth) over hot carrier stress time. The variations of Ion and Vth, were defined as (Ion,stressed － Ion,initial)/Ion,initial×100% and (Vth,stressed－Vth,initial)/Vth,initial×100%, respectively, where Ion,stressed, Vth,stressed, Ion,initial, and Vth,initial, represent the measured values before and after
electrical stress. Generally, less grain boundary trap state density will cause slighter impact ionization under hot carrier stress, and hence the reliability of device will be improved. However, in Fig. 3-11, we can see that the degradation rate of the on-state current and threshold voltage deteriorated with the increase of the stripes of poly-Si channel. Therefore, we will make a discussion about this phenomenon.
Figure 3-12 presents the trap state density in the poly-Si channel before and after 4sec, 10sec, and 100sec hot carrier stress with the stress conditions of VDS=15V, VGS=10V and source electrode grounded. Figure 3-13 shows the increasing ratio of trap state density within the channel after 4sec, 10sec, and 100sec electrical stress. It was significantly demonstrated that the trap state density after hot carrier stress increased with poly-Si channel stripes increasing. To explain this phenomenon, we used MEDICI to simulate the electric field distribution in the channel region of device with dual-gate and single-gate, as shown in Fig. 3-15 and Fig. 3-16, respectively.
Figure 3-14 shows the schematic plot of dual-gate and single-gate structures for simulations. To simplify the simulation, in this model, we only considered the influence of the number of gate strips, and not considered that of the grain boundary.
We can see that the electric field strength at the drain side of the dual-gate poly-Si TFTs is larger than that of the single-gate poly-Si TFTs under the same bias conditions (VDS=15V, VGS=10V). Of course, this phenomenon will be more significant in the tri-gate poly-Si TFTs. Besides electric field strength near the drain, corner effect and sidewall roughness will also enhance the device’s degradation rate. Therefore, it is concluded that the electric field at the drain side was enlarged with the increase of the stripes of poly-Si channel under hot carrier stress to cause severer impact ionization and hence to generate more trap states.
3.4 Summary
The effects of the numbers of the channel strips in multi-channel TFTs on the performance and reliability have been investigated. As the stripes increased, the electrical characteristics of devices were improved significantly due to the enhancement of gate control capability. However, a severer reliability was found which can be attributed to the enlargement of electric field at drain side. Therefore, for the fabrication of high reliable devices and yield improvement of multi-channel TFTs, the channel structures must be carefully designed.
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• Wet oxide 5000Å by furnace
• a -Si channel 1000Å by LPCVD
• Poly-Si channel formation by SPC
• Gate oxide 500Å by LPCVD
• Poly Gate 2000Å by LPCVD
• S/D formation by ion implantation
• Passivation by PECVD
• Metal pad
Fig. 3-1 Process flow of the conventional and multi-channel poly-Si TFTs.