Chapter 1 Introduction
1.3 Organization of the Thesis
In the following sections, we will show our research efforts.
In Chapter 2, the electrical characteristics and fabrication processes of low temperature poly-Si TFTs on an FSG buffer layer will be proposed. Experimental results reveal that the reliability and uniformity of our devices have remarkable improvements in comparison with conventional TFTs. In addition, we will discuss the degradation phenomenon on electrical characteristics and reliability caused by the incorporation of too many fluorine atoms.
In Chapter 3, the fabrication processes and electrical characteristics of n-channel ploy-Si TFTs with different stripes of channel will be proposed. Experimental results reveal that poly-Si TFTs with multiple channels have better performance than the conventional TFTs. Then, we will make a complete discussion about the reliability issue of poly-Si TFTs with multiple channels.
In Chapter 4, the reliability issue of poly-Si TFTs will be investigated by applying different drain bias. It is found that Ion degradation under both high and low drain bias of stress conditions has different phenomenon. Then, we will analyze the
degradation mechanism under hot carrier stress with low drain bias.
At the end of this thesis, we will make a conclusion in Chapter 5.
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Chapter 2
Characteristics of Low Temperature Poly-Si TFTs on FSG Buffer Layer
2.1 Introduction
Polycrystalline silicon thin-film transistors (poly-Si TFTs) have attracted much attention owing to the possibility of realizing the integration of driving circuits and pixel switching elements on a single glass substrate, and the potential to accomplish the System-on-Panel (SOP) [1]. High-performance and high-reliability poly-Si TFTs are required to achieve this goal. Excimer laser annealing (ELA) has been utilized in enlarging the grain size of the poly-Si to reduce trap states, leading to an excellent device performance [2][3]. However, the random distribution of grain boundaries in poly-Si films still causes a large leakage current and poor device uniformity.
Hydrogenation process has been utilized to terminate the grain boundary trap states [4]. Unfortunately, hydrogenated poly-Si TFTs suffer from an instability issue due to weak Si-H bonds breaking [5]. On the other hand, a low-temperature PECVD-oxide buffer layer is conventionally adopted to block the contaminations from the inexpensive glass or flexible plastic substrate. Nevertheless, the mismatch between the thermal expansion coefficient of the poly-Si and that of the oxide causes considerable mechanical tensile stress at the interface during ELA, leading to the degradation in device performance [6-9]. All these drawbacks limit the applications of poly-Si TFTs.
Recently, fluorine atoms have been proposed to passivate trap states in the
poly-Si [10-15]. This is because that the rather strong Si-F bonds exist in the poly-Si channel and SiO2/poly-Si interface, and thus reduce the trap-state density in the poly-Si channel region. In addition, the composition of Si-F bonds is more stable than Si-H bonds and Si-O bonds, and improves the device reliability obviously. However, ion implantation is not appropriate for extremely large-sized glass substrate in current productions. High temperature process that was required to activate implanted fluorine atoms and recover the damage created by implantation is not compatible with the AMLCD process application. In addition, another method that deposited fluorine-doped silicon oxide (SiOxFy) on the channel as a diffusion source of fluorine atoms was revealed by C. H. Kim et al, but that caused the process more complicated due to an extra etching step.
Therefore, a new method must be found to introduce fluorine atoms into poly-Si films. Fluorinated silicate oxide (FSG) has been known easy to integrate using plasma-enhanced chemical vapor deposition (PECVD) systems. The out-diffused fluorine atoms form FSG can terminate trap states and also release the strain bonds at the interface [16]. This work proposes a novel process-compatible fluorination technique using a FSG film as the buffer layer. Poly-Si TFTs fabricated on FSG buffer layers exhibit high device performance, uniformity and reliability.
2.2 Experimental
Figure 2-1 schematically depicts the process flow of the proposed poly-Si TFT.
First, 500-nm-thick thermal oxide was grown on the Si wafers by furnace system to substitute for the glass substrate and all the experimental devices in this study were fabricated on thermally-oxidized Si wafers. Then, a 40-nm-thick FSG buffer layer was deposited using a PECVD system at 350°C with SiH4, CF4 and N2O as process gases.
In order to determine the effect of fluorine content in FSG layers, varying CF4 flow rates of 10, 20, and 40 sccm, with a SiH4 flow rate of 90 sccm and a N2O rate of 5 sccm, were used to grow various FSG buffer layers, denoted by FSG1, FSG2 and FSG3, respectively. Table 2-1 lists the conditions of precursors to grow FSG buffer layers. The fluorine contents in FSG1, FSG2 and FSG3 were calculated from the SIMS profiles of the as-deposited FSG layers (as shown in Fig. 2-2) and were about 2%, 4%, and 7%, respectively.
Then, 100-nm-thick amorphous silicon layers were deposited on the FSG buffer layers in a low-pressure chemical vapor deposition (LPCVD) system with silane (SiH4) gas source at 550°C. The deposition pressure was 100mTorr and the SiH4 flow rate was 40sccm. Next, a semi-Gaussian-shaped KrF excimer laser with wavelength of 248nm was performed for the phase transformation from amorphous to polycrystalline silicon at the laser energy density of 420mJ/cm2 with substrate heating of 400°C under the chamber pressure of 10-3Torr. The average grain size of the poly-Si is approximately 300nm.
Individual active regions were then patterned and defined. After a clean process, a 100-nm-thick TEOS oxide was deposited with TEOS and O2 gas source by PECVD at 350°C for gate insulator. A 200-nm-thick poly-Si was deposited to serve as the gate electrode by LPCVD. Then, gate electrode was patterned and the regions of source, drain, and gate were doped by a self-aligned phosphorous ion implantation at the dosage and energy of 5×1015ions/cm-2 and 40keV, respectively. The dopant activation was performed by excimer laser annealing with laser energy density of 220mJ/cm2, followed by a deposition of 400nm-thick passivation oxide in a PECVD system at 350°C and the definition of contact holes. Finally, a 500-nm-thick Al electrode was deposited by thermal evaporation and patterned for metal pads. For comparison, the control samples were fabricated on a 40-nm-thick conventional PECVD-oxide buffer
layer.
2.3 Method of Device Parameter Extraction
In this thesis, we use Ellipsometer to measure the thickness of poly-Si, amorphous-Si and TEOS oxide films in the fabrication procedure. All the electrical characteristics of proposed poly-Si TFTs were measured by HP 4156B-Precision Semiconductor Parameter Analyzer.
Many methods have been proposed to extract the characteristic parameters of poly-Si TFTs. In this section, those methods are described.
2.3.1 Determination of Threshold Voltage
Threshold voltage (Vth) is an important parameter required for the channel length-width and series resistance measurements. However, Vth is not uniquely defined. Various definitions have been proposed and the reason can be found in ID-VGS curves. One of the most common techniques is the linear extrapolation method with the drain current measured as a function of gate voltage at a low drain voltage of 50~100mV to ensure operation in the linear region [17]. The drain current is not zero when VGS below threshold voltage and approaches zero asymptotically. Hence the IDS
versus VGS curve can be extrapolated to ID=0, and the Vth is determined from the extrapolated intercept of gate voltage (VGSi) by
2
DS GSi th
V V
V = − --- (Eq. 2.1) Equation (2.1) is strictly only valid for negligible series resistance. Fortunately series resistance is usually negligible at the low drain current when threshold voltage measurements are made. The IDS-VGS curve deviates from a straight line at gate voltage below Vth due to subthreshold current and above Vth due to series resistance
and mobility degradation effects. It is common practice to find the point of maximum slope of the IDS-VGS curve and fit a straight line to extrapolate to ID=0 by means of finding the point of maximum of transconductance (Gm).
In this thesis, we use a simpler method to determinate the Vth called constant drain current method. The voltage at a specified threshold drain current is taken as the Vth. This method is adopted in the most studied papers of poly-Si TFTs. It can be given a threshold voltage close to that obtained by the complex linear extrapolation method. Typically, the threshold current is specified at (W/L)×10nA for VDS=0.1V and (W/L)×100nA for VDS=5V, where W and L are channel width and channel length, respectively.
2.3.2 Determination of Subthreshold-Swing
Subthreshold swing (S.S.) is a typical parameter to describe the control ability of gate toward channel, which reflects the turn on/off speed of a device. It is defined as the amount of gate voltage required to increase/decrease drain current by one order of magnitude.
The S.S. should be independent of drain voltage and gate voltage. However, in reality, the S.S. increases with drain voltage due to channel shortening effect such as charge sharing, avalanche multiplication and punchthrough effect. The subthreshold swing is also related to gate voltage due to undesirable and inevitable factors such as the serial resistance and interface states.
In this thesis, the S.S. is defined as one-third of the gate voltage required to decrease the threshold current by three orders of magnitude. The threshold current is specified to be the drain current when the gate voltage is equal to threshold voltage.
2.3.3 Determination of Field Effect Mobility
Usually, field effect mobility (µeff) is determined from the maximum value of transconductance (Gm) at low drain bias. The transfer characteristics of poly-Si TFTs are similar to those of conventional MOSFETs, so that the first order of I-V relation in the bulk Si MOSFETs can be applied to poly-Si TFTs. The drain current in linear region (VDS＜VGS－Vth) can be approximated as the following equation:
( )
⎥⎦⎤where W and L are channel width and channel length, respectively. Cox is the gate oxide capacitance per unit area and Vth is the threshold voltage. Thus, the transconductance is given by
DS
Therefore, the field-effect mobility is
(max) →0
2.3.4 Determination of ON/OFF Current Ratio
On/off current ratio is one of the most important parameters of poly-Si TFTs since a high-performance device exhibits not only a large on-current but also a small off-current (leakage current). The leakage current mechanism in poly-Si TFTs is not like that in MOSFET. In MOSFET, the channel is composed of single crystalline Si and the leakage current is due to the tunneling of minority carrier from drain region to accumulation layer located in channel region. However, in poly-Si TFTs, the channel is composed of poly-Si. A large amount of trap state densities in grain structure attribute a lot of defect states in energy band gap to enhance the tunneling effect.
Therefore, the leakage current is much larger in poly-Si TFTs than in MOSFET. When
the voltage drops between gate voltage and drain voltage increases, the band gap width decreases and the tunneling effect becomes much more severe. Normally we can find this effect in typical poly-Si TFTs’ IDS-VGS characteristics where the magnitude of leakage current will reach a minimum and then increase as the gate voltage decreases/increases for n/p-channel TFTs.
There are a lot of ways to specify the on and off-current. In this chapter, take n-channel poly-Si TFTs for examples, the on-current is defined as the drain current when gate voltage at the maximum value and drain voltage is 5V. The off-current is specified as the minimum current when drain voltage equals to 5V.
V
2.3.5 Extraction of Grain Boundary Trap State Density
The Trap State Density (Nt), which can be determined by the theory established by Levinson et al. [18], which is based on Seto’s theory [19].
For poly-Si TFTs, the drain current IDS can be given as following:
⎟⎟
This expression, first developed by Levinson et al., is a standard MOSFET’s equation with an activated mobility, which depends on the grain-boundary barrier
height. Levinson et al. assumed that the channel thickness was constant and equal to the thickness of the poly-Si film (t). This simplifying assumption is permissible only for very thin film (t<10nm). The trap-state density can be obtained by extracting a straight line on the plot of ln(IDS/VGS) versus 1/VGS at low drain voltage and high gate
height. Levinson et al. assumed that the channel thickness was constant and equal to the thickness of the poly-Si film (t). This simplifying assumption is permissible only for very thin film (t<10nm). The trap-state density can be obtained by extracting a straight line on the plot of ln(IDS/VGS) versus 1/VGS at low drain voltage and high gate