Reliability of Poly-Si TFTs with Multiple Channels

Finally, the reliability issue of the conventional and the proposed poly-Si TFTs with single, 2, 4, 10, and 20 stripes of the same total channel width were discussed.

The hot-carrier stress test was performed at V_D,stress=15V, V_G,stress=10V, and source electrode grounded for 200sec to investigate the device reliability. Figure 3-11 shows the variations of the on-state current (I_on) and threshold voltage (V_th) over hot carrier stress time. The variations of Ion and Vth, were defined as (Ion,stressed － I_on,initial)/I_on,initial×100% and (Vth,stressed－V_th,initial)/V_th,initial×100%, respectively, where Ion,stressed, Vth,stressed, Ion,initial, and Vth,initial, represent the measured values before and after

electrical stress. Generally, less grain boundary trap state density will cause slighter impact ionization under hot carrier stress, and hence the reliability of device will be improved. However, in Fig. 3-11, we can see that the degradation rate of the on-state current and threshold voltage deteriorated with the increase of the stripes of poly-Si channel. Therefore, we will make a discussion about this phenomenon.

Figure 3-12 presents the trap state density in the poly-Si channel before and after 4sec, 10sec, and 100sec hot carrier stress with the stress conditions of V_DS=15V, VGS=10V and source electrode grounded. Figure 3-13 shows the increasing ratio of trap state density within the channel after 4sec, 10sec, and 100sec electrical stress. It was significantly demonstrated that the trap state density after hot carrier stress increased with poly-Si channel stripes increasing. To explain this phenomenon, we used MEDICI to simulate the electric field distribution in the channel region of device with dual-gate and single-gate, as shown in Fig. 3-15 and Fig. 3-16, respectively.

Figure 3-14 shows the schematic plot of dual-gate and single-gate structures for simulations. To simplify the simulation, in this model, we only considered the influence of the number of gate strips, and not considered that of the grain boundary.

We can see that the electric field strength at the drain side of the dual-gate poly-Si TFTs is larger than that of the single-gate poly-Si TFTs under the same bias conditions (V_DS=15V, V_GS=10V). Of course, this phenomenon will be more significant in the tri-gate poly-Si TFTs. Besides electric field strength near the drain, corner effect and sidewall roughness will also enhance the device’s degradation rate. Therefore, it is concluded that the electric field at the drain side was enlarged with the increase of the stripes of poly-Si channel under hot carrier stress to cause severer impact ionization and hence to generate more trap states.

3.4 Summary

The effects of the numbers of the channel strips in multi-channel TFTs on the performance and reliability have been investigated. As the stripes increased, the electrical characteristics of devices were improved significantly due to the enhancement of gate control capability. However, a severer reliability was found which can be attributed to the enlargement of electric field at drain side. Therefore, for the fabrication of high reliable devices and yield improvement of multi-channel TFTs, the channel structures must be carefully designed.

References:

[1] J. Levinson, F. R. Shepherd, P. J. Scalom, W. D. Westwood, G. Este, and M. Rider,

“Conductivity behavior in polycrystalline semiconductor thin film transistor,” J.

Appl. Phys., vol. 53, no. 2, pp. 1193-1202, 1982.

[2] J. G. Fossum and A. Ortiz-Conde, “Effects of grain boundaries on the channel conductancem of SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 30, no. 8, pp. 933-940, 1983.

[3] G. Baccarani, B. Ricco, and G. Sachini, “Transport properties of polycrystalline silicon films,” J. Appl. Phys., vol. 49, no. 11, p. 5565-5570, 1978.

[4] T. I. Kamins, “Field-effects in polycrystalline-silicon films,” Solid-State Electron., vol. 15, pp. 789-799, 1972.

[5] J. W. Seto, “Electrical properties of polycrystalline silicon films,” J. Appl. Phys., vol. 46, pp. 5247-5254, 1975.

[6] N. Yamauchi, J-J. J. Hajjar, R. Reif, K. Nakazawa, and K. Tanaka, “Characteristics of narrow-channel polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 38, no. 8, pp.1967-1968, Aug. 1991.

[7] H. W. Zen, T. C. Chang, P. S. Shih, D. Z. Peng, T. Y. Hwang, and C. Y. Chang,

“Analysis of narrow width effects in polycrystalline silicon thin film transistors,”

Jpn. J. Appl. Phys., vol. 42, pp.28-32, 2003.

[8] P. S. Shih, H. W. Zan, T. C. Chang, T. Y. Huang, and C. Y. Chang, “Dimensional effects on the drain current of n- and p-channel polycrystalline silicon thin film transistors,” Jpn. J. Appl. Phys., vol. 39, pp. 3879-3882, July 2000.

[9] H. W. Zan, P. S. Shih, T. C. Chang, and C. Y. Chang, “Dimensional effects on the reliability of polycrystalline silicon thin-film transistors,” Microelectronics Reliability, vol. 40, pp. 1479-1483, 2000.

[10] T. Takeshita, T. Unagami, and O. Kogure, “Study on narrow-stripe polycrystalline silicon thin-film transistors,” Jpn. J. Appl. Phys., vol. 27, no. 10, pp. 1937-1941, Oct. 1988.

[11] T. Unagami, and O. Kogure, “Large on/off current ratio and low leakage current poly-Si TFT’s with multichannel structure,” IEEE Trans. Electron Devices, vol. 35, no. 11, pp. 1986-1989, Nov. 1988.

[12] T. Unagami, “High-voltage poly-Si TFT’s with multichannel structure,” IEEE Trans. Electron Devices, vol. 35, no. 12, pp. 2363-2367, Dec. 1988.

[13] Y. C. Wu, C. Y. Chang, T. C. Chang, P. T. Liu, C. S. Chen, C. H. Tu, H. W. Zan, Y.

H. Tai, and S. M. Sze, “High performance and high reliability polysilicon thin-film transistors with multiple nano-wire channels,” in IEDM Tech. Dig., pp.

777-780, Dec. 2004.

• Wet oxide 5000Å by furnace

• a -Si channel 1000Å by LPCVD

• Poly-Si channel formation by SPC

• Gate oxide 500Å by LPCVD

• Poly Gate 2000Å by LPCVD

• S/D formation by ion implantation

• Passivation by PECVD

• Metal pad

Fig. 3-1 Process flow of the conventional and multi-channel poly-Si TFTs.

Poly-Si

n

⁺

n

⁺

n

⁺

Buffer Thermal Oxide Si Wafer

Fig. 3-2 Cross-section of the conventional and multi-channel poly-Si TFTs is parallel to the direction of the source and drain electrode.

Poly-Gate

G1 G1

G2 G3

G3

Gox Gox

Channel Channel

Fig. 3-3 Cross-section of the conventional and multi-channel poly-Si TFTs is perpendicular to the direction of the source and drain electrode.

S D G

(a) Conventional TFT with single channel (S1)

S D

G

(c) Multi-channel TFT with 8 stripes (M8)

S D

G

(d) Multi-channel with 20 stripes (M20)

S D G

(e) Multi-channel with 40 stripes (M40)

Fig. 3-4 Top view of the conventional and multi-channel poly-Si TFTs in (a), (b), (c), and (d). (The effective channel width Weff = 40μm ; channel length L = 2μ m.)

Table 3-1 Summary of the dimensions of S1, M4, M8, M20, and M40 TFTs. All devices have the same active channel thickness 100nm, gate TEOS-oxide thickness 50nm, and total channel width 40μm.

1

Table 3-2 Summary of device parameters of the conventional and the proposed multi-channel poly-Si TFTs (W/L = 40μm/2μm) with different stripes of channel.

10^-11 10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4 10^-3

-5 0 5 10 15 20

S1 M8 M20 M40

Drain Currnet, I D (A)

Gate Voltage, V_G (V)

W/L = 40µm/2µm

VD = 1V Tox = 50nm

Fig. 3-5 Transfer characteristics of the conventional and the proposed multi-channel poly-Si TFTs with different stripes of channel.

0 5 10 15 20 25 30 35

-5 0 5 10 15 20

S1 M8 M20 M40

Field Effect Mobility,

µ

eff (cm2 /V.sec)

Gate Voltage, V

G (V) W/L = 40µm/2µm

VD = 0.1V

Fig. 3-6 Field effect mobility of the conventional and the proposed multi-channel poly-Si TFTs with different stripes of channel.

-12.5 -12 -11.5 -11 -10.5

0.003 0.007 0.01

S1 M8 M20 M40

y = -10.388 - 180.73x R= 0.99945 y = -10.375 - 175.26x R= 0.9997 y = -10.319 - 156.42x R= 0.99955 y = -10.296 - 137.66x R= 0.99968

ln [ I DS/(V GS-V FB) ] (Ω-1 )

1/(VDS-V

FB)² (V^-2)

Nt=5.06x10¹²cm^-2

Nt=5.40x10¹²cm^-2 Nt=5.71x10¹²cm^-2 Nt=5.80x10¹²cm^-2

Fig. 3-7 Trap state density extraction of the conventional and the proposed multi-channel poly-Si TFTs with different stripes of channel.

0 5 10 15 20 25 30 35 40

0 10 20 30 40 50

Effective channel width On-state current

Percentage (%)

Number of Channel Stripe

on-state current measured at VDS=1V ; V

GS=20V W/L = 40µm/2µm

Fig. 3-8 Increasing ratio of the effective channel width and the on-state current as a function of number of channel stripes.

0 0.1 0.2 0.3 0.4 0.5 6 0.6

0 2 4 6 8 10

S1 M8 M20 M40

Drain Current, I D (mA)

Drain Voltage, V_D(V) W/L = 40µm/2µm

V_G - V_th = 0.5 ; 2 ; 3.5V

Fig. 3-9 Output characteristics of the conventional and the proposed poly-Si TFTs with different stripes of channel. (VG – Vth = 0.5; 2; 3.5V)

1 10^-4

Drain Currnet, I D (A)

Gate Length (µm) Field Effect Mobility, µ eff (cm2 /V.sec)

Gate Length (µm) W=40µm

VD=0.1V

(b) Field effect mobility

8 8.5 9 9.5 10 10.5 11

0 2 4 6 8 10 12

S1 M8 M20 M40

Threshold Voltage (V)

Gate Length (µm) W=40µm

(c) Threshold voltage

Fig. 3-10 (a) on-state current, (b) field effect mobility, and (c) threshold voltage as a function of different gate length with the number of channel stripes.

-100

(a) On-state current degradation with stress time

0

(b) Threshold voltage degradation with stress time

Fig. 3-11 (a) on-current, and (b) threshold voltage degradation as a function of stress time under hot-carrier stress.

3 Trap State Density, N t (1012 cm-2 )

Number of Channel Stripe 20µm/2µm Stress condition VG=10V ; V

D=15V

Fig.3-12 Trap state density (Nt), before and after 4sec, 10sec, and 100sec stress with different number of channel stripes.

0

N t increasing ratio (%)

Number of Channel Stripe 20µm/2µm Stress condition VG=10V ; V

D=15V

Fig. 3-13 Increasing ratio of trap state density after 4sec, 10sec, and 100sec stress with different number of channel stripes.

Gate Oxide Gate Oxide

Gate Oxide Gate Oxide Gate Oxide Gate Oxide

Source Source Source

Source DrainDrain

Drain Drain (a) Dual-Gate

(b) Single-Gate

Fig. 3-14 Schematic plot of structures for simulation.

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75

0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0

Electric Field (105V/cm)

X (μm) V_G=10V ; V_D=15V

Dual Gate

Source Drain

Fig.3-15 Electric field distribution in the poly-Si channel of dual-gate TFTs.

Electric Field (105V/cm)

0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0

X (μm)

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75

Single Gate V_G=10V ; V_D=15V

Source Drain

Fig. 3-16 Electric field distribution in the poly-Si channel of single-gate TFTs.

Chapter 4

The Lifetime of Poly-Si Thin-Film Transistors

4.1 Introduction

Lifetime is a convenient characteristic to monitor the device’s reliability. It is often used for the comparison of hot carrier immunity of different structures and technologies of devices. For this purpose, we usually apply high voltage to extract device’s lifetime. As we know, poly-Si TFTs have been widely used in many applications. However, to date, the lifetime prediction of poly-Si TFTs hasn’t been well-studied.

For MOSFETs, drain-avalanche-hot-carrier (DAHC) injection, based on impact ionization near the drain, causes the severest damage on the device’s characteristics.

The device’s degradation depends on the trap states generation, which is also proportional to the substrate current (Isub) [1]. Therefore, DAHC-induced Isub is used to monitor the device degradation and to predict the device lifetime. Under the severest DAHC stress, the empirical model for the lifetime prediction has been reported. It is found that threshold voltage shift (∆Vth), Gm degradation (∆Gm/Gm0), or On-current degradation (∆Ion/Ion0), can be expressed as [2][3]

∆V_th

(

∆Gm/Gm₀,or∆I_on/I_on0

)

=A×tⁿ --- (Eq. 4.1) The slope n, in the log-log plot depends on the hot-carrier injection conditions.

This tendency is valid for conventional MOSFETs.

However, for poly-Si TFTs, besides impact ionization, parasitic bipolar transistor (PBT) can also enhance the drain current to accelerate the device

degradation [4]. Due to the lack of body terminal in poly-Si TFT, holes generated during impact ionization will be recombined with electron as they flow to the channel, or they will accumulate in the substrate near the source. The injection of holes into the body will lowers the potential barriers between the source and the channel. When the voltage drop across the body-source junction is large enough, the parasitic bipolar transistors (PBT) will be turned on. The action of PBT will enhance the on-current and then increase the device degradation rate [5]. Therefore, PBT should be considered as predicting the lifetime of poly-Si TFTs. In this section, we used the conventional empirical extrapolating method of MOSFETs to predict the lifetime of poly-Si TFTs. However, there was apparent disagreement observed in low drain stress voltages (VDS). This is believed to be due to the action of PBT.

4.2 Experimental

Figure 4-1 and 4-2 show the process flow and cross-sectional view of the investigated poly-Si TFT. First, 500-nm-thick thermal oxide was grown on the Si wafers by furnace system to substitute for the glass substrate. Then, 100-nm-thick amorphous silicon layers were deposited on the thermal-oxidized layer in a low-pressure chemical vapor deposition (LPCVD) system by pyrolysis of silane (SiH4) gas source at 550°C. Next, a semi-Gaussian-shaped KrF excimer laser with wavelength of 248nm was performed for the phase transformation from amorphous to polycrystalline silicon at the laser energy density of 480mJ/cm² with substrate heating of 400°C under the chamber pressure of 10^-3Torr. Individual active regions were then patterned and defined. After an RCA cleaning procedure, a 100nm-thick TEOS oxide was deposited with TEOS and O2 gas source by PECVD at 350°C for the gate insulator. A 200-nm-thick poly-Si was deposited to serve as the gate electrode by

LPCVD. Then, gate electrode was patterned and the regions of source, drain, and gate were doped by a self-aligned phosphorous ion implantation at the dosage and energy of 5×10¹⁵ions/cm^-2 and 40keV. The dopant activation was performed by excimer laser annealing with laser energy density of 220mJ/cm², followed by a deposition of 400-nm-thick passivation oxide in a PECVD system at 350°C and the definition of contact holes. Finally, a 500-nm-thick Al electrode was deposited by thermal evaporation and patterned for metal pads. The transfer characteristics of the poly-Si TFT is shown in Fig. 4-3.

4.3 Results and Discussion

Impact ionization near the drain is a main mechanism to cause substantial trap states at the interface for MOSFETs under a hot carrier stress. From the empirical model, the Ion degradation can be expressed as

n on

on I A t

I = ×

∆ ₀ --- (Eq. 4.2)

The magnitude of degradation, A, which has physical meaning as the number of excess carrier generated by impact ionization, has been known to have the VDS

dependency:

A ∝ exp

(

−a /VDS

)

--- (Eq. 4.3)

where a is a constant. On the other hand, the peak substrate current (Isub) and the increase of trap states, which are also proportional to the number of electron-hole pairs generated by impact ionization, can be also expressed in the same dependency [6][7].

N it ∝ I_sub ∝ α ∝ exp

(

−^{c /E}

)

∝ exp

(

−c /VDS

)

∝ A^c/a --- (Eq. 4.4) where α is the impact ionization factor, c is a constant, and E is the local electric

field near the drain. Using (Eq. 4.2), (Eq. 4.3), and (Eq. 4.4), the lifetime (τ ) of the MOSFET under a certain criterion can be expressed as:

τ

∝ exp

(

b VDS

)

--- (Eq. 4.5)

where b is also a constant. Therefore, we will use this conventional empirical model to investigate the lifetime of poly-Si TFTs.

First, we define the worst case of hot carrier stress of poly-Si TFTs. It has been demonstrated that the worst-case hot carrier degradation for MOSFET is known to be under VG=1/2 VD [8]. However, due to the PBT action, the worst-case degradation for SOI-MOSFETs is VG≈Vth [9]. As we know, poly-Si TFTs is similar to SOI MOSFETs;

both of their body is floating. Therefore, we deduced that the worst-case degradation for poly-Si TFTs is also under VG≈Vth. Figure 4-4 shows the comparison of the ID

degradation under stress conditions of VG=1/2 VD and VG≈Vth with VDS=20V and 18V.

It is obviously shown that the VG≈Vth conditions cause severest damage of poly-Si TFTs. Therefore, the degradation of poly-Si under stress conditions of VG≈Vth, with VDS=10~20V and source grounded for 1000sec were investigated. Figure 4-5 shows the Ion variations as a function of stress time with various VDS. As can be seen, the slope n, in log-log plot depends on the VDS strongly. Obviously, two sets of slopes can be observed. The slopes for high VDS are almost equal to 0.5, which indicates that recombination-induced trap states dominate the device degradation [10]. However, the slopes for low VDS stress conditions are higher than that of high VDS stress conditions.

A similar tendency has been found in SOI MOSFETs [11][12]. However, the mechanism responsible for this phenomenon has not been well-studied before.

Figure 4-6 presents the lifetime (τ ) as function of the reciprocal VDS. The lifetime is defined as the time taken for 10% Ion degradation at VD=1V. We found that the experimental results agree with the empirical model only for high VDS stress

conditions. This indicates that impact ionization model only dominate the device degradation under high VDS stress conditions. Current and electric field near the drain is known to be the most important two factors of impact ionization. When VDS

increases, the two factors were then enhanced. Therefore, under high VDS the empirical model is valid for not only MOSFETs but also poly-Si TFTs.

However, there is a deviation under low VDS stress conditions. Moreover, the relationship between the magnitude of device degradation A and reciprocal VDS is show in Fig. 4-7. The agreement between the model and experimental results only can be found under high VDS. Therefore, this proves that the impact ionization model is unsuitable for the low VDS stress conditions.

Comparing the device structures between MOSFETs and poly-Si TFTs, the floating body is the main difference between them. For MOSFETs, the Isub generated by impact ionization in MOSFETs flowed to the body terminals. However, for poly-Si TFTs, the Isub will flow through the substrate toward the source to be recombined or accumulate in the substrate, and turn on the PBT. Moreover, under low VDS stress condition, the current and high electric field near the drain side is not high enough.

Therefore, the impact ionization is not the first order effect for the current multiplication. Therefore, we deduce that PBT action plays the main roles on the current enhancement to damage the device characteristics at low VDS. That is why the magnitude of device degradation (A) and lifetime (τ ) do not agree with the empirical impact ionization model under low VDS stress conditions.

So, when predicting the lifetime of poly-Si TFTs, the PBT phenomenon must be considered. Figure 4-8 shows the current generation in the poly-Si TFTs with a floating body. In this figure, the intrinsic drain current (ID) induces a hole current (Isub) due to impact ionization near the drain side, and the Isub, which flows to the source induces a bipolar electron current (Ie), can be expressed as:

( )

_D

sub M I

I = −1 --- (Eq. 4.6) The bipolar electron current (Ie) can be expressed as:

( )

sub

( )( )

D

e I M I

I = β+1 = β+1 −1 --- (Eq. 4.7) where β is the bipolar current gain, and M is the impact-ionization multiplication factor, which can be expressed as:

(

M ⁻¹

)

⁼

∫

^αdy --- (Eq. 4.8)

Then, Ie which injects into the channel will enlarge ID, and enhance impact ionization near the drain to generate higher Isub.

( )( )

derived and expressed as

( ) [ ( ) ( ) ]

is proportional to the reciprocal Isub. So, it can be expresses as:

τ

∝ 1

(

β+1

) (

^A0 M−1

)

^B0 --- (Eq. 4.12)

where A0 and B0 are constant. As can be seen, this form shows the lifetime prediction including both impact ionization and PBT effects.

Moreover, it has been proposed by using simulation method that the β varies with VDS [4]. The β decreases dramatically with increasing VDS [4]. This can be explained by the high current injection [4][13]. Therefore, under high VD stress condition, (M-1) is large and β is small, which can be neglected. Then, τ ∝

1/(M −1)^B0, which means that the impact ionization dominates. However, under low VD stress condition, β is large, whereas (M-1) is small. In this condition, the PBT action must be considered. That is why the lifetime prediction as shown in Fig. 4-6 did not agree with the conventional empirical model. Although further investigation is still needed, from this section, we can understand the lifetime prediction model more in poly-Si TFTs.

4.4 Summary

Lifetime of poly-Si TFTs has been investigated. It is found that lifetime extraction of poly-Si TFTs is not the same with that of MOSFETs. The worst-case of stress conditions is under VG≈Vth not VG=1/2 VD. Moreover, Ion degradation under both high and low VD of stress conditions has different phenomena. This is because impact ionization dominated under high VD. However, under low VD, the degradation mechanism is complicated; not only impact ionization but also parasitic BJT phenomenon must be considered.

References:

[1] C. M. Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Terrill, “Hot electron induced MOSFET degradation—model, monitor, and improvement,”

IEEE Trans. Electron Devices, vol. 32, no. 2, pp. 375-385, 1985.

[2] E. Takeda, and N. Suzuki, “An empirial model for device degradation due to hot-carrier injection,” IEEE Electron Device lett., vol. 4, no. 4, pp. 111-113, 1983.

[3] E. Takeda, N. Suzuki, and T. Hagiwara, “Device performance degradation due to hot-carrier injection at energies below the Si-SiO2 energy barrier,” in IEDM Tech.

Dig., pp. 396-399, 1983.

[4] M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora, and I.

Policicchio, “Floating body effects in polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 44, no. 12, pp. 2234-2241, Dec. 1997.

[5] G. A. Armstrong, S. D. Brotherton, and J. R. Ayres, “A comparison of the kink effect in polysilicon thin film transistors and silicon on insulator transistors,” Solid State Electronics, vol. 39, no. 9, pp. 1337-1346, Sept. 1996.

[6] T. Y. Chan, P. K. Ko, and C. Hu, “A simple method to characterize substrate current in MOSFET’s,” IEEE Electron Device lett., vol. 5, no. 12, pp. 505-507, 1984.

[7] E. Takeda, H. Kume, T. Toyade, and S. Asai, “Submicrometer MOSFET structure for minimizing hot-carrier generation,” IEEE Trans. Electron Devices, vol. 29, no.

4, pp. 611-617, 1982.

[8] P. H. Worelee, C. Juffermans, H. Lifka, W. Manders, F. M. Oude Lansink, G. M.

Paulzen, P. Sheridan, and A. Walker, “A half-micron CMOS technology using ultra-thin silicon on insulator,” in IEDM Tech. Dig., pp. 583-586, 1990.

[9] L. T. Su, H. Fang, J. E. Chung, and D. A. Antoniadis, “Hot-carrier effects in

fully-depleted SOI nMOSFETs,” in IEDM Tech. Dig., pp. 349-352, 1992.

[10] B. Doyle, M. Bourcerie, J. C. Marchetaux, and A. Boudou, “Interface state creation and charge trapping in the medium-to-high gate voltage range (Vd/2 ≥ Vg

[10] B. Doyle, M. Bourcerie, J. C. Marchetaux, and A. Boudou, “Interface state creation and charge trapping in the medium-to-high gate voltage range (Vd/2 ≥ Vg

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