Motivation

Metal-induced lateral crystallization process has been introduced by which the a-Si thin films could be crystallized at a low temperature of below 500 ^oC. However, the applications of Ni-mediated lateral crystallization of a-Si to poly-Si TFTs have a critical issue because the leakage current are mostly high [45]. The Ni defects induced leakage current is directly related to the lateral electrical field in the drain region in the off-state [46]. Much research related to overcoming the problems in MILC poly-Si TFTs has been carried out, and the general consensus is that the presence of Ni-silicide in the channel region is the cause of these problems. Several methods have been proposed to reduce the amount of undesired metal impurity [47]-[49]. However, these methods are complicated and need of extra process.

8

Accordingly, we propose a more simple method to reduce the Ni silicide contamination in the MILC region and expect the applicability of the method to fabricate poly-Si TFTs with high performance.

In this thesis, we fabricate the symmetric vertical-channel NSILC-VTFT device with unilateral crystallization. Thus, the MILC/MILC grain boundary (LLGB) in the middle of the channel can be eliminated. Besides, the devices can reduce the metal contaminations on source and drain region due to the metal seed window is separated from the drain metallurgical junction [45]. We also hope that grain filtering effect occurred on the NSILC process when the width of a-Si film pattern was narrowed.

Thus we can obtain the vertical channel region, which is composed of a single-orientated crystal. In addition, the NSILC-VTFTs which has the inherently own an effective dual gate structure and offset region. We hope that measured results shows the NSILC-VTFTs have high on-state current, high field effect mobility, steeper subthreshold swing, and low leakage current.

9

1.4 Organization of the Thesis

There are four chapters in this thesis. This thesis is organized as follows:

In Chapter 1, we introduce the development of thin-film transistors and comparison between poly-Si TFTs and a-Si TFTs. Some technique of manufacture the poly-Si TFTs are described in this chapter. Moreover, we also introduce the vertical channel thin-film transistors.

In Chapter 2, we describe the structure and the process of our vertical thin-film transistors. We also show the VTFTs cross-sectional photograph of TEM and optical microscopy photograph during different process time of MILC. Besides, the electrical parameters extraction are shown in the end of this chapter.

In Chapter 3, we discuss the electrical characteristic of VTFTs and the effect of post treatment. Then, we discuss the crystal filtering effect in the VTFTs and comparison between MILC-VTFTs and NSILC-VTFTs.

Finally, the main conclusions and future works are summarized in Chapter 4.

10

Fig. 1-1 Schematic of field-effect transistor.

Poly-Si gate Gate oxide

n

⁺

n

⁺

P-type substrate

Field oxide

Field oxide

e^-e^-e^-e^- e^-e^- e

-V

_g

> V

_t

Source Drain

Si Diamond structure a = 5.430 Å

NiSi

2

Fluorite structure a = 5.406 Å

Fig. 1-2 The crystalline structure of Si and NiSi

2

.

11

Fig. 1-3 Schematic equilibrium molar free-energy diagram for NiSi

2

in contact with a-Si and c-Si. [36]

into c-Si layer c-Si NiSi2

Growth of epitaxial c-Si

12

Chapter 2

Device Fabrication and Electrical Parameters Extraction

2.1 Fabrication of the vertical channel thin-film-transistor 2.1.1 Fabrication Process

The overall fabrication process flow of the vertical thin-film-transistors (VTFTs) is shown in Fig 2.1.

First of all, the 550-nm thick thermal oxide was grown on Si wafer as starting substrate. Then 200-nm thick poly-Si layer was deposited for gate by low-pressure chemical vapor deposition (LPCVD) system using SiH4 as source gas. The gate was implanted with phosphorous, the energy and the dose of the implantation were 40 keV and 5 × 10¹⁵ 𝑐𝑚⁻², respectively. Subsequently, the dopants were activated by furnace at 600 ^oC for 24 hours.

After the gate patterning, the oxide was overetched to about 80-nm to form the offset region. Then, the 15-nm thick layer of tetraethoxysilane (TEOS) oxide and 50-nm thick undoped amorphous Si (a-Si) layer were deposited consecutively as gate oxide and active region by LPCVD. The deposition pressure and temperature of a-Si film are 350 mTorr and 560 ^oC, respectively. After active region patterning, Ni-window mask pattern was form on the top of the TFTs using photoresist. The 10-nm Ni film was deposited by electron-beam evaporation system and then Ni film on the photoresist was removed by the lift-off process. Ni contacts with a-Si only in the seeding window;

other areas of wafers outside the seeding window are mostly free of Ni contamination.

We used two methods to complete the channel crystallization: MILC and NSILC.

The MILC-VTFTs were fabricated without Ni-silicidation process by rapid thermal annealing (RTA). In the NSILC-VTFTs, the Ni-silicidation was carried out at 450 ^oC for 30 s by RTA. And then, the unreacted Ni film was removed by H₂SO₄ / H₂O₂

13

solution at 120 ^oC for 10 min. Next, both devices were crystallized subsequently at 500

oC for 48 hours in N2 ambient.

Then, a 15-nm thick TEOS oxide was deposited and 15-keV, 5 × 10¹⁵ 𝑐𝑚⁻² As⁺ ion implantation to form self-aligned n⁺ S/D and n⁺ floating region. Then the dopants were activated by RTA at 750 ^oC for 30 s. The three-dimensional graph of the device structure is shown in Fig. 2-2.

2.1.2 Fabrication results

Fig. 2-3 and Fig. 2-4 show the cross-sectional transmission electron microscope (TEM) microphotograph of the NSILC-VTFTs and MILC-VTFTs. The integrity of the vertical poly-Si channel is verified by the transmission electron diffraction (TED) pattern inserted in TEM microphotograph. In the TEM images, the gate oxide and the poly-Si thickness in the channel are roughly 20-nm and 50-nm, respectively. The offset region between the gate and the S/D edges was achieved by wet-oxide overetched resulting in about 20-nm offset region. Fig. 2-5 displays the top-view schematic diagram of MILC-VTFTs with source, drain, bottom gate and Ni-window. And the schematic cross-sectional view and effective dual gate structure of MILC-VTFTs are shown in Fig. 2-6. The length of floating n⁺ region (Lf) is defined by the mask channel length, and the mask channel width (W_mask) is equal to the effective channel width. The effective channel length Leff is the vertical channel region, which is defined as 2 × the total thickness of the poly-Si gate, which equals 0.4 μm. Moreover, the equivalent dual-gate structure can reduce the peak lateral electrical field in the drain depletion region, significantly reducing the leakage current and increasing the Ion /I_off current ratio [1]-[2].

The Fig. 2-7 shows optical microscopy photograph of active pattern with the source, the drain, channels, bottom-gate and Ni-seeding window. The gate length is 1

14

μm, and the channel width is 2 μm. The optical micrograph of a sample heat treated for 3 h at 500 °C, as in Fig. 2-8(a), the crystallization was seen to proceed laterally from the Ni-window and the MILC distance was around 5.98 μm from the Ni-seeding window. And the crystallization was completed in 12 h as in Fig. 2-8(b), the whole active channel was crystallized by the MILC process. Three distinct regions are visible:

the rectangle with the brighter contrast was originally covered by Ni, which is MIC region. This is surrounded by the MILC region with the brightest contrast. And the darkest area in the out of MILC region is a-Si region. These results indicate that the active channel can be crystallized during the MILC process at 500 ^oC for 48 hours.

2.2 Method of Device Parameter Extraction

In this thesis, all of the electrical properties of proposed poly-Si TFTs were measured by semiconductor characterization system Keithley 4200. Many methods have been proposed to extract the characteristics of poly-Si TFT. In this section, extractions of various electrical parameters are introduced. These parameters include the subthreshold swing (S.S.), Filed-effect mobility (𝜇_𝑒𝑓𝑓), On-state current (Ion), and Off-state current (Ioff).

2.2.1 Determination of Subthreshold swing

Subthreshold swing (S.S.) is an important parameter to describe the control ability of gate toward the channel, reflecting the switch speed of the device. It is defined as the amount gate voltage required to increase/ decrease drain current by one-order of magnitude. In general, the S.S. should be independent on drain voltage and gate voltage. However, there are many non-ideal effects in MOSFETs and TFTs. The degradation of the S.S. with increasing drain voltage is due to short channel effect, avalanche multiplication, and punch through effect. Moreover, the subthreshold swing

15

is related to gate voltage which attributes the undesirable factor, such as interface states and gate oxide thickness.

In this thesis, the S.S. is defined as a quarter of gate voltage required to increase drain current by four-orders of magnitude.

S. S. ≡ 𝜕𝑉_𝐺

𝜕(𝑙𝑜𝑔𝐼_𝐷)= (𝑙𝑛10) 𝜕𝑉_𝐺

𝜕(𝑙𝑛𝐼_𝐷)

By neglecting the depletion capacitance in the active layer, Takashi Noguchi has reported that effective interface-trap-state-density (Nit) near the poly-Si/ SiO2 interface can be extracted from the subthreshold swing [3]-[5].

𝑁_𝑖𝑡 = [(𝑆. 𝑆.

𝑙𝑛10) (𝑞

𝑘𝑇) − 1](𝐶_𝑜𝑥 𝑞 )

2.2.2 Determination of Field Effect Mobility

Usually, the field effect mobility (𝜇_𝑒𝑓𝑓) is extracted from the maximum value of transconductance (g_m) at low drain voltage (V_DS = 0.1 V, V_GS-V_th >> V_DS ). The transfer characteristic of poly-Si TFTs is similar to traditional MOSFET, so the first order of I-V relation in the bulk Si MOSFETs can be applied to poly-Si TFTs. The drain current in linear region (VD < VG – Vth) can be approximated as the following equation: Therefore, the field-effect mobility is obtained by

𝜇_𝐹𝐸 = 𝐿

𝑊𝐶_𝑜𝑥𝑉_𝐷𝑆 𝑔_{𝑚,𝑚𝑎𝑥}

16

2.2.3 Determination of ON/ OFF current ratio

On/off current ratio is one of the most important parameters of poly-Si TFTs. An promising poly-Si TFT technique should not only provides high on-state current but also low off-state leakage current. For switching elements, as pixel cell, the off state is frequently operated in normal operation. Therefore, on/off current ratio is evidently a more appropriate evaluation parameter compared with on state current alone. The leakage current mechanism in the poly-Si TFTs is more complicated than single crystal device. For single crystal device, the channel film is composed of single crystalline and the leakage current is due to the tunneling of minority carrier from drain region to accumulation layer located in channel region. However, in poly-Si TFTs, the channel is composed of poly-Si grain, which has lots of inherence defects in the intra-grain and inter-grain site. And most of the density of states located within deep state close to the middle of the forbidden band-gap, and increase as the number of dangling bond increases. Thus, the leakage current due to trap-assisted tunneling and band-to-band tunneling is much larger in poly-Si TFTs than in the single crystal MOSFETs.

In this thesis, the on-state current is defined as the drain current when the gate voltage at 6V and drain voltage is 0.1V for n-channel TFT. The off-state current is defined as the minimum current when the drain voltage equals to 0.1V.

𝐼_𝑜𝑛

𝐼_𝑜𝑓𝑓 =𝐷𝑟𝑎𝑖𝑛 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑜𝑓 𝐼_𝐷𝑆−𝑉_𝐺𝑆 𝑝𝑙𝑜𝑡 𝑎𝑡 𝑉_𝐷𝑆=0.1 𝑉,𝑉_𝐺𝑆=6𝑉 𝑀𝑖𝑛𝑖𝑚𝑢𝑚 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑜𝑓 𝐼_𝐷𝑆−𝑉_𝐺𝑆 𝑝𝑙𝑜𝑡 𝑎𝑡 𝑉_𝐷𝑆=0.1 𝑉

17

Buried Oxide Poly-Si

(1) 550-nm thick buried oxide was grown and 200-nm a-Si was deposited.

Buried Oxide Poly-Si

Phosphorous implant

(2)

Phosphorous implantation

.

Buried Oxide n ⁺ poly-Si

(3) 600 ℃ annealing for 24 hours was used to activate the dopants.

18

Buried Oxide Poly-Si

Ni

Buried Oxide Poly-Si

(4) Dry etching the poly-Si and 80-nm thick buried oxide to define the gate pattern.

Buried Oxide Poly-Si

a-Si

(5) Deposit the 15-nm thick TEOS oxide and 50-nm thick a-Si as gate oxide and channel respective.

(6) Using photoresist to define the Ni-window and deposit 10-nm thick Ni.

19

Poly-Si

Buried Oxide Ni

(7)

The Ni film on the photoresist was removed by the lift-off process.

Poly-Si

Buried Oxide

NiSi

(8) The Ni-silicide was formed at 450 ℃ for 30 s by RTA.

Poly-Si

Buried Oxide

Poly-Si channel

(9) To crystallize the channel during MILC process (500 ℃, 48 h)

20

Poly-Si

Buried Oxide

n

⁺

source n

⁺

drain

n

⁺

floating region

(10) As⁺ ion Implantation to form n⁺ source/drain and n⁺ floating region.

Fig. 2-1 The schematic cross-section diagrams and key process flows of the devices.

Source

Gate

Drain

Buried Oxide

Drain

Vertical channel

Fig. 2-2 Device structure of the proposed VTFT.

21

n

⁺

floating region

Vertical Channel

n

+

poly-Si Gate

Fig. 2-3 The cross-sectional transmission electron microscope (TEM)

microphotograph and TED pattern of the NSILC-VTFTs.

22

Drain

Source

n

+

poly-Si Gate Vertical channel n

⁺

floating region

Oxide overetched

Gate

Gate Oxide

Vertical channel

Fig. 2-4 The cross-sectional transmission electron microscope (TEM)

microphotograph and TED pattern of the MILC-VTFTs.

23

(b)

Fig. 2-6 (a) The cross-sectional schematic diagram of MILC-VTFTs and (b) Effective dual gate structure of MILC-VTFTs.

Wet oxide

Fig. 2-5 The top-view schematic diagram of MILC-VTFTs with source, drain, bottom gate and Ni-window.

(a)

24

Ni-window

Poly-Si Gate

a-Si region

Fig. 2-7 Optical microscopy photograph of active pattern with the

source, the drain, channels, bottom-gate and Ni-seeding window.

25

(a)

(b)

Fig. 2-8 The OM micrographs of a sample heat treated for (a) 3 h and (b) 12 h

of heat treatment at 500

^o

C, and the whole active channel was crystallized by

the MILC process.

26

Chapter 3

Characteristics of Vertical Channel Low Temperature Nickel Induced Lateral Crystallization Poly-Si TFT

Poly-Si TFTs have attracted considerable interest due to their wide applications, such as driving pixels and peripheral circuits in AMOLEDs and system on panel (SOP).

The most widely employed methods for poly-Si formation are solid-phase crystallization (SPC), excimer laser annealing (ELA) and metal-induced lateral crystallization (MILC). The a-Si thin films could be crystallized at a low temperature of below 500 ^oC by MILC, and it has uniform poly-Si films and low-cost production.

However, there are many intra-grain defects in poly-Si and the Ni and NiSi₂ precipitates are trapped in poly-Si grain boundaries. Both Ni and NiSi2 act as trap sites for high leakage current at the junction boundary and as scattering sources that considerably reduce the filed-effect mobility. Therefore, Ni contamination inside the MILC poly-Si film should be reduced to improve the device performance.

In order to alleviate adverse effects to obtain high performance TFTs, plasma treatment and crystal filtering can be used to produce the uniform crystal orientation and enhance the device performance. Besides, several methods have been proposed to reduce the amount of undesired metal impurity [47]-[49]. But these methods are complicated and need extra process. Accordingly, we propose a more simple method to reduce the Ni and NiSi₂ contamination in the MILC region and expect the applicability of the method to fabricate poly-Si TFTs with high performance.

27

3.1 Effects of post treatment

It is well known that the grain boundaries exert a profound effect on device characteristic, because the charges trapped within grain boundaries and build up potential barriers to the flow of carrier subsequently. Moreover, the numerous intra-grain defects in poly-Si channel film also adversely influence on the device performance. Thus, poly-Si TFTs exhibit poor performance such as low mobility, large subthreshold swing, large threshold voltage, and large leakage current than the single-crystal counterparts. To obtain high performance poly-Si TFTs, both the grain enlargement techniques [1]-[2] and defect passivation processes have become increasingly important. In order to reduce the trap state densities in the poly-Si channel film, it can be performed by plasma treatment, including H2, O2, N2, and NH3 plasma [3]-[7]. Traditionally, H₂ plasma has been a very effective and popular method for passivation. However, it had been observed that the introduction of hydrogen would degrade the reliability due to the weak Si-H bonds. To attenuate the hot-carrier degradation and obtain comparable device performance, NH3 anneal and NH3 plasma passivation have been recently proposed, and the better hot-carrier reliability than using H2 plasma passivation has been realized.

In this thesis, the NH₃ plasma treatment was performed for 10 min at 300 ^oC with RF power of 50 W. The flow-rate was 100 sccm at pressure of 67 Pa. The typical transfer characteristic and the transconductance of NSILC-VTFTs and MILC-VTFTs with and without NH3 plasma treatment is shown in Fig. 3-1. The length of the floating region and channel width is 0.35 μm and 1 μm respectively.

Accordingly, the subthreshold swing (S.S.) and the effective interface trap-state density (N_it) of the NH₃ plasma-treated NSILC-VTFT are 224.1 mV/dec. and 2.98 × 10¹² 𝑐𝑚⁻², respectively, which are superior to 1206.9 mV/dec. and 20.8 × 10¹² 𝑐𝑚⁻² of the control NSILC-VTFT. And the S.S and the Nit of the plasma-treated

28

MILC-VTFT are 256.8 mV/dec. and 3.57 × 10¹² 𝑐𝑚⁻², respectively. Moreover, the field-effect mobility of NILC-VTFT and MILC-VTFT with NH3 plasma treatment for 10 min are 131.87 cm²/V-s and 147.39 cm²/V-s, respectively. It is evident that device characteristics are significantly improved by NH3 plasma passivation. Detailed device parameters such as field-effect mobility (μ_eff), subthreshold swing (S.S.), effective interface trap-state density (Nit), off-state current (Ioff), ON/OFF current ratio are summarized in Table 3-1. It has higher field mobility, higher ON/OFF current ratio, lower threshold voltage, and steeper subthreshold swing with NH3 plasma treatment.

The previous study had reported that the threshold voltage and subthreshold swing are related to the dangling-bond deep trap states. They have faster response to the plasma passivation. And the leakage current and field-effect mobility, which are related to strain-bond tail trap states of poly-Si channel, have slower improvement to plasma passivation [8]. NH₃ plasma passivation further improves the performance of these devices, suggesting that the NH3 plasma effectively passivated the dangling bonds at the grain boundary by the H and N radicals coupling and the nitrogen pile up at the SiO2/poly-Si interface resulting in the formation of strong Si-N bonds[6]-[8]. Moreover, the NH₃ plasma passivation reduces the barrier height (E_B) of the poly-Si grain boundary, the electrons can easily overcome EB, producing a high current and allowing the TFT to be easily turned on.

3.2 Crystal Filtering Effect

The poly-Si TFTs have attracted much attention for driving pixels and peripheral circuits in AMOLEDs, due to their higher carrier mobility than a-Si TFTs. However, the presence of poly-Si grain boundary defects in the channel region of TFTs drastically influences on the electrical characteristics [9]-[10]. Therefore, the control of the orientation of the Si crystal grains enables us to control the alignment of grain

29

boundaries. Thus, the electrical performance can be improved by reducing the grain boundary defects and the randomly oriented grain boundaries from the device area. In this section, we propose the VTFTs with various crystal filter widths and multichannel structure to improve the electrical characteristics by crystal filtering effect.

In this thesis, the devices can be divided into two groups, EW2 and EW1, according to their effective widths listed in Table 3-2. The top view optical microscope microphotographs of MILC-VTFTs with various widths of crystal filter are shown in Fig. 3.2. The effective width of EW2 and EW1 are 2 μm and 1 μm respectively. Both the devices of the floating region length (L_f) were fixed at 1 μm. In the group EW2, one with crystal filter width of 2 μm and a single-channel (designed “W2C1”), one with crystal filter width of 1 μm and two channels (designed “W1C2”), one with crystal filter width of 0.5 μm and four channels (designed “W0.5C4”), and the other with crystal filter width of 0.4 μm and five channels (designed “W0.4C5”). In the group EW1, one with crystal filter width of 1 μm and a single-channel (designed

“W1C1”), and another with crystal filter width of 0.5 μm and two-channels (designed

“W0.5C2”).

Fig. 3.3 shows the transfer characteristics of MILC-VTFTs with various widths of crystal filter. Compared with W2C1, W1C2, W0.5C4, W0.4C5 has better device performance than its counterparts. Moreover, the W0.5C2 also has the significant performance than other. These results indicate that the narrower the unit channel width is, the better the electrical performance is, including higher on-state current, steeper subthreshold swing, and lower off-state current. This is attributed to that lower probability of the channel region covers the grain boundary in narrower width devices and the channel region would have more uniform crystal growth direction than the unfiltered active layer of MILC-VTFT area. The narrower the widths of the crystal filters are, the more uniform the crystallographic orientation the MILC poly-Si is

30

[11]-[12]. In general, the c-Si grains grow toward the a-Si region with the migration of NiSi2 and the individual crystallites form networks in Ni-MILC process. Moreover, if the NiSi₂ layer at the front of c-Si grain meets other crystal grains crystallized by the MILC process. Subsequently, the NiSi2 cannot migrate through the c-Si anymore because there is no difference of chemical potential driving force for the phase transformation between the two c-Si grains [13]. Therefore, the captured NiSi2 would increase silicide contaminations in the MILC region. For the crystal filtering method, there are few crystal Si grains, which has growth direction parallel to the crystal filter, can pass through the filter. Thus, the crystallized Si grains have longer grain lengths, similar crystal orientation and dense microstructure could be selected through crystal filter [14]-[15]. Therefore, the narrower crystal filter width has better grain crystallization, less intra-grain defects, less grain boundaries defects and NiSi2

contaminations in the poly-Si channel. Hence, the device performance, including higher on-state current, steeper subthreshold swing, lower off-state current, will be

contaminations in the poly-Si channel. Hence, the device performance, including higher on-state current, steeper subthreshold swing, lower off-state current, will be

在文檔中 鎳金屬誘發側向結晶垂直通道低溫複晶矽薄膜電晶體之研究 (頁 21-0)