Determination of On/Off Current Ratio

On/off current ratio is one of the most important parameters of poly-Si TFTs. An promising poly-Si TFT technique should not only provides high on-state current but also low off-state leakage current. For switching elements, as pixel cell, the off state is frequently operated in normal operation. Therefore, on/off current ratio is evidently a more appropriate evaluation parameter compared with on state current alone. The leakage current mechanism in the poly-Si TFTs is more complicated than single crystal device. For single crystal device, the channel film is composed of single crystalline and the leakage current is due to the tunneling of minority carrier from drain region to accumulation layer located in channel region. However, in poly-Si TFTs, the channel is composed of poly-Si grain, which has lots of inherence defects in the intra-grain and inter-grain site. And most of the density of states located within deep state close to the middle of the forbidden band-gap, and increase as the number of dangling bond increases. Thus, the leakage current due to trap-assisted tunneling and band-to-band tunneling is much larger in poly-Si TFTs than in the single crystal MOSFETs.

In this thesis, the on-state current is defined as the drain current when the gate voltage at 6V and drain voltage is 0.1V for n-channel TFT. The off-state current is defined as the minimum current when the drain voltage equals to 0.1V.

𝐼_𝑜𝑛

𝐼_𝑜𝑓𝑓 =𝐷𝑟𝑎𝑖𝑛 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑜𝑓 𝐼_𝐷𝑆−𝑉_𝐺𝑆 𝑝𝑙𝑜𝑡 𝑎𝑡 𝑉_𝐷𝑆=0.1 𝑉,𝑉_𝐺𝑆=6𝑉 𝑀𝑖𝑛𝑖𝑚𝑢𝑚 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑜𝑓 𝐼_𝐷𝑆−𝑉_𝐺𝑆 𝑝𝑙𝑜𝑡 𝑎𝑡 𝑉_𝐷𝑆=0.1 𝑉

17

Buried Oxide Poly-Si

(1) 550-nm thick buried oxide was grown and 200-nm a-Si was deposited.

Buried Oxide Poly-Si

Phosphorous implant

(2)

Phosphorous implantation

.

Buried Oxide n ⁺ poly-Si

(3) 600 ℃ annealing for 24 hours was used to activate the dopants.

18

Buried Oxide Poly-Si

Ni

Buried Oxide Poly-Si

(4) Dry etching the poly-Si and 80-nm thick buried oxide to define the gate pattern.

Buried Oxide Poly-Si

a-Si

(5) Deposit the 15-nm thick TEOS oxide and 50-nm thick a-Si as gate oxide and channel respective.

(6) Using photoresist to define the Ni-window and deposit 10-nm thick Ni.

19

Poly-Si

Buried Oxide Ni

(7)

The Ni film on the photoresist was removed by the lift-off process.

Poly-Si

Buried Oxide

NiSi

(8) The Ni-silicide was formed at 450 ℃ for 30 s by RTA.

Poly-Si

Buried Oxide

Poly-Si channel

(9) To crystallize the channel during MILC process (500 ℃, 48 h)

20

Poly-Si

Buried Oxide

n

⁺

source n

⁺

drain

n

⁺

floating region

(10) As⁺ ion Implantation to form n⁺ source/drain and n⁺ floating region.

Fig. 2-1 The schematic cross-section diagrams and key process flows of the devices.

Source

Gate

Drain

Buried Oxide

Drain

Vertical channel

Fig. 2-2 Device structure of the proposed VTFT.

21

n

⁺

floating region

Vertical Channel

n

+

poly-Si Gate

Fig. 2-3 The cross-sectional transmission electron microscope (TEM)

microphotograph and TED pattern of the NSILC-VTFTs.

22

Drain

Source

n

+

poly-Si Gate Vertical channel n

⁺

floating region

Oxide overetched

Gate

Gate Oxide

Vertical channel

Fig. 2-4 The cross-sectional transmission electron microscope (TEM)

microphotograph and TED pattern of the MILC-VTFTs.

23

(b)

Fig. 2-6 (a) The cross-sectional schematic diagram of MILC-VTFTs and (b) Effective dual gate structure of MILC-VTFTs.

Wet oxide

Fig. 2-5 The top-view schematic diagram of MILC-VTFTs with source, drain, bottom gate and Ni-window.

(a)

24

Ni-window

Poly-Si Gate

a-Si region

Fig. 2-7 Optical microscopy photograph of active pattern with the

source, the drain, channels, bottom-gate and Ni-seeding window.

25

(a)

(b)

Fig. 2-8 The OM micrographs of a sample heat treated for (a) 3 h and (b) 12 h

of heat treatment at 500

^o

C, and the whole active channel was crystallized by

the MILC process.

26

Chapter 3

Characteristics of Vertical Channel Low Temperature Nickel Induced Lateral Crystallization Poly-Si TFT

Poly-Si TFTs have attracted considerable interest due to their wide applications, such as driving pixels and peripheral circuits in AMOLEDs and system on panel (SOP).

The most widely employed methods for poly-Si formation are solid-phase crystallization (SPC), excimer laser annealing (ELA) and metal-induced lateral crystallization (MILC). The a-Si thin films could be crystallized at a low temperature of below 500 ^oC by MILC, and it has uniform poly-Si films and low-cost production.

However, there are many intra-grain defects in poly-Si and the Ni and NiSi₂ precipitates are trapped in poly-Si grain boundaries. Both Ni and NiSi2 act as trap sites for high leakage current at the junction boundary and as scattering sources that considerably reduce the filed-effect mobility. Therefore, Ni contamination inside the MILC poly-Si film should be reduced to improve the device performance.

In order to alleviate adverse effects to obtain high performance TFTs, plasma treatment and crystal filtering can be used to produce the uniform crystal orientation and enhance the device performance. Besides, several methods have been proposed to reduce the amount of undesired metal impurity [47]-[49]. But these methods are complicated and need extra process. Accordingly, we propose a more simple method to reduce the Ni and NiSi₂ contamination in the MILC region and expect the applicability of the method to fabricate poly-Si TFTs with high performance.

27

3.1 Effects of post treatment

It is well known that the grain boundaries exert a profound effect on device characteristic, because the charges trapped within grain boundaries and build up potential barriers to the flow of carrier subsequently. Moreover, the numerous intra-grain defects in poly-Si channel film also adversely influence on the device performance. Thus, poly-Si TFTs exhibit poor performance such as low mobility, large subthreshold swing, large threshold voltage, and large leakage current than the single-crystal counterparts. To obtain high performance poly-Si TFTs, both the grain enlargement techniques [1]-[2] and defect passivation processes have become increasingly important. In order to reduce the trap state densities in the poly-Si channel film, it can be performed by plasma treatment, including H2, O2, N2, and NH3 plasma [3]-[7]. Traditionally, H₂ plasma has been a very effective and popular method for passivation. However, it had been observed that the introduction of hydrogen would degrade the reliability due to the weak Si-H bonds. To attenuate the hot-carrier degradation and obtain comparable device performance, NH3 anneal and NH3 plasma passivation have been recently proposed, and the better hot-carrier reliability than using H2 plasma passivation has been realized.

In this thesis, the NH₃ plasma treatment was performed for 10 min at 300 ^oC with RF power of 50 W. The flow-rate was 100 sccm at pressure of 67 Pa. The typical transfer characteristic and the transconductance of NSILC-VTFTs and MILC-VTFTs with and without NH3 plasma treatment is shown in Fig. 3-1. The length of the floating region and channel width is 0.35 μm and 1 μm respectively.

Accordingly, the subthreshold swing (S.S.) and the effective interface trap-state density (N_it) of the NH₃ plasma-treated NSILC-VTFT are 224.1 mV/dec. and 2.98 × 10¹² 𝑐𝑚⁻², respectively, which are superior to 1206.9 mV/dec. and 20.8 × 10¹² 𝑐𝑚⁻² of the control NSILC-VTFT. And the S.S and the Nit of the plasma-treated

28

MILC-VTFT are 256.8 mV/dec. and 3.57 × 10¹² 𝑐𝑚⁻², respectively. Moreover, the field-effect mobility of NILC-VTFT and MILC-VTFT with NH3 plasma treatment for 10 min are 131.87 cm²/V-s and 147.39 cm²/V-s, respectively. It is evident that device characteristics are significantly improved by NH3 plasma passivation. Detailed device parameters such as field-effect mobility (μ_eff), subthreshold swing (S.S.), effective interface trap-state density (Nit), off-state current (Ioff), ON/OFF current ratio are summarized in Table 3-1. It has higher field mobility, higher ON/OFF current ratio, lower threshold voltage, and steeper subthreshold swing with NH3 plasma treatment.

The previous study had reported that the threshold voltage and subthreshold swing are related to the dangling-bond deep trap states. They have faster response to the plasma passivation. And the leakage current and field-effect mobility, which are related to strain-bond tail trap states of poly-Si channel, have slower improvement to plasma passivation [8]. NH₃ plasma passivation further improves the performance of these devices, suggesting that the NH3 plasma effectively passivated the dangling bonds at the grain boundary by the H and N radicals coupling and the nitrogen pile up at the SiO2/poly-Si interface resulting in the formation of strong Si-N bonds[6]-[8]. Moreover, the NH₃ plasma passivation reduces the barrier height (E_B) of the poly-Si grain boundary, the electrons can easily overcome EB, producing a high current and allowing the TFT to be easily turned on.

3.2 Crystal Filtering Effect

The poly-Si TFTs have attracted much attention for driving pixels and peripheral circuits in AMOLEDs, due to their higher carrier mobility than a-Si TFTs. However, the presence of poly-Si grain boundary defects in the channel region of TFTs drastically influences on the electrical characteristics [9]-[10]. Therefore, the control of the orientation of the Si crystal grains enables us to control the alignment of grain

29

boundaries. Thus, the electrical performance can be improved by reducing the grain boundary defects and the randomly oriented grain boundaries from the device area. In this section, we propose the VTFTs with various crystal filter widths and multichannel structure to improve the electrical characteristics by crystal filtering effect.

In this thesis, the devices can be divided into two groups, EW2 and EW1, according to their effective widths listed in Table 3-2. The top view optical microscope microphotographs of MILC-VTFTs with various widths of crystal filter are shown in Fig. 3.2. The effective width of EW2 and EW1 are 2 μm and 1 μm respectively. Both the devices of the floating region length (L_f) were fixed at 1 μm. In the group EW2, one with crystal filter width of 2 μm and a single-channel (designed “W2C1”), one with crystal filter width of 1 μm and two channels (designed “W1C2”), one with crystal filter width of 0.5 μm and four channels (designed “W0.5C4”), and the other with crystal filter width of 0.4 μm and five channels (designed “W0.4C5”). In the group EW1, one with crystal filter width of 1 μm and a single-channel (designed

“W1C1”), and another with crystal filter width of 0.5 μm and two-channels (designed

“W0.5C2”).

Fig. 3.3 shows the transfer characteristics of MILC-VTFTs with various widths of crystal filter. Compared with W2C1, W1C2, W0.5C4, W0.4C5 has better device performance than its counterparts. Moreover, the W0.5C2 also has the significant performance than other. These results indicate that the narrower the unit channel width is, the better the electrical performance is, including higher on-state current, steeper subthreshold swing, and lower off-state current. This is attributed to that lower probability of the channel region covers the grain boundary in narrower width devices and the channel region would have more uniform crystal growth direction than the unfiltered active layer of MILC-VTFT area. The narrower the widths of the crystal filters are, the more uniform the crystallographic orientation the MILC poly-Si is

30

[11]-[12]. In general, the c-Si grains grow toward the a-Si region with the migration of NiSi2 and the individual crystallites form networks in Ni-MILC process. Moreover, if the NiSi₂ layer at the front of c-Si grain meets other crystal grains crystallized by the MILC process. Subsequently, the NiSi2 cannot migrate through the c-Si anymore because there is no difference of chemical potential driving force for the phase transformation between the two c-Si grains [13]. Therefore, the captured NiSi2 would increase silicide contaminations in the MILC region. For the crystal filtering method, there are few crystal Si grains, which has growth direction parallel to the crystal filter, can pass through the filter. Thus, the crystallized Si grains have longer grain lengths, similar crystal orientation and dense microstructure could be selected through crystal filter [14]-[15]. Therefore, the narrower crystal filter width has better grain crystallization, less intra-grain defects, less grain boundaries defects and NiSi2

contaminations in the poly-Si channel. Hence, the device performance, including higher on-state current, steeper subthreshold swing, lower off-state current, will be improved by reducing the crystal filter width.

In order to further confirm the crystal filter effect is correct, we measured more than 20 devices to determine the statistical average values of on-state current (I_on), off-state current (Ioff ), subthreshold swing (S.S.), and transconductance (Gm) of group EW2 and EW1, shown in Fig. 3-4 – Fig. 3-11. Based on the statistical result, the narrower crystal filter width also has higher Ion, lower Ioff, steeper S.S., and higher Gm

than others wider crystal filter width. The statistical average values of some important parameters of all devices are summarized in Table 3-3. The W0.4C5 also has the highest field-effect mobility (μ_FE) as 87.5 cm²/V·s in the group EW2. And the W0.5C2 has the best field-effect mobility as 96.3 cm²/V·s in all devices. These results were similar to previous reports, indicating that the poly-Si grain lateral length increase as the channel width declines and the grain boundary defects of poly-Si would be reduced

31

to increase the mobility.

In addition, the longitudinal grains and their boundaries are parallel to the direction of carrier flow in the channel. The wide channel devices with grain boundaries traversing from source to drain provide extra current paths and cause punchthrough. However, the VTFTs inherently own an effective dual gate structure and the offset region, constructed by self-aligned oxide overetching. The previous study had reported that the OFF-state currents can be improved by increasing the oxide overetching depth and equivalent dual-gate structure [16]. This improvement on leakage current originates from reducing the lateral electrical field in the drain depletion region [17]-[20]. Thus, the OFF-state current of these device can be reduced below 1 pA/ μm.

3.3 Compare NSILC-VTFT with MILC-VTFT

According to the previous report [21], the excess Ni accumulation in the middle of the n+ floating region is found in the MILC-VTFTs, but it is not found in the NSILC-VTFTs. The Ni and NiSi₂ precipitates trapped in the grain boundary would act as trap sites which increase the leakage current and degrade the field-effect mobility.

In this section, we focus on discussing the different electrical characteristics between NSILC-VTFTs and MILC-VTFTs. Fig. 3-12 –Fig. 3-15 show the on-state current distribution, off-state current distribution, subthreshold swing distribution, and transconductance distribution of the NSILC-VTFTs and MILC-VTFTs with 1 μm of length of n⁺ floating region and channel width from 0.35 μm to 1 μm, respectively. We can observe that the electrical performance of NSILC-VTFTs and MILC-VTFTs seems to be no significantly difference. No matter what size of device we choose, we still have the same conclusion: There are no difference between NSILC-VTFTs and MILC-VTFTs.

32

This observation can be possibly ascribed to the following explanations. In this work, we used the unilateral crystallization method to complete the channel crystallized. Therefore, there is no excess Ni accumulation found in MILC-VTFTs and NSILC-VTFTs. And the MILC/MILC grain boundary in the middle of the channel can be eliminated. If the Ni content is provided by an appropriate amount to complete the channel crystallization, even MILC-VTFTs will be no excess Ni remaining in the channel. Therefore, the NSILC-VTFTs with Ni-silicided seeding window to limit the Ni source is not able to further improve the device characteristics. Nevertheless, the leakage current still can be suppressed by the dual-gate structure and offset region due to reducing the lateral electrical field in the drain depletion region.

Moreover, as channel widths decrease, the I_off suppresses and the G_m, S.S. and I_on enhances. These results reflect the crystal filtering once more. The average values of some important parameters are summarized in the Table 3-4. The narrower the widths of the crystal filters are, the more uniform the crystallographic orientation the MILC poly-Si is. Thus, the high performance device can be achieved by reducing the channel widths.

Although the narrower the channel width is the better the electrical performance, the on-state current would be degrade due to the W/L factor reducing. In order to overcome this problem, we proposed a layout which given high performance VTFTs.

The design of wide devices usually involves the breakdown of a wide transistor into a number of smaller transistors in parallel. In this experiment, we fabricated the multiple channels structure, which unit channel width of 0.35 μm. Fig. 3-16 shows the transfer characteristics of a MILC-VTFT with unit crystal width of 0.35 μm under various channel number. These results indicate that the multiple channel and crystal filtering effect can significant improve the on-state current, while maintaining the high performance of VTFTs. When the channel numbers are increased, the S.S. still remains

33

better performance about 300 mV/dec.. Moreover, the off-state current can significantly be reduced with both the equivalent dual-gate structure and offset region, and the on-state current and G_m can evidently be improved by multiple channels. In order to further verify the result is correct, more than 20 devices are measured to obtain the statistics. The average values of some important parameters such as I_on, I_off, S.S., Gm and their standard deviations with unit crystal width of 0.35 μm for various channel number are shown in Fig. 3-17- Fig. 3-20. As a result, the combination of narrower crystal width and multiple channels can successfully further optimize electrical characteristics of poly-Si TFTs, owning to the elimination of grain boundaries and defects.

34

Fig. 3-1 The typical transfer characteristic and the field-effect mobility of

(a) NSILC-VTFTs and (b) MILC-VTFTs with and without NH

₃

plasma.

35

Condition S.S.

(mV/dec.)

𝝁_𝑭𝑬 (cm²/V∙s)

Nit (10¹² cm^-2)

Ion

(μA)

Ioff

(pA)

Ion/Ioff

(×10⁷)

NSILC-VTFTs

No-plasma 1206. 9 100.42 20.8 3.30 0.162 2.03

NH3 10 min 224.1 131.87 2.98 5.27 0.041 12.8

MILC-VTFTs

No-plasma 1341.4 75.67 21.0 2.47 0.760 0.295

NH₃ 10 min 256.8 147.39 3.57 6.49 0.076 8.51

Table 3-1 Characteristics of poly-Si TFTs with and without plasma

treatment. All parameters are extracted at V

d

= 0.1 V. W/L = 0.35 μm/ 1 μm

36

Group Device

Unit channel Total

channel width

width number

EW 2

W2C1 2 1

2 μm

W1C2 1 2

W0.5C4 0.5 4

W0.4C5 0.4 5

EW 1

W1C1 1 1

1 μm

W0.5C2 0.5 2

Table 3-2 The width and number of unit channel in the devices.

37

W2C1 W 1C2

W0.5C4 W0.4C5

W1C1 W0.5C2

(b)

Fig. 3-2 The top view optical microscope microphotograph of MILC-VTFTs with various widths of crystal filter. (a) Total width = 2 μm (b) Total width =1μm

(a)

38

(b) Effective widths = 1 μm

Fig. 3-3 The transfer characteristics of MILC-VTFTs with various widths

of crystal filter. (a) Effective widths = 2 μm (b) Effective widths = 1 μm

39

Fig. 3-4 The statistical average values of on-state current of group EW2.

0

Fig. 3-5 The statistical average values of off-state current of group EW2.

40

Fig. 3-6 The statistical average values of subthreshold swing of group EW2.

0

Fig. 3-7 The statistical average values of transconductance of group EW2.

41

Fig. 3-8 The statistical average values of on-state current of group EW1.

0

Fig. 3-9 The statistical average values of off-state current of group EW1.

42

Fig. 3-10 The statistical average values of subthreshold swing of group EW1.

0

Fig. 3-11 The statistical average values of transconductance of group

EW1.

43

MILC-VTFT W2C1 W1C2 W0.5C4 W0.4C5 W1C1 W0.5C2

S.S. (mV/dec.) 428.67 360.97 331.88 303.66 379.85 310.03 μ

_FE

(cm

²

/V-s) 61.1 77.2 80.3 87.5 83.0 96.3

I

on

(μA) 10.56 13.46 14.98 19.17 9.88 10.57 I

^off

(pA) 2.03 1.25 1.07 0.92 0.66 0.48

I

^on

/ I

^off (×

10

⁷)

0.52 1.08 1.4 2.08 1.5 2.2

Table 3-3 The statistical average value of some parameters of EW2 and EW1.

44

Fig. 3-13 Comparison the off-state current distribution of NSILC-VTFTs and MILC-VTFTs with various channel width.

Fig. 3-12 Comparison the on-state current distribution of NSILC-VTFTs and MILC-VTFTs with various channel width.

-5

45

Fig. 3-15 Comparison the transconductance distribution of NSILC-VTFTs and MILC-VTFTs with various channel width.

Fig. 3-14 Comparison the subthreshold swing distribution of NSILC-VTFTs

and MILC-VTFTs with various channel width.

46 Condition

Parameter

W = 0.35 μm W =0.5 μm W = 1 μm

NSILC-TFTs

MILC-V TFTs

NSILC-T FTs

MILC-V TFTs

NSILC-T FTs

MILC-V TFTs S.S.

(mV/dec.)

295.94 298.81 324.80 317.10 366.92 360.66

μFE (cm²/V-s) 108.68 106.16 103.52 104.41 90.11 88.05

I_on (μA) 4.83 4.66 7.14 6.18 10.64 10.03 I_off (pA) 0.12 0.17 0.82 1.05 1.15 1.41

I_on/ I_off (×

10

⁷)

4.03 2.74 0.87 0.59 0.93 0.71

Table 3-4 Comparison the statistical average value of NSILC-VTFTs and

MILC-VTFTs with various channel width.

47

Fig. 3-16 The transfer characteristics of a MILC-VTFT with unit crystal width of 0.35 μm under various channel number.

1 channel 2 channels 5 channels 10 channels

-4 -3 -2 -1 0 1 2 3 4 5 6 10

^-14

10

^-13

10

^-12

10

^-11

10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

Drain curre nt I

DS

(A)

Gate voltage V

G

(V)

MILC-VTFTs Lf = 1 ^m VDS = 0.1 V

NH₃ plasma 10 min

Unit channel width = 0.35m

48

49

Fig. 3-20 The transconductance distribution of NSILC-VTFTs and

MILC-VTFT with unit crystal width of 0.35 μm under various channel

50

Chapter 4

Conclusions and Future Works 4.1 Conclusions

In this thesis, for the first time, we have investigated the characteristic of vertical channel poly-Si thin-film transistors fabricated by MILC with crystal filtering technique. For crystal filtering technique, the narrower crystal filter width has better grain crystallization and less intra-grain, less grain boundaries defects and NiSi₂ contaminations in the poly-Si channel. This is attributed to the lower probability of the channel region to cover the grain boundary in narrower width devices and the channel region would have more uniform crystal growth direction than the unfiltered active layer of MILC-VTFT area. The device performance including higher on-state current, steeper subthreshold swing, lower off-state current will be improved by reducing the crystal filter width.

In this thesis, we also observe that the electrical performance of NSILC-VTFTs and MILC-VTFTs seems to be no significantly difference. In this work, we used the unilateral crystallization method to complete the channel crystallized. Therefore, the MILC/MILC grain boundary in the middle of the channel can be eliminated. Once the Ni content is provided by an appropriate amount to complete the channel crystallized, even MILC-VTFTs will be no excess Ni remaining in the channel. Therefore, the NSILC-VTFTs with Ni-silicided seeding window to limited the Ni source is not able to further improve the device characteristics. Besides, the leakage current still can be suppressed by the dual-gate structure and offset region due to reducing the lateral electrical field in the drain depletion region. Thus, the OFF-state current of these device can be reduced below 1 pA/ μm.

51

4.2 Future works

There are some interesting and important topics that are suggested for the future work. First of all, MILC process is used to crystallize the a-Si layer in this thesis. The on-state current limitation results from the large S/D parasitic series resistance and contact resistance, which remain problems for device scaling and reduce device performance. To decrease the parasitic resistance of the poly-Si TFTs, the fully Ni-salicided S/D and n⁺ floating region is a technology to solve this problem.

Second, lower the gate height to achieve the short-channel device, which can overcome the limit of photolithography. Different gate height including 150nm, 100nm can be executed. Thus, the channel length of device can be scaled down below the limitation of I-line stepper. Besides, the lower the gate height, the easier it is to form the spacer and Ni-silicide.

Third, the reliability mechanisms of VTFTs by MILC crystallization method, such as hot carrier stress, NBTI and PBTI can be studied. And we can not only change the material of channel layer to a-Ge or III-V compound material but also change the gate dielectric layer to high-k insulators, such as Al2O3, Ta2O5 or HfO2.

Moreover, the vertical channel structure can be applied by as a memory device.

This idea is shown in Fig. 4-1. This double-gate SONOS-type TFT memory is suitable for NAND flash memory, due to simple fabrication process, multi-bit per cell and

This idea is shown in Fig. 4-1. This double-gate SONOS-type TFT memory is suitable for NAND flash memory, due to simple fabrication process, multi-bit per cell and

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