2.1 Introduction
Multi-phase clocks are usually generated by multi-phase clock generators. The clock generators could be identified as two classifications roughly. One of the classifications is the phase-locked loop. It generates multi-phase clocks by the voltage-controlled oscilla-tor. Another classification is the delay-locked loop. It generates multi-phase clocks by the voltage-controlled delay line. The voltage-controlled oscillator and the voltage-controlled delay line could be constructed by many different components with different methods. For example, the traveling wave principle could be used in the voltage-controlled oscillator design [15] [16] [17]. Its advantages are accurate high frequency signal generation, adia-batic operation, and good phase noise properties. In CMOS techniques, the most popular design methods of the voltage-controlled oscillator and the voltage-controlled delay line are cascading delay cells as a ring or a string [18] [19] [20].
In this chapter, the architectures, operation principles, analysis, and limitations of the phase-locked loops and the delay-locked loops with delay cell based voltage-controlled oscillators and voltage-controlled delay lines are introduced. The methods which could increase the number of output phases of the clock generators and improve the output phase quality are collected and discussed. Finally, the cause of jitter in clock generators is introduced.
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2.2 Phase-Locked Loop and Delay-Locked Loop
Fig. 2.1 shows the two different architectures of delay cell based multi-phase clock gen-erators, phase-locked loop and delay-locked loop. The basic operation concepts of the two architectures are very similar. They adjust their output phases to follow the input reference clocks.
In the phase-locked loop shown in Fig. 2.1(a), the voltage-controlled oscillator gen-erates multi-phase clocks at each output node of the delay cells with the same delay time. The phase-locked loop is used to control the oscillation frequency of the voltage-controlled oscillator. The phase detector compares the phase difference between the put phase of the voltage-controlled oscillator and the input reference clock, and then out-puts the error message about the phase difference. The charge-pump circuit receives the error message and then adjusts its output, control voltage, to increase or decrease the op-eration frequency of the voltage-controlled oscillator. The output of the charge-pump cir-cuit would be filtered by a low-pass filter to filter the high-frequency noise. Because the voltage-controlled oscillator outputs phases by frequency integration, the phase-locked loop is a high-order control system. The transfer function of the system includes two poles at origin. The first pole is caused by the characteristic of the voltage-controlled os-cillator. Another pole is caused by the loop filter. In order to cancel the effect of the two poles, the transfer function should include a zero for the stability of the loop system [21].
This zero could be produced by a resistor and a capacitor with serial connection in the loop filter. However, due to the zero, high frequency attenuation of the loop filter is not enough to filter the high frequency noise. In order to solve this problem, another capacitor is placed in parallel. Finally, the loop system becomes a third-order system, thus the phase margin and the stability of the loop become critical issues. By setting the capacitance of the additional capacitor is 1/10 times to 1/15 times of another capacitor. The loop system could be approximated to a second-order system.
The classification of high-order transfer function would produce more complex prob-lems. For example, the process variation would change the position of the zero, thus the stability of the system would be destroyed [22] [23]. However, the voltage-controlled os-cillator provides many advantages. First, because the whole loop is a low-pass filter, the
Reference Clock
Phase Detector
Charge
Pump Filter
Loop Voltage−Controlled Oscillator
1 2 3 4 5 N−1 N
VSS
(a)
Reference Clock
Phase Detector
Charge
Pump Filter
Loop Voltage−Controlled Delay Line
1 2 3 4 5 N−1 N
VSS
(b)
Figure 2.1: Block diagrams of delay cell based multi-phase clock generators. (a) phase-locked loop, (b) delay-phase-locked loop.
jitter of the input reference clock would not affect the output clocks of the system directly.
Second, the output frequency could be the multiple of the frequency of the input reference clock by using a frequency divider in the loop system. That is why the phase-locked loop is widely used in clock generation systems.
The delay-locked loop shown in Fig. 2.1(b) is only used in the fixed frequency sys-tems. The voltage-controlled delay line generates multi-phase clocks at each output node of the delay cells with the same delay time. The delay-locked loop is used to control the delay time of the voltage-controlled delay line. The phase detector compares the phase difference between the output phase of the voltage-controlled delay line and the input reference clock, and then outputs the error message about phase difference. The charge-pump circuit receives the error message and then adjusts its output, control voltage, to increase or decrease the delay time of the voltage-controlled delay line. The output of the charge-pump circuit would be filtered by a low-pass filter to filter the high-frequency noise. The voltage-controlled delay line is a simple delay gain element and has not the function of frequency integration as voltage-controlled oscillators. There is no necessary to add a zero in the loop system for stability. Therefore, the loop filter could be imple-mented by a simple integrator. The loop system must a very stable system, because the effect factors are tail away. That also means the design of delay-locked loops would be easier than the design of phase-locked loops. The detail analysis of phase-locked loops and delay-locked loops is described in Appendix A.
The major difference of phase-locked loops and delay-locked loops is the response when jitter occurs. In general, phase-locked loops have higher sensitivity of power supply noise and substrate noise, when those two systems are operated in the same frequency [24].
The operation frequency of voltage-controlled oscillators would be varied, when the voltages of power supply and substrate are changed by noise. The frequency error would become phase error by the frequency integration effect. The amount of phase error accu-mulation would be eliminated slowly by the loop. If the bandwidth of the loop is larger, the behavior of elimination would be faster. Otherwise, if the bandwidth is narrower, the behavior would be slower. If the supply voltage is varied in the delay-locked loop, the de-lay time would be affected at the moment when the noise occurs. The delay-locked loop