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Student : Ju-Ming Chou
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Advisor : Jieh-Tsorng Wu
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A Dissertation
Submitted to Department of Electronics Engineering
and Institute of Electronics
College of Electrical and Computer Engineering
National Chiao-Tung University
in partial Fulfillment of the Requirements
for the Degree of
Doctor of Philosophy
in
Electronics Engineering
June 2007
Hsin-Chu, Taiwan, Republic of China
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Student : Ju-Ming Chou
Advisor : Jieh-Tsorng Wu
Department of Electronics Engineering
and Institute of Electronics
National Chiao-Tung University
Abstract
Multi-phase clocks can be found in applications such as timing recovery, phase/frequency modulation and demodulation, and time-interleaved applications. The performance of those systems is mainly determined by the resolution of the available clock phases, i.e., how many and how accurate the available phases are, because all of the output phases of multi-phase clock generators will connect to outer parts for controlling the procedure of data processing. With the increasing of the applied processing frequency, the period of data processing is getting shorter and shorter. Also, if the circuits in the clock gen-erators do not match with outer environment and inner status, the timing margin of the clock signals will get much narrower to raise the complexity of the data processing terri-bly. Furthermore, with the ongoing advance of fabrication process, the problem of circuit mismatch will be getting worse and worse because of the circuit element’s shrinkage.
This thesis described circuit techniques using resistor strings (R-strings) and resistor rings (R-rings) for phase averaging and interpolation. Phase averaging can reduce phase errors, and phase interpolation can increase the number of available phases. In addition to the waveform shape, the averaging and the interpolation performances of the R-string and
expense of larger power dissipation. If multiple-phase clocks are available, folders can be used for frequency multiplication. To demonstrate the resistor ring’s capability of phase averaging and interpolation, an 8b 125MHz digital-to-phase converter (DPC) was de-signed and fabricated using a standard 0.35 µm SPQM CMOS technology. Measurement results show that the DPC attains 8-bit resolution using the proposed phase averaging and interpolation technique.
Circuit techniques using variable pre-charged delay units (VPDUs) for adjusting the time delay of the output phases of clock generators are also described in this thesis. The delay tuning mechanism is realized by changing the charging and discharging behavior at the internal node in VPDUs. The linearity of delay tuning in different conditions is de-scribed. VPDUs require digital-to-analog converters for providing pre-charging voltages, and combinational logic gates for generating timing control signals from clock gener-ator outputs. To demonstrate the VPDU’s capability, an 8-channels 1GHz phase-locked loop was fabricated using a standard 0.18 µm CMOS technology. The digitally-controlled VPDU has a 0.145 psec delay control resolution and a total control range of 69.78 psec.
First, I would like to thank my advisor Prof. Jieh-Tsorng Wu for his support and guidance in my research. Whenever I encounter the difficulties or problems, he is always patient to give me the direction and encouragement. I would also like to thank Prof. Chung-Yu Wu, Prof. Jiin-Chuan Wu, Prof. Ming-Dou Ker, and Prof. Wei-Zen Chen for teaching the courses and giving me the encouragement.
I wish to thank Mr. Cheng-Chung Hsu and Mr. Hung-Chih Liu for discussing the design skill. I wish to extend my gratitude to my classmates, Mr. Kuo-Chun Hsu, Miss Zwei-Mei Lee, Mr. Chung-Yun Chou, Miss Li-Ju Lin, Mr. Kuan-Hsun Huang, and Mr. Feng-Fei Ma, for discussing the courses. I also thank Mr. Chang-Tsung Fu, Mr. Jen-Lin Fan, Miss Chai Yun, Mr. Chi-Wei Fan, Mr. Chun-Cheng Huang, Mr. Chung-Yi Wang, Mr. Wei-Hsin Tseng, Mr. Yung-Hui Chung, Mr. Tzu-Chang Wang, Mr. Bing-Nang Fang, Mr. Su-Hao Wu, Mr. Jih-Ming Chang, and Mr. Cheng-Chan Tien for the wonderful research life in 307 Lab. I thank the Chip Implementation Center for chip fabrication.
Finally, I would like to express my greatest appreciation to my mother, my brother, and my girl friend, Miss Hsin-Yi Lin, for their unconditional support and encouragement.
J
U-M
INGC
HOU National Chiao-Tung University2007, June
Z` i
English Abstract iii
Acknowledgements v
List of Tables xi
List of Figures xiii
1 Introduction 1
1.1 Motivation . . . 1
1.2 Organization . . . 3
2 Multi-Phase Clock Generation 5 2.1 Introduction . . . 5
2.2 Phase-Locked Loop and Delay-Locked Loop . . . 6
2.2.1 Performance Limitation . . . 9
2.3 Extra Clock Phase Generation . . . 12
2.3.1 Two-Dimensional Array Oscillator . . . 13
2.3.2 Phase Interpolation . . . 18
2.3.3 Delay-Locked Loop Array . . . 20
2.4 Phase Accuracy Enhancement Technique . . . 22
2.4.1 Self-Calibrated Phase-Locked Loop . . . 22
2.4.2 Self-Calibrated Delay-Locked Loop . . . 24 vii
2.6 Summary . . . 29
3 Phase Processing Using Resistor Strings 31 3.1 Introduction . . . 31
3.2 Phase Averaging Using R-String . . . 31
3.3 Phase Interpolation Using R-String . . . 41
3.4 Resistor Rings . . . 44
3.5 Frequency Multipliers . . . 45
3.6 Summary . . . 46
4 An 8b 125MHz Digital-to-Phase Converter 47 4.1 Introduction . . . 47
4.2 Architecture of Digital-to-Phase Converter . . . 47
4.2.1 Fully-Differential Delay Cell . . . 50
4.2.2 Isolation Buffer . . . 53
4.3 Experimental Results . . . 56
4.4 Summary . . . 60
5 High-Resolution Phase Adjusting Technique 61 5.1 Introduction . . . 61
5.2 Phase Adjusting Techniques . . . 62
5.3 Variable Pre-Charged Delay Unit . . . 65
5.4 An 8-Channels 1GHz Phase-Locked Loop . . . 68
5.5 Experimental Results . . . 70
5.6 Summary . . . 75
6 Conclusions 77 6.1 Summary . . . 77
6.2 Recommendations for Future Investigation . . . 79 Appendix A Linear Models of PLLs/DLLs 81
Bibliography 91
Vita 101
4.1 Performance summary of the 8b digital-to-phase converter. . . 60 5.1 Performance summary of the 8-channels phase-locked loop. . . 74 5.2 Performance comparison. . . 75
1.1 Time-interleaved system. . . 2
2.1 Block diagrams of delay cell based multi-phase clock generators. (a) phase-locked loop, (b) delay-locked loop. . . 7
2.2 A basic phase-locked loop with eighteen output phases. . . 9
2.3 Output phases of a nine-stages ring oscillator. (a) ideal environment, (b) real environment. . . 11
2.4 Output phases of a delay line. . . 12
2.5 A 3x3 coupled ring oscillator array. . . 14
2.6 Operation modes of a 3x3 coupled ring oscillator array. . . 15
2.7 A phase interpolator with 360o tuning range. . . . 16
2.8 4X phase interpolation with phase blender circuits. . . 17
2.9 Phase blender for phase-resolution improvement. (a) simple model of phase-blending inverters, (b) phase-blender output with w = 0.5, (c) phase-blender output with optimal w. . . . 18
2.10 A delay-locked loop array. . . 21
2.11 A self-calibrated phase-locked loop. . . 23
2.12 A self-calibrated delay-locked loop. . . 25
2.13 A eight-stage shifted-averaging voltage-controlled delay line. . . 26
3.1 A simple delay line. . . 32
3.2 A delay line with a R-string. . . 33
3.3 A delay line with a R-string and isolation buffers. . . 34
3.4 A simplified model for analyzing a delay line with a R-string. . . 34 xiii
3.7 R-string’s space response of phase for β= 1, 10−1,10−2. . . . . 37
3.8 R-string’s INL reduction factor, RINL, versus β. . . . 38
3.9 R-string’s DNL reduction factor, RDNL, versus β. . . . 40
3.10 R-string voltage response for different input phase spacing. . . 41
3.11 Phase interpolation using R-string. . . 42
3.12 Phase error of a 16X R-string phase interpolator. . . 43
3.13 Phase interpolation and averaging using R-ring. . . 44
3.14 A frequency tripler using 3X folders. . . 45
3.15 A three-input folder for the frequency tripler. . . 46
4.1 An 8b digital-to-phase converter. . . 48
4.2 The effect of duty cycle (a) 50% (b) 62.5%. . . 50
4.3 A fully-differential delay cell. . . 51
4.4 A self-biased replica-feedback bias circuit. . . 51
4.5 A fully-differential amplifier with cross-coupled and diode-connected loads. 54 4.6 A isolation buffer. . . 55
4.7 Phase error of the R-Ring 2 phase interpolator. . . 56
4.8 Chip micrograph of the digital-to-phase converter. . . 57
4.9 Measured output jitter of the digital-to-phase converter. . . 57
4.10 (a) Measured transfer characteristics of the digital-to-phase converter. (b) Measured INL. (c) Measured DNL. . . 58
4.11 Measurement setup of the digital-to-phase converter. . . 59
5.1 A phase interpolator. . . 62
5.2 A simple digitally controlled delay element with RC time constant varia-tion techniques. . . 63
5.3 A simple digitally controlled delay element with current variation tech-niques. . . 64
5.4 Simulated transfer curves of 6-bits digitally controlled delay elements. . . 65 xiv
5.6 A multi-phase clock generator with variable pre-charged delay units. . . . 69
5.7 φ1-Vo,1signal path. . . 69
5.8 Chip micrograph of the 8-channels phase-locked loop. . . 70
5.9 Measured jitter performance of the 8-channels phase-locked loop. . . 71
5.10 Measured transfer curves of fine VPDU. . . 72
5.11 Measured DNL and INL of a fine VPDU with 0 V ≤ VL ≤ 0.5 V and 1.3 V ≤ VH ≤1.8 V . . . . 72
5.12 Measured DNL and INL of a fine VPDU with 0 V ≤ VL ≤ 0.6 V and 1.2 V ≤ VH ≤1.8 V . . . . 73
5.13 Simulated transfer curves of 6-bits digitally controlled delay elements. . . 73
5.14 Measurement setup of the 8-channels phase-locked loop. . . 74
A.1 Linear models of PLLs and DLLs. (a) PLL without charge pump, (b) PLL with charge pump, (c) DLL without charge pump, (d) DLL with charge pump. . . 82
C.1 A simple mixer. . . 88
C.2 Simulated transfer curves of normalized output phase versus input ampli-tude difference. . . 89
C.3 Simulated transfer curves of normalized output amplitude versus input amplitude difference. . . 90
Introduction
1.1
Motivation
With the development of communication technique, there are more and more articles deal-ing with the generation of multi-phase clocks in the complementary metal-oxide semi-conductor (CMOS) integral circuit design [1] [2] [3], i.e., generation of multiple periodic clock waveforms with different phases that equally divide the time period of an input ref-erence clock. Multi-phase clocks can be found in applications such as timing recovery [4] [5] [6], phase/frequency modulation and demodulation [7] [8] [9], and time-interleaved applications [10] [11] [12] [13] [14]. The performance of those systems is mainly deter-mined by the resolution of the available clock phases, i.e., how many and how accurate the available phases are, because all of the output phases of multi-phase clock generators will connect to outer parts for controlling the procedure of data processing.
Fig. 1.1 shows the block diagram of a time-interleaved system. The system uses all of the output phases of a multi-phase clock generator to sample the input data and then outputs by a multiplexer. The number of the output phases of the clock generator and the operation frequency of the clock generator dominate the processing frequency of the time-interleaved system. With the increasing of the applied processing frequency, the pe-riod of data processing is getting shorter and shorter. Also, if the circuits in the clock generators do not match with outer environment and inner status, the timing margin of the clock signals will get much narrower to raise the complexity of the data processing
φ2 φn φ1 φ1 φ2 φ3 φn Channel 1 Channel 2 Channel n S/H S/H S/H Data MUX
Figure 1.1: Time-interleaved system.
bly. Furthermore, with the ongoing advance of fabrication process, the problem of circuit mismatch will be getting worse and worse because of the circuit element’s shrinkage.
Multi-phase clocks are usually generated using a delay line consisting of cascaded delay cells, whose delay time is controlled by either a delay-locked loop or a phase-locked loop. If the delay cells are identical, then their outputs have identical waveform shapes but different phases. The number of available phases is the number of delay cells that constitute one (or half) clock period. The accuracy of the output phases is determined by the matching properties of the delay cells. At high clock frequencies, the available phases are limited by the minimum delay of the delay cells.
It is possible to attain phase resolution beyond the phase quantization step set by the delay cells. One novel scheme is using two-dimensional array oscillators. The phase res-olution is increased by the number of coupled rings at the expense of larger chip area and power dissipation. An alternative is using phase interpolators, which combine two clock waveforms of different phases to generate a new one. The resulting phase is determined by the combination weighting of the two inputs. In CMOS technologies, phase interpola-tors are usually realized using two source-coupled pairs sharing the same output port; and the ratio of their tail currents set the combination weighting. However, the relationship between the output phase and the current ratio is not linear and sensitive to other factors
such as source-coupled pair’s transconductance characteristics, waveform shape of the in-puts, and the pole frequency of the output port. Phase accuracy can be improved by using cascaded arrays of identical phase interpolators with fixed combination weighting. In this scheme, each phase interpolator is optimized to produce an output whose phase is located at the center of the two input phases.
Phase accuracy is often improved by using phase accuracy enhancement techniques. The techniques often use phase detectors or statistical analysis for determining the phase errors, and insert delay cells into each clock output paths for fine tuning the output phases. The resolution of the delay cells dominates the performance of the phase accuracy en-hancement techniques. The major penalties of those techniques are complex calibration loops, control circuits, and additional noise sources in the clock output paths.
This thesis describes a circuit technique that uses resistor strings (R-strings) or re-sistor rings (R-rings) for phase interpolation. Due to the symmetric nature of the circuit topology, the phases of the generated new clocks can be uniformly spaced. The R-strings and R-rings also exhibit an averaging capability that can reduce the phase errors caused by mismatches among the delay cells. Another circuit technique that uses variable pre-charged delay units (VPDUs) inserted in the clock paths for digitally-controlled the delay time of each clock path is described, too. It could be used to fine tune the output phases for better phase accuracy.
1.2
Organization
The rest of this thesis is organized as follows:
Chapter 2 describes the multi-phase clock generation. The prototypes of the clock generators are introduced. Their behavior and performance limitation are discussed. Sev-eral methods which could increase the available output phases and improve the quality of the output phases are introduced.
Chapter 3 describes the phase averaging and phase interpolation technique using the R-strings. A simplified model with capacitive loadings is used to analyze the phase av-eraging effect. The impact of capacitive loading on phase interpolation is also discussed. The condition and benefits of using R-rings is discussed. The technique of frequency
multiplication using R-rings and folders is also presented.
In Chapter 4, an 8b 125MHz CMOS digital-to-phase converter is described to demon-strate the proposed phase averaging and interpolation techniques. The digital-to-phase converter chip was fabricated in a standard 0.35 µm CMOS technology. The designs of fully-differential delay cells and isolation buffers for the phase averaging technique are also described.
Chapter 5 describes the high-resolution phase adjusting techniques. The linearity of the delay units and phase shifters dominates the performance of the phase adjusting tech-niques. Therefore, a novel delay unit called VPDU is introduced. The operation principle and timing diagram of the VPDUs are introduced. A design example is also presented. The chip was fabricated in a standard 0.18 µm CMOS technology.
Chapter 6 draws the conclusions of this thesis and makes recommendations for future work.
Multi-Phase Clock Generation
2.1
Introduction
Multi-phase clocks are usually generated by multi-phase clock generators. The clock generators could be identified as two classifications roughly. One of the classifications is the phase-locked loop. It generates multi-phase clocks by the voltage-controlled oscilla-tor. Another classification is the delay-locked loop. It generates multi-phase clocks by the voltage-controlled delay line. The voltage-controlled oscillator and the voltage-controlled delay line could be constructed by many different components with different methods. For example, the traveling wave principle could be used in the voltage-controlled oscillator design [15] [16] [17]. Its advantages are accurate high frequency signal generation, adia-batic operation, and good phase noise properties. In CMOS techniques, the most popular design methods of the voltage-controlled oscillator and the voltage-controlled delay line are cascading delay cells as a ring or a string [18] [19] [20].
In this chapter, the architectures, operation principles, analysis, and limitations of the phase-locked loops and the delay-locked loops with delay cell based voltage-controlled oscillators and voltage-controlled delay lines are introduced. The methods which could increase the number of output phases of the clock generators and improve the output phase quality are collected and discussed. Finally, the cause of jitter in clock generators is introduced.
2.2
Phase-Locked Loop and Delay-Locked Loop
Fig. 2.1 shows the two different architectures of delay cell based multi-phase clock gen-erators, phase-locked loop and delay-locked loop. The basic operation concepts of the two architectures are very similar. They adjust their output phases to follow the input reference clocks.
In the phase-locked loop shown in Fig. 2.1(a), the voltage-controlled oscillator gen-erates multi-phase clocks at each output node of the delay cells with the same delay time. The phase-locked loop is used to control the oscillation frequency of the voltage-controlled oscillator. The phase detector compares the phase difference between the put phase of the voltage-controlled oscillator and the input reference clock, and then out-puts the error message about the phase difference. The charge-pump circuit receives the error message and then adjusts its output, control voltage, to increase or decrease the op-eration frequency of the voltage-controlled oscillator. The output of the charge-pump cir-cuit would be filtered by a low-pass filter to filter the high-frequency noise. Because the voltage-controlled oscillator outputs phases by frequency integration, the phase-locked loop is a high-order control system. The transfer function of the system includes two poles at origin. The first pole is caused by the characteristic of the voltage-controlled os-cillator. Another pole is caused by the loop filter. In order to cancel the effect of the two poles, the transfer function should include a zero for the stability of the loop system [21]. This zero could be produced by a resistor and a capacitor with serial connection in the loop filter. However, due to the zero, high frequency attenuation of the loop filter is not enough to filter the high frequency noise. In order to solve this problem, another capacitor is placed in parallel. Finally, the loop system becomes a third-order system, thus the phase margin and the stability of the loop become critical issues. By setting the capacitance of the additional capacitor is 1/10 times to 1/15 times of another capacitor. The loop system could be approximated to a second-order system.
The classification of high-order transfer function would produce more complex prob-lems. For example, the process variation would change the position of the zero, thus the stability of the system would be destroyed [22] [23]. However, the voltage-controlled os-cillator provides many advantages. First, because the whole loop is a low-pass filter, the
Reference
Clock
Phase
Detector
Charge
Pump
Filter
Loop
Voltage−Controlled Oscillator
1 2 3 4 5 N−1 NVSS
(a)Reference
Clock
Phase
Detector
Charge
Pump
Filter
Loop
Voltage−Controlled Delay Line
1 2 3 4 5 N−1 N
VSS
(b)
Figure 2.1: Block diagrams of delay cell based multi-phase clock generators. (a) phase-locked loop, (b) delay-phase-locked loop.
jitter of the input reference clock would not affect the output clocks of the system directly. Second, the output frequency could be the multiple of the frequency of the input reference clock by using a frequency divider in the loop system. That is why the phase-locked loop is widely used in clock generation systems.
The delay-locked loop shown in Fig. 2.1(b) is only used in the fixed frequency sys-tems. The voltage-controlled delay line generates multi-phase clocks at each output node of the delay cells with the same delay time. The delay-locked loop is used to control the delay time of the voltage-controlled delay line. The phase detector compares the phase difference between the output phase of the voltage-controlled delay line and the input reference clock, and then outputs the error message about phase difference. The charge-pump circuit receives the error message and then adjusts its output, control voltage, to increase or decrease the delay time of the voltage-controlled delay line. The output of the charge-pump circuit would be filtered by a low-pass filter to filter the high-frequency noise. The voltage-controlled delay line is a simple delay gain element and has not the function of frequency integration as voltage-controlled oscillators. There is no necessary to add a zero in the loop system for stability. Therefore, the loop filter could be imple-mented by a simple integrator. The loop system must a very stable system, because the effect factors are tail away. That also means the design of delay-locked loops would be easier than the design of phase-locked loops. The detail analysis of phase-locked loops and delay-locked loops is described in Appendix A.
The major difference of phase-locked loops and delay-locked loops is the response when jitter occurs. In general, phase-locked loops have higher sensitivity of power supply noise and substrate noise, when those two systems are operated in the same frequency [24].
The operation frequency of voltage-controlled oscillators would be varied, when the voltages of power supply and substrate are changed by noise. The frequency error would become phase error by the frequency integration effect. The amount of phase error accu-mulation would be eliminated slowly by the loop. If the bandwidth of the loop is larger, the behavior of elimination would be faster. Otherwise, if the bandwidth is narrower, the behavior would be slower. If the supply voltage is varied in the delay-locked loop, the de-lay time would be affected at the moment when the noise occurs. The delay-locked loop
Detector
Phase
Pump
Charge
Reference
Clock
Filter
Loop
Figure 2.2: A basic phase-locked loop with eighteen output phases.
would not accumulate the phase error. Therefore, the loop bandwidth could be narrower to reduce the effect of the jitter of the input reference clock.
From above discussion, the design of delay-locked loops is easier than phase-locked loops, and the delay-locked loop is a stable system. There is no the effect of phase error ac-cumulation in delay-locked loops. Therefore, if frequency multiplication is not required, the delay-locked loop is a better choice than the phase-locked loop.
2.2.1
Performance Limitation
Multi-phase clock generators which are constructed by delay cells could be identified as two classifications roughly. One of the classifications is the phase-locked loop which includes a voltage-controlled oscillator constructed by cascading delay cells as a ring. Another classification is the delay-locked loop which includes a voltage-controlled delay line constructed by cascading delay cells as a string. The phase-locked loop with ring oscillator is used as an example to introduce the operation principle of the ring oscillator, to define the correlative nouns, and to describe the performance limitation factors of multi-phase clock generators.
Fig. 2.2 shows the block diagram of a basic phase-locked loop with eighteen output phases. The ring oscillator is constructed by fully-differential delay cells. It would be self-oscillation by its feedback loop. Assume the phase-locked loop is in lock, if there is
a positive voltage difference at the input nodes of the first delay cell, and then it would become negative voltage difference after the feedback of the loop. The delay time of this phenomenon is Ts/2 where Ts is the oscillation period. After another Ts/2, the voltage
difference would become positive again due to the feedback of the loop. Therefore, the oscillation behavior is established. The delay time of each delay cell of the ring oscillator is one oscillation period over two times of the number of the delay cells. If the ring oscil-lator is constructed by N delay cells, then the oscillation period and oscillation frequency,
fosc, would be obtained by
Ts = 2 · N · td (2.1) fosc= 1 Ts = 1 2 · N · td (2.2) where td is the delay time of a delay cell. From the fact shown in Equation 2.2, if the
oscillation frequency of the ring oscillator is required to be changed, then the delay time or the number of delay cells should be changed. In order to meet the required oscillation frequency defined by system specification, a better method is using a control voltage to change the delay time of delay cells.
The maximum number of the output phases of the ring oscillator, 2NMax, is limited
by the required operation frequency and the minimum delay time of a delay cell, td,Min.
2NMax= Ts td,Min = 1 fosc· td,Min (2.3) Another performance limitation of the multi-phase clock generator is phase accu-racy. When a phase-locked loop is in lock and the ring oscillator is constructed by nine fully-differential delay cells, the ring oscillator should produce eighteen phases which are equally-spaced distributed around an oscillation period. The phase difference of each two adjacent phases is completely equal. Fig. 2.3(a) shows the ideal output result which the ring oscillator should produce. However, due to the process variation, defects of sub-strate, and so on, the delay cells and the metal-oxide-semiconductor field-effect transistors (MOSFETs) are mismatch. The phase difference of each two adjacent phases would not be equal, and then phase errors occur. Besides, in order to reduce the chip area, the MOS-FETs with minimum channel length are often chosen. With the advancement of process, the channel length of MOSFETs becomes smaller, so the mismatching probability and
0 2 4 6 8 1012141618
0 2 4 6 8 1012141618
(b) Real
(a) Ideal
Edge Spacing
Edge Spacing
Edge Number
Edge Number
Figure 2.3: Output phases of a nine-stages ring oscillator. (a) ideal environment, (b) real environment.
effect would become larger. Therefore, in real environment, the ring oscillation would produce eighteen phases with unequally-spaced phase difference which is shown in Fig. 2.3(b).
In order to determine the difference of the phases produced by a multi-phase clock generator between the ideal environment and the real environment, two quality factors are defined.
• Integral nonlinearity (INL). • Differential nonlinearity (DNL).
INL is the phase error which can be obtained by calculating the difference between the real output phases and the ideal output phases. DNL is the phase difference error which can be obtained by calculating the difference between the real output phase differences and the ideal output phase differences. Fig. 2.4 shows the output phases of a delay line. In real environment, the delay time of each delay cell is not the same, and then phase error occurs. The INL of the output phases of the delay line is φe
φ
2φ
1φ
0φ
−1φ
−2φ
e−2φ
−1 eφ
e 1 eφ
2Ideal
Real
∆φ
0
oFigure 2.4: Output phases of a delay line.
DNL of the output phases is |φx−1− φx| − ∆φ, where x= · · · , −2, −1, 0, 1, 2, · · · and ∆φ
is the ideal output phase difference. If INL and DNL are smaller, the quality of the output phases of multi-phase clock generators is better.
2.3
Extra Clock Phase Generation
The maximum number of the output phases of multi-phase clock generators is limited by the required operation frequency of the clock generator and the minimum delay time of a delay cell in the clock generator. In order to increase the available output phase, many techniques are presented in many journals [25] [26] [27]. They could be identified as two classifications roughly. One of the classifications is phase interpolation by using phase interpolator. Another is array structure by combining several voltage-controlled oscillators or voltage-controlled delay lines.
In this section, three methods would be introduced. They are two-dimensional array oscillator, phase interpolation, and delay-locked loop array. They are the major methods to increase the output phases of multi-phase clock generators in recent years.
2.3.1
Two-Dimensional Array Oscillator
Two-dimensional array oscillators could be used to overcome the limitation of the mini-mum delay time of delay cells and to output more available phases [28] [29]. They are constructed by combining several ring oscillators to form an oscillator array. Each delay cell of the ring oscillators consists of two input stages. One of the input stages is used to connect to the output of another delay cell to form a ring oscillator. Another input stage is used to connect to the output of the upper ring oscillator to make each ring oscillator correlative. The effects of each input to the output of delay cells are equal. Therefore, each ring oscillator oscillates by itself and the degree of their output phases is dominated by themselves and the upper ring oscillator. That is the basic design concept of two-dimensional array oscillators. The phase resolution is increased by the number of coupled rings at the expense of larger chip area and power dissipation. If the number of the delay cells in a ring oscillator is N, the number of the ring oscillators is M, and the delay cells are signal-ended, the total available output phases could be obtained by
Available Output Phases= M · N (2.4) And, the phase resolution is improved by M.
The most important characteristic of the two-dimensional array oscillators is symme-try. Each delay cell experiences the same circuit configuration at the output port around the array oscillator. Therefore, if the array oscillator operates in a stable state, the input signals of each delay cell must be very similar. That means the operation frequency of each ring oscillator are the same, and the delay time of each delay cell is the same, too. Two possible operation states of the array oscillator could satisfy the above descriptions. One of the operation states is that there is no phase difference between the input signals of the delay cell. Another is that there are equally-spaced phase differences between the input signals.
The number of stable operation mode of the two-dimensional array oscillators is an important issue. If the stable operation mode is not unique, the sorting order of the output phases is not unique. That means the degree of the output phases could not be predicted. If the output phases connect to outer circuits to control their timing sequences in a system, the uncertainty may damage the normal operation of the system. Therefore, the stable
T
0
T
1
T
2
B
0
B
1
B
2
11/3D
2/3D
14/3D
5/3D
8/3D
17/3D
10/3D
1/3D
13/3D
4/3D
16/3D
7/3D
9/3D
0
12/3D
3/3D
15/3D
6/3D
Mode 1
Mode 0
1/3D
0
−1/3D
1/3D + 2D
0
3/3D
3/3D
−1/3D − 2D
280
Mode 1
Mode 0
40
I
1I
2I
3I
4φ
Qφ
Iφ
outVDD
VSS
VSS
VSS
VSS
Figure 2.7: A phase interpolator with 360o tuning range.
operation mode must be unique in the two-dimensional array oscillator design.
In order to avoid the sorting order problem of the output phases in the two-dimensional array oscillator design, the delay cells with three input stages are used [30] [31] [32] [33]. The additional input stage is used to connect to the output of the lower ring oscillator. The additional input stage is used to enlarge the input phase difference of delay cells. Fig. 2.5 shows a 3x3 coupled ring oscillator array with three input stages fully-differential delay cells. In this architecture, T0connects B1, T1connects B2, and T2connects B0. The degree
of each output phase could be calculated easily. Fig. 2.6 shows the possible operation modes of the 3x3 coupled ring oscillator array. In Mode 0, the input phase difference is 40o, and in Mode 1, the input phase difference is 280o. Due to the cancellation effect, Mode 1 could not be a stable operation mode. Therefore, it consists of a unique stable operation mode, Mode 0, and outputs eighteen output phases with predictable sorting order.
’
φ
A,0
’
φ
A,1
’
φ
B,0
φ
B
φ
A
’’
φ
B,0
’’
φ
A,3
’’
φ
A,2
’’
φ
A,1
’’
φ
A,0
Phase blender
φ
Bφ
Aφ
Aφ
oφ
Bφ
oφ
Aφ
oφ
Bw x I
(1−w) x I
R
C
(a)
(b)
(c)
VDD
VSS
VSS
Figure 2.9: Phase blender for resolution improvement. (a) simple model of phase-blending inverters, (b) phase-blender output with w = 0.5, (c) phase-blender output with optimal w.
2.3.2
Phase Interpolation
Phase interpolation by using phase interpolators is the most popular method to increase the number of available output phases in multi-phase clock generator design [34] [35] [36]. Phase interpolators combine two clock waveforms of different phases to generate a new one. The resulting phase is determined by the combination weighting of the two inputs. In CMOS technologies, phase interpolators are usually realized using two source-coupled pairs sharing the same output port; and the ratio of their tail currents set the combination weighting.
Fig. 2.7 shows the schematic of the phase interpolator with 360o tuning range. The
phase difference between φI and φQ is 90o. The resulting output phase, φout could be
obtained by
φout = α1· φI+ α2· φQ (2.5)
where α1 depends on I1 - I2, and α2 depends on I3 - I4. In order to maintain constant
equations.
α12+ α22 = constant (2.6)
I1+ I2 = I3+ I4 = constant (2.7)
However, the relationship between the output phase and the current ratio is not linear and sensitive to other factors such as source-coupled pair’s transconductance characteristics, waveform shape of the inputs, and the pole frequency of the output port.
Phase accuracy could also be improved by using cascaded arrays of identical phase interpolators with fixed combination weighting [37] [38] [39]. In this scheme, each phase interpolator is optimized to produce an output whose phase is located at the center of the two input phases.
Fig. 2.8 shows the block diagram of a 4x phase interpolation with phase blender circuits. The phase blender circuit is basically an equally-weighted phase interpolator. By the characteristic of equally-weighted sum, the degree of each new phase is the half of the degree sum of its two input phases ideally. Fig. 2.9(a) shows the simple model of phase-blending inverters. Due to the effect of the pole frequency of the output port and input waveform shapes, the output phase of the phase blender shown in Fig. 2.9(b) is not ideal. The output of the phase blender could be expressed as
Vo(t) = VDD + R · I · h w · u(t) · (e−RCt −1)+ (1 − w) · u(t − t d) · (e− t−td RC −1) i (2.8) where td is the timing difference of the two inputs, φAand φB. The position of the output
phase could be optimized by varying w.
If ignoring the delay of phase blender circuits and buffers, the ideal degree of each output phase could be obtained as follows.
φ00A,0 = φ0A,0= φA (2.9) φ00A,1 = φ 0 A,0+ φ 0 A,1 2 = 3 4φA+ 1 4φB (2.10) φ00A,2 = φ0A,1= 1 2φA+ 1 2φB (2.11) φ00A,3 = φ 0 A,1+ φ 0 B,0 2 = 1 4φA+ 3 4φB (2.12) φ00B,0 = φ0B,0 = φB (2.13)
If more phase blenders are inserted into Fig. 2.8, the more available output phases are generated. However, if there are more phase blenders, the clock paths would be longer. That means there are more noise sources in each clock path. And, if output phase of the first-stage phase blender is not accurate, the output phases of the following ideal phase blenders are not accurate, too.
2.3.3
Delay-Locked Loop Array
Another method which could overcome the limitation of the minimum delay time of delay cells and to output more available phases is using delay-locked loop array [40] [41] [42]. Fig. 2.10 shows the block diagram of a delay-locked loop array. It consists of a master delay-locked loop and F slave delay-locked loops. The slave delay-locked loops have the same configuration. There are M delay cells in the master delay-locked loop, and there are N delay cells in each slave delay-locked loops. F is the submultiple of M. That means each input reference clock of slave delay-locked loops are equally-spaced. The total output phases of the delay-locked loop array could be obtained by
Total Output Phases= F · N (2.14) The delay step in the master delay-locked loop is
td,master =
Tref
M (2.15)
where td,masteris the delay time of the delay cells in the master delay-locked loop, and Tref
is the period of input reference clock. The delay step in the slave delay-locked loops is
td,slave =
Tref
N (2.16)
where td,slave is the delay time of the delay cells in the slave delay-locked loop. The delay
resolution, tbin, could be improved as
tbin = |td,master×
M
F − td,slave|=
|N − F |
M · N × Tref (2.17)
However, the number of available output phases is not the same as the number of the total output phases. That means this method would produce many phases with the same degree.
PD PD PD PD PD Clock Reference PD DLL1 N 1 2 3 4 5 N−1 DLL2 N 1 2 3 4 5 N−1 DLL3 N 1 2 3 4 5 N−1 DLL4 N 1 2 3 4 5 N−1 DLLF N 1 2 3 4 5 N−1 Master DLL 1 2 3 4 5 6 7 8 M−1 M Slave DLLs
For example, if F = 2 and N = 4, the DLL1 would produce four phases, 0o, 90o, 180o,
270o, and the DLL
2 would also produce four phases, 180o, 270o, 0o, 90o. The number of
total output phase is eight, but the number of available output phases is four. In order to reduce the waste of the phases with the same degree, the value of M and N should be carefully selected.
2.4
Phase Accuracy Enhancement Technique
Due to the process variation, defects of substrate, and so on, the delay cells and the MOSFETs are mismatch. The phase difference of each two adjacent output phases of multi-phase clock generators would not be equal and then phase errors occur. In order to improve the quality of the output phases of the clock generators, many techniques are pre-sented in many journals [43] [44] [45]. They are often using a calibration loop to calibrate their output phases by themselves.
In this section, three methods for improving the quality of the output phases of multi-phase clock generators are introduced. They are calibrated multi-phase-locked loop, self-calibrated delay-locked loop, and shifted-averaging voltage-controlled delay line.
2.4.1
Self-Calibrated Phase-Locked Loop
Fig. 2.11 shows the block diagram of a self-calibrated phase-locked loop [46] [47]. It is basically a traditional phase-locked loop. The major difference of the self-calibrated phase-locked loop and traditional phase-locked loops is that the delay time of each delay cells in the self-calibrated phase-locked loop is not only controlled by the output of the major charge pump circuit, CP1, but also the minor charge pump circuit, CP2. The delay cells consist of two adjustable output loads. One of the output loads controlled by CP1 is used to maintain the frequency control ability as a traditional phase-locked loop. Another output load is used to fine tune the output phase. The divide ratio of the frequency divider is M+ k/8. The output of the voltage-controlled oscillator would be divided by M first, and then be re-sampled by the eight output phases. If k= 1, the switch box would output the re-sampled output phases in proper sequence. At the same time, the control signals of
8
Divider &
Switch Box
CP1
Control
PFD
CP2
8
8
Frequency
Control
Offset
Control
Clock
Reference
divide ratio: M+k/8
DFF
DFF
DFF
DFF
Divide by M
φ
1φ
2φ
3φ
8Switch
Box
VSS
VSS
VSS
the switch box would also control the CP2’s output switches to fine tune each delay cell. Finally, phase errors are calibrated.
This analog fine tune method could eliminate phase errors completely. However, if k is the submultiple of the number of the output phases of the voltage-controlled oscillator, several phases could never be selected. That means the unselected phases would never be calibrated. And, if the phase selection paths are mismatch, the systemic phase errors occur. Every time when the delay cell is fine tuned, the calibration loop should halt to wait for the phase-locked loop locked again. Therefore, the calibration period spends much time. If the operation frequency of the system is slow, the leakage current of the capacitors at the output node of the operational amplifiers would damage the performance of the calibration loop.
2.4.2
Self-Calibrated Delay-Locked Loop
By inserting additional delay cells into the output phase paths of delay-locked loops, the quality of the output phase could be improved by fine tuning the delay time of each addi-tional delay cell [48] [49] [50]. The available calibration methods could be identified as two classifications. One of the classifications is analog control. Another is digital control. The calibration methods using analog control are often realized by using the basic design concept of delay-locked loops. The major issues of this method are the matching of the calibration paths and complex layout. The calibration methods using digital control are often realized by using the basic concepts of statistics. The major issue of this method is that the resolution and linearity of delay cells dominates the performance and costs of the method.
Fig. 2.12 shows a self-calibrated locked loop. Each output phase of the delay-locked loop connects to a delay cell. The delay time of the delay cells could be adjusted individually by the control signals. The delay comparator is used to judge if the phase differences between three input phases are equal. If the phase differences are not equal, the delay comparator would vary its output to increase or decrease the delay time of the delay cells. Finally, each clock path is calibrated and the phase difference between each
Clock
Reference
PD
Signals
Control
φ
1
φ
2
φ
n−1
φ
n
Delay
Comparator
Delay
Comparator
Delay
Comparator
φ
1
φ
2
φ
3
φ
n
φ
1
φ
n
φ
1
φ
2
φ
n−1
1
2
N−1N
1
2
N−1N
Delay Comparator Array
φ
8+
φ
7+
φ
6+
φ
5+
φ
5−
φ
6−
φ
7−
φ
8−
φ
4+
φ
3+
φ
2+
φ
1+
φ
4−
φ
3−
φ
2−
φ
1−
5
6
7
8
1
2
3
4
Figure 2.13: A eight-stage shifted-averaging voltage-controlled delay line. phase are equal.
φ1− φ2 = φn− φ1 (2.18) φ2− φ3 = φ1− φ2 (2.19) φ3− φ4 = φ2− φ3 (2.20) φ4− φ5 = φ3− φ4 (2.21) · · · φn− φ1 = φn−1− φn (2.22)
The major issue of this method is the stability of the calibration loops. Because the delay tuning of each delay cell would affect the results of other delay comparators, the whole calibration loop may not convergence.
2.4.3
Shifted-Averaging Voltage-Controlled Delay Line
Shifted-averaging voltage-controlled delay line could also be used to decrease phase er-rors [51] [52] [53]. The architecture is an excellent invention because it does not require
any additional circuits to improve the quality of its output phases. It is basically a tradi-tional delay line, but the connection method is different. If the delay line is in locked, the total delay of the delay line is a clock period, and the reference clock possesses a 50% duty cycle, the delay line would output two sets of output phases with the same degree due to the use of fully-differential delay cells. By exchanging the connection of the phases with the same degree, the INL of the output phases of the delay line could be improved by√2.
Fig. 2.13 shows an eight-stage shifted-averaging voltage-controlled delay line. If the above conditions are satisfied, the degree of its output phases is shown in follows.
φ1+ = φ5− ; φ5+ = φ1− (2.23) φ2+ = φ6− ; φ6+ = φ2− (2.24) φ3+ = φ7− ; φ7+ = φ3− (2.25) φ4+ = φ8− ; φ8+ = φ4− (2.26) By exchanging the connections of φ1−, φ2−, φ3−, φ4−, φ5+, φ6+, φ7+, and φ8+, the ability
of phase errors reducing in the delay line is established.
This method could smooth phase errors with a fixed improvement factor,√2. In order to achieve the maximum improvement, the symmetry in layout is very important.
2.5
Jitter in Clock Generator
In clock generators, the operation of circuits affected by noise is unavoidable and then jitter occurs. When jitter occurs, the quality of the phases of output clocks produced by clock generators would be reduced. Therefore, jitter is the most important index factor of the performance of clock generators.
There are two reasons which would cause jitter. One of the reasons is that the input reference clock signal is poor quality. Another comes from the noise sources of MOSFETs in clock generators. The noise sources of MOSFETs are the internal noises including thermal noise, shot noise, and flicker noise, and the external noises including supply noise coupling and substrate noise coupling. In the clock generator design, the delay cells with
high anti-noise ability and good architecture of the clock generator should be chosen for reducing jitter.
The architectures of clock generators are introduced in previous sections. The cause of jitter includes the jitter of the input reference clock and the noise sources in clock generators [54]. No matter which architecture is chosen, it must include a low-pass filter. Therefore, the closed-loop transfer function between the input reference clock and output clocks is a low-pass function. If the bandwidth of the phase-locked loop is narrower, the jitter of the input reference clock could be ignored easily. But, the quality of output clocks would be limited by the noise sources in the clock generator. In this case, if output phases shift a little, the loop system can not fix it immediately. In the wide bandwidth phase-locked loop, the phase shift could be fixed faster. However, if the bandwidth is very wide, the jitter of the input reference clock can not be ignored anymore. Therefore, the system performance is limited by the jitter of the input reference clock in this case. With the consideration of the stability of the loop system and the two factors, the bandwidth of phase-locked loops should be chosen as 1/10 times to 1/20 times of the frequency of the input reference clock. The delay-locked loop has not the problem of phase error accumulation. Therefore, its bandwidth could be narrower.
In many documents, the detail analysis of the jitter produced by delay cells had been introduced, and the design concepts of delay cells had been pointed out [55] [56] [57] [58] [59] [60].
1. Jitter is an inverse proportion to the VGS − Vtof input MOSFETs.
2. With a fixed delay time, if the power consumption of delay cells is larger, then the jitter would be smaller.
3. The charging and discharging paths of delay cells for output should be symmetric to suppress the high frequency up-conversion phenomenon of the flicker noise. 4. With a fixed power consumption and operation frequency, if the number of cascaded
delay cells is more, the jitter produced by fully-differential delay cells is worse. But, the jitter produced by single-ended delay cells would be the same.
In several circuit environments, the jitter of output clocks would be dominated by the noise of power supply and substrate. Because the jitter produced by the internal noise sources is few femto seconds. However, the jitter produced by power supply noise and substrate noise is few pico seconds. Therefore, how to design a delay cell which is not so easy to be affected by the external noise sources is very important.
The effect of the external noise sources could be identified as two classifications. When the DC level of the power supply voltage is changed, the delay time of delay cells would be different. If the change of the DC level is caused by noise, the phases of output clocks would be shifted. This classification is called static supply noise sensitivity. The measurement method is to measure the variation of delay time when the DC level of the power supply voltage changes. When the variation is smaller, the sensitivity is smaller. Another classification is called dynamic supply noise sensitivity. When the power supply voltage is changed temporarily, the delay time of delay cells would be different temporar-ily, too. The measurement method is to measure the variation of the delay time when the power supply voltage is an AC function. Because the variation effect of the substrate voltage is the same as the power supply voltage, the same measurement methods can be used for judging the sensitivities caused by the substrate noise.
2.6
Summary
Multi-phase clocks are usually generated by phase-locked loops and delay-locked loops. The voltage-controlled oscillator and the voltage-controlled delay line are the most im-portant components of the clock generators to generate multi-phase clocks. They can be constructed by many different components with different methods. In CMOS techniques, the most popular design methods of the controlled oscillator and the voltage-controlled delay line are cascading delay cells as a ring or a string.
The maximum number of the output phases of multi-phase clock generators is limited by the required operation frequency of the clock generator and the minimum delay time of a delay cell. The methods which can overcome the limitation can be identified as two classifications, phase interpolation by using phase interpolator and array structure by combining several voltage-controlled oscillators or voltage-controlled delay lines. Three
major methods to increase the output phases of multi-phase clock generators are two-dimensional array oscillator, phase interpolation, and delay-locked loop array.
Due to the process variation, defects of substrate, and so on, the delay cells and the MOSFETs are mismatch. The phase difference of each two adjacent output phases of multi-phase clock generators would not be equal and then phase errors occur. The meth-ods which can calibrate the phase errors are often using a calibration loop to calibrate their output phases by themselves. Three major methods for improving the quality of the output phases of multi-phase clock generators are self-calibrated phase-locked loop, self-calibrated delay-locked loop, and shifted-averaging voltage-controlled delay line.
Phase Processing Using Resistor Strings
3.1
Introduction
In this chapter, a novel multi-phase clock generation technique which could be used to smooth the phase errors caused by the mismatch of the delay cells of multi-phase clock generators is introduced. This phase averaging technique requires a multi-phase clock generator and resistors. Each resistor connects to two adjacent phases produced by the clock generator to form a resistor string (R-string) or a resistor ring (R-ring). The R-string and R-ring provide a current path to distribute the error currents induced by the phase errors into each output node of the clock generator. By the distribution of error currents the quality of the output phases could be improved. The R-string and R-ring could also be used to generate more output phases by phase interpolation. How this technique improves the quality of the output phases, and the penalties for using resistors would be introduced in the following sections. The technique of frequency multiplication using R-rings and folders is also presented.
3.2
Phase Averaging Using R-String
In the previous chapter, the quality factors, INL and DNL, are introduced. In order to achieve the better quality when designing a multi-phase clock generator before, the place-ment of MOSFETs in layout should be symmetric perfectly or using other control
φ
o,0
φ
o,−1
φ
o,+1
φ
o,+2
φ
o,−2
Delay Line
Figure 3.1: A simple delay line.
cuits fine tunes the output phases. However, the above methods would make the system more complex and increase the difficulty of layout. Therefore, a novel phase averaging technique is developed to decrease the phase and phase difference errors caused by the mismatch of delay cells and MOSFETs.
Fig. 3.1 shows a traditional delay line consisting of multiple delay cells. Assuming that all of the delay cells are identical, the output of each delay cell would produce an equally-spaced phase. That means the phase difference between each two adjacent output phases are the same. However, due to the mismatches among the delay cells and MOS-FETs, the phase difference between two adjacent delay cells would not be the same along the delay line.
The occurrence of the phase error, φe,n, could be visualized as an error current flowing
into the output loading of the n-th delay cell, thus varying the output phase from its correct position. If the error current could be eliminated, decreased, or equally distributed to the output loads of each delay cell around a delay line, then the performance of the delay line should be improved. A feasible method is inserting an additional current path leading the error current to flow into its output loads and the other output loads.
Fig. 3.2 shows the schematic of a delay line coupling with a R-string whose resistor element has an identical resistance of R. The R-string introduces a spatial filtering effect on the outputs [61]. When R approaches to infinity, the interconnection between adjacent delay cells breaks and the outputs of the delay line are determined merely by their cor-responding delay cells. With shrinking R, each output would begin to be affected by the
φ
o,0
φ
o,−1
φ
o,+1
φ
o,+2
φ
o,−2
R
R
R
R
R
R
Delay Line
Figure 3.2: A delay line with a R-string.
neighboring ones. That is because the output currents of each delay cell would not only flow into their own loads, but also the neighboring ones via the R-string. The interaction between the outputs leads to the basic concept of phase averaging.
For most delay cell designs, the delay time is controlled by varying the equivalent output resistance Ro to change the RoCo product associated with the output node, where
Co is the total capacitance at the output node. This RoCo product will be changed if the
R-string is added. In addition, the value of R is small comparing to Ro so as to achieve
good phase averaging effect. This will lead to a reduction in the controllable range of delay time. Thus, it is necessary to separate the function of delay time control from the R-string’s phase averaging function.
Fig. 3.3 shows a schematic consisting of a delay line, R-string, and isolation buffers. The buffers isolate the delay line from large resistive and capacitive loadings, and inherit the phase information from their corresponding delay-cell output. The output resistance of the buffers should be high to attain the strongest averaging effect offered by the R-string [61] [62] [63]. The control of the delay line is separated from the R-string. The output phase errors due to the delay-cell mismatches and buffer mismatches can also be reduced by the R-string.
The voltage waveform at each output node in Fig. 3.3 is determined not only by the output currents of the neighboring isolation buffers, but also by the resistive and capacitive
φ
o,0
φ
o,−1
φ
o,+1
φ
o,+2
φ
o,−2
Isolation
Buffers
R
R
R
R
R
Delay Line
Figure 3.3: A delay line with a R-string and isolation buffers.
Ii,0
Ii,−1
Ii,−2
Vo,+1
Vo,+2
Vo,−1
Vo,−2
Ii,+1
Ii,+2
Vo,0
ω
i
φ
i,0
IA
Io,0
Io,+2
Io,−1
Io,−2
Io,+1
φ
o,0
φ
o,−1
φ
o,+1
φ
o,+2
φ
o,−2
t
R
R
R
R
R
C
C
C
C
C
R
sin( )
VSS VSS VSS VSS VSSloadings at the output nodes. In order to quantitatively analyze the circuit’s behavior, the simplified model shown in Fig. 3.4 is used. The capacitance at each output node is C. The buffers are modeled as ideal current sources with sinusoidal output currents expressed as:
Ii,x = IAsin (ωit+ φi,x) x= 0, ±1, ±2, · · · (3.1)
where IA is the current amplitude, ωi is the clock frequency, and φi,x is the clock phase.
The output current flowing into the output capacitor is Io,x. As derived in Appendix B,
with Ii,x = 0 for x 6= 0, the frequency response of the single buffer current Ii,0 to the
output current Io,xcan be expressed as:
AI(β, x)= Io,x Ii,0 = (−4j/β)|x| p 1 − 4j/β 1+ p1 − 4j/β |2x| (3.2) where β = ωi× RC (3.3)
is the input frequency normalized by the RC product of the R-string.
Fig. 3.5 shows the frequency response of |AI(β, x)| at different locations, i.e., x = 0,
±1, and ±2. Data from both calculation using Equation 3.2 and simulation using SPICE are shown, thus verifying the validity of Equation 3.2. At x = 0, the transfer gain |AI(β, 0)| is increased for larger β, i.e., at a higher clock frequency, more current flows
into the capacitor directly connected to the signal source. For β > 10, |AI(β, 0)|
ap-proaches 1 and the R-string loses its phase averaging capability. Therefore, a smaller β is good for phase averaging.
Fig. 3.6 and Fig. 3.7 show the space response of AI(β, x), i.e., magnitude and phase
responses at different locations, for β = 1, 1/10, and 1/100. For smaller β, the buffer current is distributed more evenly to the neighboring output capacitors, resulting in a stronger phase averaging effect.
By neglecting R-string’s boundary conditions and assuming all sinusoidal current in-puts have an identical amplitude of IA, the voltage on the output nodes can be computed
10
-210
-110
010
110
2β
=
ω
i×
RC
-40
-20
0
|A
I(
β
,x)| (dB)
Calculation
Simulation
x = 0
x = ±1
x = ±2
Figure 3.5: R-string frequency response at locations x= 0, x = ±1, and x = ±2.
