Figure 2.8: 4X phase interpolation with phase blender circuits.
φ
Bφ
Aφ
Aφ
oφ
Bφ
oφ
Aφ
oφ
Bw x I (1−w) x I
R C
(a) (b) (c)
VDD
VSS VSS
Figure 2.9: Phase blender for resolution improvement. (a) simple model of phase-blending inverters, (b) phase-blender output with w = 0.5, (c) phase-blender output with optimal w.
2.3.2 Phase Interpolation
Phase interpolation by using phase interpolators is the most popular method to increase the number of available output phases in multi-phase clock generator design [34] [35] [36].
Phase interpolators combine two clock waveforms of different phases to generate a new one. The resulting phase is determined by the combination weighting of the two inputs.
In CMOS technologies, phase interpolators are usually realized using two source-coupled pairs sharing the same output port; and the ratio of their tail currents set the combination weighting.
Fig. 2.7 shows the schematic of the phase interpolator with 360o tuning range. The phase difference between φI and φQ is 90o. The resulting output phase, φout could be obtained by
φout = α1· φI+ α2· φQ (2.5) where α1 depends on I1 - I2, and α2 depends on I3 - I4. In order to maintain constant output amplitude, the weighting factors from Equation 2.5 should fulfill the following
equations.
α12+ α22 = constant (2.6) I1+ I2 = I3+ I4 = constant (2.7) However, the relationship between the output phase and the current ratio is not linear and sensitive to other factors such as source-coupled pair’s transconductance characteristics, waveform shape of the inputs, and the pole frequency of the output port.
Phase accuracy could also be improved by using cascaded arrays of identical phase interpolators with fixed combination weighting [37] [38] [39]. In this scheme, each phase interpolator is optimized to produce an output whose phase is located at the center of the two input phases.
Fig. 2.8 shows the block diagram of a 4x phase interpolation with phase blender circuits. The phase blender circuit is basically an equally-weighted phase interpolator. By the characteristic of equally-weighted sum, the degree of each new phase is the half of the degree sum of its two input phases ideally. Fig. 2.9(a) shows the simple model of phase-blending inverters. Due to the effect of the pole frequency of the output port and input waveform shapes, the output phase of the phase blender shown in Fig. 2.9(b) is not ideal. The output of the phase blender could be expressed as
Vo(t) = VDD + R · I ·h
w · u(t) · (e−RCt −1)+ (1 − w) · u(t − td) · (e−t−tdRC −1) i
(2.8) where td is the timing difference of the two inputs, φAand φB. The position of the output phase could be optimized by varying w.
If ignoring the delay of phase blender circuits and buffers, the ideal degree of each output phase could be obtained as follows.
φ00A,0 = φ0A,0= φA (2.9)
If more phase blenders are inserted into Fig. 2.8, the more available output phases are generated. However, if there are more phase blenders, the clock paths would be longer.
That means there are more noise sources in each clock path. And, if output phase of the first-stage phase blender is not accurate, the output phases of the following ideal phase blenders are not accurate, too.
2.3.3 Delay-Locked Loop Array
Another method which could overcome the limitation of the minimum delay time of delay cells and to output more available phases is using delay-locked loop array [40] [41] [42].
Fig. 2.10 shows the block diagram of a delay-locked loop array. It consists of a master delay-locked loop and F slave delay-locked loops. The slave delay-locked loops have the same configuration. There are M delay cells in the master delay-locked loop, and there are N delay cells in each slave delay-locked loops. F is the submultiple of M. That means each input reference clock of slave delay-locked loops are equally-spaced. The total output phases of the delay-locked loop array could be obtained by
Total Output Phases= F · N (2.14)
The delay step in the master delay-locked loop is td,master = Tref
M (2.15)
where td,masteris the delay time of the delay cells in the master delay-locked loop, and Tref
is the period of input reference clock. The delay step in the slave delay-locked loops is td,slave = Tref
N (2.16)
where td,slave is the delay time of the delay cells in the slave delay-locked loop. The delay resolution, tbin, could be improved as
tbin = |td,master× M
F − td,slave|= |N − F |
M · N × Tref (2.17) However, the number of available output phases is not the same as the number of the total output phases. That means this method would produce many phases with the same degree.
PD
Figure 2.10: A delay-locked loop array.
For example, if F = 2 and N = 4, the DLL1 would produce four phases, 0o, 90o, 180o, 270o, and the DLL2 would also produce four phases, 180o, 270o, 0o, 90o. The number of total output phase is eight, but the number of available output phases is four. In order to reduce the waste of the phases with the same degree, the value of M and N should be carefully selected.
2.4 Phase Accuracy Enhancement Technique
Due to the process variation, defects of substrate, and so on, the delay cells and the MOSFETs are mismatch. The phase difference of each two adjacent output phases of multi-phase clock generators would not be equal and then phase errors occur. In order to improve the quality of the output phases of the clock generators, many techniques are pre-sented in many journals [43] [44] [45]. They are often using a calibration loop to calibrate their output phases by themselves.
In this section, three methods for improving the quality of the output phases of multi-phase clock generators are introduced. They are calibrated multi-phase-locked loop, self-calibrated delay-locked loop, and shifted-averaging voltage-controlled delay line.
2.4.1 Self-Calibrated Phase-Locked Loop
Fig. 2.11 shows the block diagram of a self-calibrated phase-locked loop [46] [47]. It is basically a traditional phase-locked loop. The major difference of the self-calibrated phase-locked loop and traditional phase-locked loops is that the delay time of each delay cells in the self-calibrated phase-locked loop is not only controlled by the output of the major charge pump circuit, CP1, but also the minor charge pump circuit, CP2. The delay cells consist of two adjustable output loads. One of the output loads controlled by CP1 is used to maintain the frequency control ability as a traditional phase-locked loop. Another output load is used to fine tune the output phase. The divide ratio of the frequency divider is M+ k/8. The output of the voltage-controlled oscillator would be divided by M first, and then be re-sampled by the eight output phases. If k= 1, the switch box would output the re-sampled output phases in proper sequence. At the same time, the control signals of
8
Figure 2.11: A self-calibrated phase-locked loop.