An 8-Channels 1GHz Phase-Locked Loop

Fig. 5.6 shows the block diagram of a multi-phase clock generator prototype with the VPDUs. It includes a phase-locked loop that receives a 250 MHz reference clock at Vi, and generates 8 clock outputs, φ₁· · · φ₈, with frequency at 1 GHz. The φ₁· · · φ₈ clocks have different phases that equally divide one clock period. Their phase accuracy is improved by tying them together with a resistor ring (R-Ring). The R-Ring provides a phase averaging function that can reduce the phase errors due to random device mismatches [67] [68].

Each φj clock is directed to a fine VPDU followed by a coarse VPDU to generate the Vo,j output, where j = 1, · · · , 8. Each coarse VPDU is controlled by the VH and VL

generated from 3-bits resistor-string DACs. Each fine VPDU is controlled by the VH and VLgenerated from 6-bits resistor-string DACs. Assume VDD = 1.8 V and V^SS = 0 V. The V_L is varied between 0 V and 0.5 V. The VH is varied between 1.3 V and 1.8 V. The VT H

of the M7-M8 inverter in each VPDU is 0.9 V. The delay control ranges of the coarse and fine VPDUs are designed by using different device sizes for the M1–M4 transistors in the VPDUs. The use of resistor-string DACs can ensure monotonic digital-to-delay transfer functions of the VPDUs.

For each VPDU, the required control signals, φA, φH, and φL can be generated from

φ7

Figure 5.6: A multi-phase clock generator with variable pre-charged delay units.

φ

Two 6b DACs Two 3b DACs

Figure 5.7: φ₁-V_o,1signal path.

Digital−to−Analog Converters Digital−to−Analog Converters

Multi−Phase Clock Generator

Phase Averaging R−Ring

Combinational Logic Gates

Cascaded VPDUs

Figure 5.8: Chip micrograph of the 8-channels phase-locked loop.

φ₁· · · φ₈ directly. Using the φ₁-V_o,1 signal path as an example shown in Fig. 5.7, its φ_A= φ3, φH = φ4· φ₆, and φL = φ2· φ₈. The two cascaded INV gates use the same size as the cascaded INV gates within fine VPDUs to maintain precise timing control.

5.5 Experimental Results

Fig. 5.8 shows the chip micrograph of the clock generator prototype fabricated using a standard 0.18 µm CMOS technology. It occupies an area of 1.1×1.3 mm² and dissipates 110 mW from a 1.8 V supply. The output frequency can be varied from 950 MHz to

Figure 5.9: Measured jitter performance of the 8-channels phase-locked loop.

1.05 GHz. As Fig. 5.9 shown, the measured peak-to-peak jitter is 17.5 psec and the root-mean-square jitter is 2.29 psec.

Fig. 5.10 shows the measured transfer characteristic of a fine VPDU with the corre-sponding coarse VPDU set at 4 different codes. The coarse VPDUs have a delay control resolution of 8.66 psec and a control range of 60.64 psec. The fine VPDUs have a delay control resolution of 0.145 psec and a control range of 9.14 psec. Fig. 5.11 shows the measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the digital-to-delay transfer function of a fine VPDU. The fine VPDUs can accept 64 different digital codes. Its LSB is equal to 0.145 psec. For the fine VPDU, the DNL is+0.93/ − 0.79 LSB and the INL is+0.57/ − 1.36 LSB. Fig. 5.12 shows the measured DNL and INL of a fine VPDU with larger control voltage range. The fine VPDU is operated in triode region when the input codes are smaller than 10–12. It means the Vt of the M2 and the M3 approximates 500 mV. Its LSB is equal to 0.187 psec. For the fine VPDU, the DNL is +0.93/ − 0.68 LSB and the INL is +3.56/ − 0.72 LSB.

Figure 5.10: Measured transfer curves of fine VPDU.

Figure 5.11: Measured DNL and INL of a fine VPDU with 0 V ≤ VL ≤ 0.5 V and 1.3 V ≤ V_H ≤1.8 V .

Figure 5.12: Measured DNL and INL of a fine VPDU with 0 V ≤ VL ≤ 0.6 V and 1.2 V ≤ VH ≤1.8 V .

Figure 5.13: Simulated transfer curves of 6-bits digitally controlled delay elements.

Reference Clock

Pulse Generator Oscilloscope

Aglient 86100C HP 8133A 8−Channels PLL

Digital Inputs

Figure 5.14: Measurement setup of the 8-channels phase-locked loop.

Technology TSMC 0.18 µm 1P6M CMOS

Supply voltage 1.8 V

Operation frequency 950 MHz ∼ 1.05 GHz

Tuning Range 69.78 ps @ 1 GHz

Resolution 0.145 ps @ 1 GHz

DNL ±1 LSB @ 1 GHz

INL ±1.4 LSB @ 1 GHz

Power consumption 110 mW @ 1 GHz

Jitter 2.29 ps rms @ 1 GHz

Die area 1.1 x 1.3 mm²

Table 5.1: Performance summary of the 8-channels phase-locked loop.

Fig. 5.13 shows the simulated transfer curves of 6-bits digitally controlled delay ele-ments. All of the designs are operated at 1-GHz, maximized their tuning range, and drive the same sized M3–M4 inverter. The tuning range of variable C, I, R, and VPDU are 15.8 psec, 153.7 psec, 155.9 psec, and 103.1 psec.

Fig. 5.14 shows the measurement setup. The pulse generator generates a 250 MHz clock signal. The clock signal connects to the 8-channels phase-locked loop chip for reference clock input, and also connects to the oscilloscope. The output clock of the chip connects to the other port of the oscilloscope. The delay measurement method is to measure the timing differences between selected phase and the reference clock.

Design [77] [76] This Work

Process 0.18 µm CMOS 0.18 µm CMOS 0.18 µm CMOS

Supply 1.8 V 1.8 V 1.8 V

Frequency 440 MHz ∼ 1.5 GHz <1 GHz 950 MHz ∼ 1.05 GHz Resolution <2.5 ps <2 ps 0.145 ps @ 1 GHz

Power 43 mW @ 1.5GHz Unknown 110 mW @ 1GHz

RMS Jitter 0.93 ps @ 1.5GHz Unknown 2.29 ps @ 1GHz Table 5.2: Performance comparison.

5.6 Summary

Variable pre-charged delay units can be used for adjusting the time delay of the output phases of clock generators. The delay tuning mechanism is realized by changing the charging and discharging behavior at the internal node, Vc, in VPDUs. The delay tuning of VPDUs can be more linear with a smaller channel-length modulation parameter. DACs are used for providing pre-charging voltages. Combinational logic gates are used for generating timing control signals.

To demonstrate the VPDU’s capability, an 8-phase 1-GHz clock generator was fab-ricated using a standard 0.18 µm CMOS technology. The digitally-controlled variable pre-charged delay unit has a 0.145 psec delay control resolution and a total control range of 69.78 psec. The chip occupies an area of 1.1×1.3 mm² and dissipates 110 mW from a 1.8 V supply.

Conclusions

6.1 Summary

Multi-phase clocks are usually generated by phase-locked loops and delay-locked loops.

The voltage-controlled oscillator and the voltage-controlled delay line are the most im-portant components of the clock generators to generate multi-phase clocks. They can be constructed by many different components with different methods. In CMOS techniques, the most popular design methods of the controlled oscillator and the voltage-controlled delay line are cascading delay cells as a ring or a string.

The maximum number of the output phases of multi-phase clock generators is limited by the required operation frequency of the clock generator and the minimum delay time of a delay cell. The methods which can overcome the limitation can be identified as two classifications, phase interpolation by using phase interpolator and array structure by combining several voltage-controlled oscillators or voltage-controlled delay lines. Three major methods to increase the output phases of multi-phase clock generators are two-dimensional array oscillator, phase interpolation, and delay-locked loop array.

Due to the process variation, defects of substrate, and so on, the delay cells and the MOSFETs are mismatch. The phase difference of each two adjacent output phases of multi-phase clock generators would not be equal and then phase errors occur. The meth-ods which can calibrate the phase errors are often using a calibration loop to calibrate their output phases by themselves. Three major methods for improving the quality of

77

the output phases of multi-phase clock generators are self-calibrated phase-locked loop, self-calibrated delay-locked loop, and shifted-averaging voltage-controlled delay line.

In this thesis, circuit techniques using resistor strings and resistor rings for phase av-eraging and interpolation are introduced. Resistor strings can be used for phase avav-eraging and phase interpolation. Phase averaging can reduce phase errors and phase interpolation can increase the number of available output phases. When clock phases spanning a full period are available for driving a resistor string, a resistor ring are preferred to mitigate the edge-distortion phenomenon. Capacitors on the resistor strings (or rings) can degrade the effectiveness of both phase averaging and phase interpolation. The design parame-ter β = ωi × RC need to be carefully chosen to optimize the trade-off between phase accuracy and power dissipation. Analogous to the folding ADCs, multi-phase frequency multipliers can be constructed using R-rings and folders.

The two basic building blocks, delay cells and isolation buffers, of the clock generators with phase averaging technique are introduced. Delay cells consist of symmetric loads and a self-biased replica-feedback current source. The current source can provide high output resistance without using the cascode current source for increasing the immunity to static supply noise. The symmetric load could eliminate the first-order term of the common-mode supply noise for increasing the immunity to dynamic supply noise. The isolation buffer which is a fully-differential amplifier with cross-coupled and diode-connected loads provides high output resistance. In order to demonstrate the R-ring’s capability of phase averaging and interpolation, a 125-MHz 8-bit digital-to-phase converter was designed and fabricated using a standard 0.35 µm SPQM CMOS technology. The digital-to-phase converter consists of two delay lines driving two R-rings respectively. Together, they generate 256 different clock phases. Measurement results show 8-bit resolution is possible using the R-ring technique.

In order to eliminate the phase errors completely, the design parameter β = ωⁱ × RC need to be very small. However, that would cost much power. If the expense of chip area is not a problem, the phase accuracy enhancement techniques are useful to eliminate phase errors completely. The phase accuracy enhancement techniques are often implemented by using phase detectors or statistical analysis for determining the phase errors, and insert phase shifters into each clock output paths for fine tuning the output

phases. The resolution of the phase shifters dominates the performance of the phase accuracy enhancement techniques.

Variable pre-charged delay units can be used for adjusting the time delay of the out-put phases of clock generators. The delay tuning mechanism is realized by changing the charging and discharging behavior at the internal node, Vc, in VPDUs. The delay tun-ing of VPDUs can be more linear with a smaller channel-length modulation parameter.

DACs are used for providing pre-charging voltages. Combinational logic gates are used for generating timing control signals. To demonstrate the VPDU’s capability, an 8-phase 1-GHz clock generator was fabricated using a standard 0.18 µm CMOS technology. The digitally-controlled variable pre-charged delay unit has a 0.145 psec delay control resolu-tion and a total control range of 69.78 psec. The chip occupies an area of 1.1×1.3 mm² and dissipates 110 mW from a 1.8 V supply.