Chapter 3 Nickel nanocrystals with HfO 2 blocking oxide for
3.5 Retention characteristics different with Co and Ni nanocrystals
This section discusses the retention different between Co and Ni nanocrystals
memory device. Fig. 3-7 shows the retention characteristic for Co and Ni nanocrystals
memory device. The charge loss rate of Co metal and Ni metal are 21.95% and
15.65% respectively after 104 s. The charge loss rate of Co metal is more than Ni
metal. Because Ni metal has higher work function (~ 4.96eV) than Co metal(~ 4.41eV)
as shown in Fig. 3-8. Fig. 3-8 presents band diagram of Ni and Co nanocrystals
nonvolatile memory during retention. The electrons tunnel from the Si substrate
through the tunnel oxide, and are trapped in the Co and Ni nanocrystals when device
metal nanocrystals. The band offset between SiO2 tunnel oxide and nanocrystals
become high due to high work function of metal. The higher band offset between
SiO2 tunnel oxide and nanocrystals, the more difficult electrons go back Si substrate
from nanocrystals. The work function of Ni metal is about 4.96eV. Its more than Co
metal(~ 4.41eV). Therefore the retention characteristic of Ni nanocrystals is better
than Co nanocrystals.
Fig. 3-1 Process flow of an HfO2/Ni/SiO2/Si stacked structure
Table 3-1 AFM analyses of Ni thin film.
Fig. 3-2. Cross-section TEM micrographs of an Ni/SiO2/Si stacked structure.
Fig. 3-3. The capacitance-voltage (C-V) hysteresis of Ni nanocrystals memory device after bidirectional sweeps between 4V/(-4V) and 5V/(-5V).
Fig. 3-4 Gate voltage dependence of the memory window.
Gate Voltage (V)
0 1 2 3 4 5 6 7
T hr e s h ol d vol tage shi ft ( V )
0.0 0.5 1.0 1.5 2.0 2.5
Fig. 3-5. The retention characteristics of the Ni nanocrystals memory device at room temperature.
Fig. 3-6. The endurance characteristics of the Ni nanocrystals memory device at room temperature.
Fig. 3-7 Retention for Ni and Co nanocrystals nonvolatile memory.
Fig. 3-8 Band diagram of Ni and Co nanocrystals nonvolatile memory.
Chapter 4
Fabrication and electrical characteristics of CoSi nanocrystals nonvolatile memory with HfO
2blocking oxide for memory device applications
4.1 Motivation
The lots produced nonvolatile memory devices are based on the concept of a
continuous layer of floating gate up to now [4.1]. Although many popular products are
made by nonvolatile memory devices, it still has the difficulties of continue scaling
down [4.2]. It must compromise between long-term nonvolatility and high operating
speed [4.3]. Therefore the concept of distributed storage of charge has caught a lot of
attention lately. Tiwari et al. [4.4] was the first time demonstrated the Si nanocrystal
floating gate memory device in the early nineties to solve the scaling limits of the
conventional FG structure. The nanocrystal memory device can not only maintain
good retention characteristics when tunnel oxide is thinner but also lower the power
consumption [4.4-4.13]. Direct forming of the metal nanocrystals from metal (Co,Ni)
films have many problems. For example, the size of metal nanocrystals cannot be
controlled. The metal nanocrystals have more active with other materials during the
processes. It may cause the devices failure. So we search the materials which are more
stable than metal. In this study, we demonstrated the fabrication and memory
desirable for applications of the nonvolatile memory technology.
4.2 Experimental procedures
Silicon p-type wafers [(100) orientation] were chemically cleaned by a standard
Radio Corporation of America cleaning. The 3-nm tunnel oxide was thermally grown
at 1000℃ in vertical furnace system. Subsequently, 3-nm a-Si layer and 3-nm Cobalt
layer were deposited onto the tunnel oxide by electron beam evaporation. As shown in
figure 4-1, the stacked structure was oxidized at 700℃ for 5 minutes to form CoSi
nanocrystals. The nanocrystals were identified to be CoSi phase by the analysis of
electron diffraction pattern shown in figure 4-2 [4.14]. A 30-nm-thickness blocking
oxide (HfO2) was capped by sputter. Finally, Al gate electrode was finally patterned
and sintered. The structural analyses were performed by transmission electron
microscopy (TEM). The capacitance-voltage (C-V) measurements were performed by
a precision LCR meter HP 4284A to study the electron charging and discharging
effects of the CoSi nanocrystals.
4.3 Results and discussions
Figure 4-3 shows the capacitor-gate voltage(C-V) characteristics of CoSi
nanocrystal embedded between the SiO2 and HfO2 layers. The electrical C-V
measurements are performed by bidirectional voltage sweep. In Fig. 4-3, with the
voltage swept from 9 to (-9) V and back to 9 V, a significant threshold voltage shift of
1.6 V is observed. As the swept voltage is increased to 12V, a more pronounced C-V
shift is observed. The electrons of the deep inversion layer and holes of the deep
accumulation layer were injected from the Si substrate into the nanocrystals, so that
the C-V hysteresis is counterclockwise. The high-k blocking oxide concentrates the
electric fields across the tunnel oxide and releases it across the blocking oxide under
program and erase mode. This effect leads to lower program and erase voltage. The
blocking oxide is utilized to prevent the carriers of gate electrode from injecting into
the CoSi nanocrystals by Fowler-Nordheim tunneling. In addition, the CoSi
nanocrystals do not bear a voltage drop from gate voltage, which means all the
voltages provided from control gate are dropped to tunnel oxide and control oxide and
gains advantage over their semiconductor counterparts. The inset was the
cross-section TEM of CoSi nanocrystals memory structure. It presents the structure of
Si substrate/ tunneling oxide/ CoSi nanocrystals/ HfO2 blocking oxide. The
well-separated and spherical Ni nanocrystals are observed.
In Fig.4-4, the charge retention characteristics of the CoSi nanocrystals were
measured at room temperature. If there are some leakage paths for the trapping
charges, the memory effect will gradually decrease. In Fig.4-4, the good retention
characteristics can be founded and the memory effect without significant decreasing
up to 104 s. The charge loss rate only decreases to 33.33% after 104 s. The inset was
threshold voltage shift versus time. It is clearly shown that the CoSi nanocrystals
memory has excellent retention characteristic.
The reliability of memory is major issue for nonvolatile memory devices. The
endurance of CoSi nanocrystals memory were studied by stressing samples with a
pulse voltage of ±7 V and a pulse width of 5 ms. Figure 4-5 shows the endurance
characteristics of CoSi nanocrystals memory after different stressing cycles. The
threshold voltage shift versus stressing cycles shows superior endurance. There was
no significant degradation (only 17.1%) of the threshold voltage shift observed even
after 106 P/E cycles.
4.4 Conclusions
In conclusion, the nonvolatile memory device with CoSi nanocrystals exhibits
1.6 V threshold voltage shift under 9 V write operation, which is sufficient for a
memory device to define the signal “0” and “1”. The device has a long retention time
with a small charge lose rate. Besides, the endurance of the memory device is not
degraded up to 106 write/erase cycles.
Fig. 4-1. The process flow proposed in this work.
Fig. 4-2. The electron diffraction pattern corresponding to CoSi nanocrystals.
Fig. 4-3. The capacitance-voltage (C-V) hysteresis of CoSi nanocrystals memory device after bidirectional sweeps between 9V/(-9V) and 12V/(-12V). The inset is cross-section TEM micrographs of an HfO2/CoSi/SiO2/Si stacked structure.
Gate Voltage (V)
Fig. 4-4. Data retention characteristics of the CoSi nanocrystals memory device.
Fig. 4-5. Endurance characteristics of the CoSi nanocrystals memory device.
Chapter 5
Nickel silicide nanocrystals embedded in SiO
2and HfO
2for Nonvolatile Memory Application
5.1 Motivation
Nonvolatile memory is a necessary indispensable component of modern
electronic systems. Nonvolatile memory is used in personal computers, cellular
phones, digital cameras, global positioning systems, etc. Conventional floating-gate
(FG) devices have their limitations, because of continued scaling of the device
structure. The tunnel oxide is thinner with the continued scaling down. So the
retention characteristics of memory devices may be degraded [5.1]. Recently,
memory-cell structure using discrete traps as the charge storage media has received
much attention as the promising candidate to replace conventional dynamic random
access memory or flash memories for future high speed and low power consuming
memory devices [5.2-5.3]. Nanocrystals memory devices employing distributed
nanodots as storage elements have exhibited great potential in device applications
[5.4-5.10]. Among the different materials of nanocrystals, the metal nanocrystals
memory possesses several advantages, such as stronger coupling with the conduction
channel, a wide range of available work functions, higher density of states around the
Fermi level, and smaller energy perturbation due to carrier confinement [5.3]. Besides,
using the high-k dielectric as the blocking oxide concentrates and releases the electric
fields across the tunnel oxide and the blocking oxide, respectively, under the
program/erase mode. Using a high-k dielectric as the blocking oxide leads to lower
program and erase voltage [5.11].
5.2 Experimental procedures
(100) oriented p-type silicon wafers were chemically cleaned by a standard
Radio Corporation of America cleaning, followed by formation of a 3-nm tunnel
oxide layer which was thermally grown at 1000℃ in a vertical furnace system.
Subsequently, a 3-nm amorphous silicon layer and a 3-nm-thick nickel layer were
deposited onto the tunnel oxide by electron beam evaporation, respectively. In
addition, a 10-nm amorphous silicon layer was deposited on some of the samples.
Oxidation at 800℃ 700℃ and 600 ℃ was performed at 5min, 10min and 10min
respectively to form nickel silicide nanocrystals. The 30-nm-thickness blocking oxide
(HfO2) layer was deposited by sputtering. Finally, an Al gate electrode was
patterned and sintered. Figure 5-1 presents the process flow. The structural analyses
were performed by transmission electron microscopy (TEM). The capacitance-voltage
(C-V) measurements were performed by a precision LCR meter HP 4284A to study
the electron charging and discharging effects of the nickel silicide nanocrystals.
5.3 Results and discussions
Figure 5-2 shows the forward and reverse sweep C-V characteristics, indicating
the electron charging and discharging effects of nickel silicide nanocrystals embedded
between the SiO2 and HfO2 layers. The bidirectional C-V sweeps were performed
from deep inversion to deep accumulation and in reverse, which exhibited an electron
charging effect. In Fig. 5-2, with the voltage swept from 8 to -8V and back to 8 V, an
outstanding threshold voltage shift of 0.7 V was observed. As the whisked voltage
was increased to 10V, a more obvious C-V shift of 1.3 V was seen. It is perceived that
the hysteresis is counterclockwise which is due to injection of electrons from the deep
inversion layer and injection of holes from the deep accumulation layer of Si substrate.
The resulting C-V shift indicates that the charging effects of nickel silicide
nanocrystals are more significant than that seen for semiconductor nanocrystals. The
high-k blocking oxide concentrates the electric fields across the tunnel oxide and
releases it across the blocking oxide under program and erase mode. This effect leads
to lower program and erase voltage. When the device is written or programmed, the
electrons directly tunnel from the Si substrate through the tunnel oxide, and are
trapped in the nickel silicide nanocrystals. On the other hand, as the device is erased,
the electrons may tunnel back to the deep accumulation layer of the Si substrate. The
blocking oxide is utilized to prevent the carriers from the gate electrode from being
injected directly into the nickel silicide nanocrystals by Fowler-Nordheim tunneling.
In addition, the nickel silicide nanocrystals do not exhibit a voltage drop from the gate
voltage, which means all the voltages provided from control gate are dropped to
tunnel oxide and control oxide and this provides an advantage over their
semiconductor counterparts. Figure 5-3 presents the cross-section TEM micrographs
of an HfO2/nickel silicide /SiO2/Si stacked structure with dry oxidation at 600℃. As
illustrated in Fig. 5-3, well-separated and spherical nickel silicide nanocrystals were
observed between the SiO2 layer and HfO2 layers. The nanocrystals were identified to
be a NiSi2 phase through analysis of the diffraction ring pattern shown in Fig. 5-4.
Figure 5-5 shows the capacitance-voltage (C-V) hysteresis of sample with
α-Si/Ni/α-Si structure after dry oxidation at 700℃. It was found that as the voltage
swept from 8 to -8V and back to 8 V, significant threshold voltage shift of 1.7 V was
observed. When the whisked voltage was increased to 10V, a more obvious C-V shift
of 2.1 V was seen. For samples oxidized at 600℃, these voltages were larger shift. In
figure 5-6, the voltage swept from 3 to -3V and back to 3 V, a threshold voltage shift
of 0.4 V was observed. When the whisked voltage was increased to 5V, a more
obvious C-V shift of 2 V was seen. Figure 5-7 presents the threshold voltage vs.
operation voltage for samples oxidized at different temperature. The sample which
used α–Si/Ni/α-Si structure had improved memory characteristics. As shown in
figure 5-1, the nickel silicide nanocrystals of α–Si/Ni/α-Si structure had random
distribution between SiO2 and HfO2. It was different from the α–Si/Ni conventional
device(distribution of plane) [5.10][5.12]. It shows that more charges were injected
into deep nickel silicide nanocrystals under programming mode. The charges which
were injected into deep nickel silicide nanocrystals resulted in the higher threshold
voltage. The operating voltage of the memory devices with a conventional floating
gate or semiconductor nanocrystals embedded in SiO2 is above 7V [5.13-5.14]. In our
approach to fabricate the nickel silicide nanocrystals embedded in SiO2 and HfO2, a
lower programming voltage of 4V and erasing voltage of -4 V realizes a significant
threshold voltage shift, 1.3 V, which is sufficient to be defined as “1” and “0” by a
typical sensing amplifier for a memory device.
5.4 Conclusions
A nonvolatile memory device with NiSi2 nanocrystals embedded in the SiO2 and
HfO2 layer has been fabricated. A significant memory effect is observed through the
electrical measurements. When a low operating voltage, 4V, is applied a significant
threshold-voltage shift, 1.3V, is observed. The processing of the structure is
compatible with the current manufacturing technology of semiconductor industry.
Fig. 5-1 The process flow of nickel silicide nanocrystals.
Fig. 5-2 The capacitance-voltage (C-V) hysteresis of nickel silicide nanocrystals memory device after bidirectional sweeps between 8V/(-8V) and 10V/(-10V).
Fig. 5-3 The cross-section TEM micrographs of an HfO2/nickel silicide /SiO2/Si stacked structure.
Fig. 5-4 The electron diffraction pattern corresponding to nickel silicide nanocrystals.
Fig. 5-5 The capacitance-voltage (C-V) hysteresis of sample with α-Si/Ni/α-Si structure after dry oxidation at 700℃.
Gate Voltage (V)
Figure 3b
Fig. 5-6 The capacitance-voltage (C-V) hysteresis of sample with α-Si/Ni/α-Si structure after dry oxidation at 600℃.
Dry Oxidation 800C 5min
Fig. 5-7 The memory window vs. (program/erase) voltage of nickel silicide nanocrystal memory.
Chapter 6
Using double layer CoSi
2nanocrystals to improve the memory effects of nonvolatile memory devices
6.1 Motivation
Memory devices employing distributed nanocrystals as storage elements have
exhibited great potential to replace conventional dynamic random array memory or
flash memories for future high speed and low power consumer memory devices
[6.1-6.5]. Nanocrystalline silicon was introduced as a replacement for the
conventional floating gate in the nonvolatile memory structure by Tiwari et al[6.1].
To date, most studies have focused on the fabrication on Si and Ge nanocrystals in
metal-oxide-semiconductor structure [6.6-6.11]. The use of a floating gate composed
of distributed nanocrystals reduces the problems of charge loss encountered in
conventional floating-gate electrically erasable programmable read-only memory
devices. It allows thinner tunnel oxide and, thereby, smaller operating voltages, better
endurance and retention, and faster program/erase speed [6.12-6.13].
The metal nanocrystals memory possesses several advantages, such as
stronger coupling with the conduction channel, a wide range of available work
functions, higher density of states around the Fermi level and smaller energy
perturbation due to carrier confinement [6.14]. Its implementation is compatible with
the current manufacturing technology of semiconductor industry and represents a
viable candidate for low-power nanoscaled nonvolatile memory devices. The work
function of metal silicide is lower than metal. So the electrical characteristics are not
better than metal. Therefore we demonstrated the double layer device to improve the
retention and memory windows.
6.2 Experimental procedures
In the preset study, two sets of samples were prepared. The processes flow are
as follow; (100) oriented p-type silicon wafers were chemically cleaned by a standard
RCA cleaning, followed by a dry oxidation in an atmospheric pressure chemical vapor
deposition (APCVD) furnace to form a 3-nm-thick tunnel oxide. Subsequently, a-Si
(3-nm)/Co (3-nm)/a-Si (3-nm) layers were deposited onto the tunnel oxide by electron
beam evaporation and plasma enhanced chemical vapor deposition. The compared
sample with single layer CoSi2 nanocrystals was without the a-Si (3-nm) layer. The
stacked structure was, afterwards, thermal annealing at 700 ℃ for 10min to form the
double layer CoSi2 nanocrystals. Subsequently, the 30-nm-thick HfO2 was capped on
the stacked structure. Finally, Al gate electrode was patterned and sintered. The
structural analyses were performed by transmission electron microscopy (TEM). The
capacitance-voltage (C-V) measurements were performed by a precision LCR meter
HP 4284A to study the electron charging and discharging effects of the CoSi2
nanocrystals.
6.3 Results and discussions
The inset of Fig. 6-1 represents a typical bright-field, cross-section TEM image.
After dry oxidation, the well-separated and spherical double layer CoSi2 nanocrystals
are observed. The CoSi2 nanocrystals were located between the tunnel oxide and the
control oxide. The characteristic is beneficial for the reliability and the yield of the
memory device.
Figure 6-1 shows the forward and reverse sweep capacitance-voltage (C-V)
characteristics, indicating the electron charging and discharging effects of CoSi2
nanocrystals embedded in dielectrics. The bidirectional C-V sweeps were performed
from deep inversion to deep accumulation and in reverse, which exhibited electron
charging effect. In Fig. 6-1, with the voltage swept from 5 to -5 V and back to 5 V, an
outstanding threshold voltage shift of 0.5V is observed. As the whisked voltage was
increased to 7V, a more obvious C-V shift of 1.5 V was seen. It is perceived that the
hysteresis is counterclockwise which is due to injection of electrons from the deep
inversion layer and injection of holes from the deep accumulation layer of Si substrate.
The result of C-V shift indicated that the charging effects of double layer CoSi2
nanocrystals are more significant than the semiconductor nanocrystals. Figure 6-2
shows the different memory effects of the single and double layer CoSi nanocrystals.
There are much more electrons that can be stored in the double layer than single layer
nanocrystal memory device. The retention characteristics can be seen in Fig. 6-3. The
double layer CoSi2 nanocrystals has better retention characteristic than the single layer.
The good retention characteristic of the double layer device is due to the
Coulomb-blockage effects on the top layer nanocrystals from the bottom layer
nanocrystals, as shown in Fig. 6-4 [6-15]. So, the memory effects of the nonvolatile
memory device can be improved by using the double layer nanocrystals. Figure 6-5
shows the band diagrams of “write” and “erase” operations of the double layer
nanocrystals with different gate polarities of the memory device. When the device is
written or programmed, the electrons directly tunnel from the Si substrate through the
tunnel oxide and are trapped in the top and bottom layer CoSi2 nanocrystals. When
the device is erased, the electrons may tunnel back to the deep accumulation layer of
Si substrate. The control oxide is utilized to prevent the carriers of gate electrode from
injecting into the CoSi2 nanocrystals by Fowler-Nordheim tunneling. In addition, the
CoSi2 nanocrystals do not bear a voltage drop from gate voltage, which means all the
voltages provided from control gate are dropped to tunnel oxide and control oxide and
gains advantage over their semiconductor counterparts. In our approach to fabricate
the double layer CoSi2 nanocrystals embedded in dielectrics, a lower programming
voltage of 5 V and erasing voltage of -5 V realize a significant threshold voltage shift,
which is sufficient to be defined as “1” and “0” by a typical sensing amplifier for a
memory device.
6.4 Conclusions
In summary, we have demonstrated the electron charging and discharging effects of
double layer CoSi2 nanocrystals embedded in dielectrics. The double layer CoSi2
nanocrystals were formed by the thermal annealing of the a-Si (3-nm)/Co (3-nm)/a-Si
(3-nm) multi-layer structure. A significant C-V hysteresis of voltage shift of 1.5V is
observed under voltage operation of 7V. The memory effects of the nonvolatile
memory device can be improved by using the double layer nanocrystals. The
implementation of the present structure is compatible with the current manufacturing
technology of semiconductor industry and represents a viable candidate for
low-power nanoscaled nonvolatile memory devices.
Fig. 6-1. The capacitance-voltage (C-V) hysteresis of CoSi2 nanocrystals
Fig. 6-1. The capacitance-voltage (C-V) hysteresis of CoSi2 nanocrystals