Chapter 2 Memory characteristics of Co nanocrystals memory device
2.4 Conclusions
In summary, the memory effects of the Co nanocrystals using tunneling and control
oxide, SiO2 and HfO2, were demonstrated in this letter. A significant C-V hysteresis of
Vt shift of 1V is observed under low operating voltage of 5V. The retention
characteristics are tested to be robust. Also, the endurance of the memory device is not
degraded up to 106 write/erase cycles.
Fig. 2-1 Process flow of an HfO2/Co/SiO2/Si stacked structure
Table 2-1 AFM analyses of Co thin film(scan area: 5 × 5 μm )
Fig. 2-2 The Cross-section TEM micrographs of an HfO2/Co/SiO2/Si
Fig. 2-3 The capacitance-voltage (C-V) hysteresis of Co nanocrystals memory device after bidirectional sweeps between 5V/(-5V) and 7V/(-7V).
Fig. 2-4 Gate voltage dependence of the memory window.
Gate Voltage (V)
0 1 2 3 4 5 6 7 8 9 10 11 12
T hr eshol d vol tage shi ft ( V )
0
1
2
3
4
5
6
7
Fig. 2-5 The band diagrams of the operation of the distributed charge storage with Co nano-dots.
Fig. 2-6. Data retention characteristics of the Co nanocrystals memory device.
Fig. 2-7. Endurance characteristics of the Co nanocrystals memory
Chapter 3
Nickel nanocrystals with HfO
2blocking oxide for nonvolatile memory application
3.1 Motivation
The commercial products contain poly-Si floating gate (FG) structure which is
taken as charge storage layer. Because of continued scaling of the device structure,
the tunneling oxide must thinner. Once the tunnel oxide is thinner, the electrical
characteristics such as endurance and retention may be degraded. Therefore
memory-cell structures which use discrete traps as the charge storage media have
received much attention. These memories can replace conventional dynamic random
access memory or flash memories for future high speed and low power consuming
memory devices [3.1-3.3]. Nanocrystal memory devices employing distributed
nanodots as storage elements have exhibited great potential in device applications
[3.4-3.10]. Among the different materials of nanocrystals, the metal nanocrystal
memory possesses several advantages: (1) stronger coupling with the conduction
channel; (2) a wide range of available work functions; (3) higher density of states
around the Fermi level; (4) smaller energy perturbation due to carrier confinement
[3.11]. Besides, we use the high-k dielectric as the blocking oxide. Its concentrates
and releases the electric fields across the tunnel oxide and the blocking oxide,
respectively, under the program/erase mode. At the same time, using the high-k
dielectric as the blocking oxide leads to lower program and erase voltage [3.12].In
this study,we demonstrated the memory characteristics of Ni nanocrystals embedded
in SiO2 and HfO2. Because Ni metal has higher work function (~ 4.96eV) than Co
metal(~ 4.41eV). It causes the retention different. Also Ni is compatible with the
current manufacturing technology of semiconductor industry.
3.2 Experimental procedures
Metal-oxide-silicon (MOS) capacitors were fabricated using silicon p-type wafers
[(100) orientation]. Figure 3-1 illustrates the process flow of fabricating Ni
nanocrystals. First, the wafers were chemically cleaned by a standard Radio
Corporation of America cleaning. The thin tunnel oxide (3nm) was thermally grown
at 1000℃ in vertical furnace system. Subsequently, a 3-nm-thick nickel layer was
deposited onto the tunnel oxide by electron beam evaporation. The Ni wetting layer
transformed the Ni nanocrystals after the Rapid thermal annealing (RTA) in the N2
ambient at 500℃ for 60 sec. A 30-nm-thickness blocking oxide (HfO2) was capped
by sputter. The parameter of the high-k sputtering is 0.3 Å/sec as rf power sputter in
150W under the working pressure of 20 mTorr. The flow rate of Ar/O2 is 20/5 SCCM
(SCCM denotes cubic centimeter per minute at STP). The dielectric constant of HfO2
is 20. Finally, Al gate electrode was patterned and sintered. The structural analyses
were performed by transmission electron microscopy (TEM). The capacitance-voltage
3.3 Results and discussions
(C-V) measurements were performed by a precision LCR meter HP 4284A to
study the electron charging and discharging effects of the Ni nanocrystals.
Table 3-1 presents AFM analyses of Ni thin film. Mean roughness of the Ni
metal film before and after thermal treatment are 0.229nm and 0.457nm, respectively.
It shows that the Ni nanocrystals are formed after thermal treatment. Figure 3-2 shows
the cross-section TEM of Ni nanocrystal memory structure. The figure presents the
structure of Si substrate/ tunneling oxide/ Ni nanocrystals. The well-separated and
spherical Ni nanocrystals are observed. The higher-resolution image confirms the
presence of Ni nanocrystals of approximately 5 nm in diameter. The aerial density of
the Ni nanocrystals is measured to be 3.9×1012/cm2.
Figure 3-3 presents the C-V characteristics of Ni nanocrystals embedded
between the SiO2 and HfO2 layers. It is found that a low operating voltage, 4 V,
causes a significant threshold-voltage shift up to ~ 1 V, which is sufficient to be
defined as ‘‘1’’ or ‘‘0’’ for the logic-circuit design. The electrons of the deep
inversion layer and holes of the deep accumulation layer were injected from the Si
substrate into the nanocrystals, so that the C-V hysteresis is counterclockwise. The
high-k blocking oxide concentrates the electric fields across the tunnel oxide and
releases it across the blocking oxide under program and erase mode. This effect leads
to lower program and erase voltage. The blocking oxide is utilized to prevent the
carriers of gate electrode from injecting into the Ni nanocrystals by Fowler-Nordheim
tunneling. In addition, the Ni nanocrystals do not bear a voltage drop from gate
voltage, which means all the voltages provided from control gate are dropped to
tunnel oxide and control oxide and gains advantage over their semiconductor
counterparts. Figure 3-4 presents gate voltage dependence of the memory window.
The threshold voltage shift is increased with gate voltage.
The retention characteristics of the Ni nanocrystals were measured at room
temperature, as shown in Fig. 3-5. If there are some leakage paths for the trapping
charges, the memory effect will gradually decrease. In Fig. 3-5, the good retention
characteristics can be founded and the memory effect without significant decreasing
up to 104 s. The charge loss rate only decreases to 15.65% after 104 s. It is clearly
shown that the Ni nanocrystals memory has excellent retention characteristic.
The programming characteristics of Ni nanocrystals memory were studied by
stressing samples with a pulse voltage of ±5 V and a pulse width of 5 ms during
programming and erasing (P/E). Figure 3-6 shows the endurance characteristics of Ni
nanocrystals memory after different stressing cycles at room temperature. The
threshold voltage shift as a function of stressing cycles shows superior endurance.
There was no degradation of the threshold voltage shift observed even after 106 P/E
cycles.
3.4 Conclusions
In summary, the nonvolatile memory device with Ni nanocrystals exhibits 1 V
threshold voltage shift under 4 V write operation, which is sufficient for a memory
device to define the signal “0” and “1”. The device has a long retention time with a
small charge lose rate. Besides, the endurance of the memory device is not degraded
up to 106 write/erase cycles.
3.5 Retention characteristics different with Co and Ni nanocrystals memory device
This section discusses the retention different between Co and Ni nanocrystals
memory device. Fig. 3-7 shows the retention characteristic for Co and Ni nanocrystals
memory device. The charge loss rate of Co metal and Ni metal are 21.95% and
15.65% respectively after 104 s. The charge loss rate of Co metal is more than Ni
metal. Because Ni metal has higher work function (~ 4.96eV) than Co metal(~ 4.41eV)
as shown in Fig. 3-8. Fig. 3-8 presents band diagram of Ni and Co nanocrystals
nonvolatile memory during retention. The electrons tunnel from the Si substrate
through the tunnel oxide, and are trapped in the Co and Ni nanocrystals when device
metal nanocrystals. The band offset between SiO2 tunnel oxide and nanocrystals
become high due to high work function of metal. The higher band offset between
SiO2 tunnel oxide and nanocrystals, the more difficult electrons go back Si substrate
from nanocrystals. The work function of Ni metal is about 4.96eV. Its more than Co
metal(~ 4.41eV). Therefore the retention characteristic of Ni nanocrystals is better
than Co nanocrystals.
Fig. 3-1 Process flow of an HfO2/Ni/SiO2/Si stacked structure
Table 3-1 AFM analyses of Ni thin film.
Fig. 3-2. Cross-section TEM micrographs of an Ni/SiO2/Si stacked structure.
Fig. 3-3. The capacitance-voltage (C-V) hysteresis of Ni nanocrystals memory device after bidirectional sweeps between 4V/(-4V) and 5V/(-5V).
Fig. 3-4 Gate voltage dependence of the memory window.
Gate Voltage (V)
0 1 2 3 4 5 6 7
T hr e s h ol d vol tage shi ft ( V )
0.0 0.5 1.0 1.5 2.0 2.5
Fig. 3-5. The retention characteristics of the Ni nanocrystals memory device at room temperature.
Fig. 3-6. The endurance characteristics of the Ni nanocrystals memory device at room temperature.
Fig. 3-7 Retention for Ni and Co nanocrystals nonvolatile memory.
Fig. 3-8 Band diagram of Ni and Co nanocrystals nonvolatile memory.
Chapter 4
Fabrication and electrical characteristics of CoSi nanocrystals nonvolatile memory with HfO
2blocking oxide for memory device applications
4.1 Motivation
The lots produced nonvolatile memory devices are based on the concept of a
continuous layer of floating gate up to now [4.1]. Although many popular products are
made by nonvolatile memory devices, it still has the difficulties of continue scaling
down [4.2]. It must compromise between long-term nonvolatility and high operating
speed [4.3]. Therefore the concept of distributed storage of charge has caught a lot of
attention lately. Tiwari et al. [4.4] was the first time demonstrated the Si nanocrystal
floating gate memory device in the early nineties to solve the scaling limits of the
conventional FG structure. The nanocrystal memory device can not only maintain
good retention characteristics when tunnel oxide is thinner but also lower the power
consumption [4.4-4.13]. Direct forming of the metal nanocrystals from metal (Co,Ni)
films have many problems. For example, the size of metal nanocrystals cannot be
controlled. The metal nanocrystals have more active with other materials during the
processes. It may cause the devices failure. So we search the materials which are more
stable than metal. In this study, we demonstrated the fabrication and memory
desirable for applications of the nonvolatile memory technology.
4.2 Experimental procedures
Silicon p-type wafers [(100) orientation] were chemically cleaned by a standard
Radio Corporation of America cleaning. The 3-nm tunnel oxide was thermally grown
at 1000℃ in vertical furnace system. Subsequently, 3-nm a-Si layer and 3-nm Cobalt
layer were deposited onto the tunnel oxide by electron beam evaporation. As shown in
figure 4-1, the stacked structure was oxidized at 700℃ for 5 minutes to form CoSi
nanocrystals. The nanocrystals were identified to be CoSi phase by the analysis of
electron diffraction pattern shown in figure 4-2 [4.14]. A 30-nm-thickness blocking
oxide (HfO2) was capped by sputter. Finally, Al gate electrode was finally patterned
and sintered. The structural analyses were performed by transmission electron
microscopy (TEM). The capacitance-voltage (C-V) measurements were performed by
a precision LCR meter HP 4284A to study the electron charging and discharging
effects of the CoSi nanocrystals.
4.3 Results and discussions
Figure 4-3 shows the capacitor-gate voltage(C-V) characteristics of CoSi
nanocrystal embedded between the SiO2 and HfO2 layers. The electrical C-V
measurements are performed by bidirectional voltage sweep. In Fig. 4-3, with the
voltage swept from 9 to (-9) V and back to 9 V, a significant threshold voltage shift of
1.6 V is observed. As the swept voltage is increased to 12V, a more pronounced C-V
shift is observed. The electrons of the deep inversion layer and holes of the deep
accumulation layer were injected from the Si substrate into the nanocrystals, so that
the C-V hysteresis is counterclockwise. The high-k blocking oxide concentrates the
electric fields across the tunnel oxide and releases it across the blocking oxide under
program and erase mode. This effect leads to lower program and erase voltage. The
blocking oxide is utilized to prevent the carriers of gate electrode from injecting into
the CoSi nanocrystals by Fowler-Nordheim tunneling. In addition, the CoSi
nanocrystals do not bear a voltage drop from gate voltage, which means all the
voltages provided from control gate are dropped to tunnel oxide and control oxide and
gains advantage over their semiconductor counterparts. The inset was the
cross-section TEM of CoSi nanocrystals memory structure. It presents the structure of
Si substrate/ tunneling oxide/ CoSi nanocrystals/ HfO2 blocking oxide. The
well-separated and spherical Ni nanocrystals are observed.
In Fig.4-4, the charge retention characteristics of the CoSi nanocrystals were
measured at room temperature. If there are some leakage paths for the trapping
charges, the memory effect will gradually decrease. In Fig.4-4, the good retention
characteristics can be founded and the memory effect without significant decreasing
up to 104 s. The charge loss rate only decreases to 33.33% after 104 s. The inset was
threshold voltage shift versus time. It is clearly shown that the CoSi nanocrystals
memory has excellent retention characteristic.
The reliability of memory is major issue for nonvolatile memory devices. The
endurance of CoSi nanocrystals memory were studied by stressing samples with a
pulse voltage of ±7 V and a pulse width of 5 ms. Figure 4-5 shows the endurance
characteristics of CoSi nanocrystals memory after different stressing cycles. The
threshold voltage shift versus stressing cycles shows superior endurance. There was
no significant degradation (only 17.1%) of the threshold voltage shift observed even
after 106 P/E cycles.
4.4 Conclusions
In conclusion, the nonvolatile memory device with CoSi nanocrystals exhibits
1.6 V threshold voltage shift under 9 V write operation, which is sufficient for a
memory device to define the signal “0” and “1”. The device has a long retention time
with a small charge lose rate. Besides, the endurance of the memory device is not
degraded up to 106 write/erase cycles.
Fig. 4-1. The process flow proposed in this work.
Fig. 4-2. The electron diffraction pattern corresponding to CoSi nanocrystals.
Fig. 4-3. The capacitance-voltage (C-V) hysteresis of CoSi nanocrystals memory device after bidirectional sweeps between 9V/(-9V) and 12V/(-12V). The inset is cross-section TEM micrographs of an HfO2/CoSi/SiO2/Si stacked structure.
Gate Voltage (V)
Fig. 4-4. Data retention characteristics of the CoSi nanocrystals memory device.
Fig. 4-5. Endurance characteristics of the CoSi nanocrystals memory device.
Chapter 5
Nickel silicide nanocrystals embedded in SiO
2and HfO
2for Nonvolatile Memory Application
5.1 Motivation
Nonvolatile memory is a necessary indispensable component of modern
electronic systems. Nonvolatile memory is used in personal computers, cellular
phones, digital cameras, global positioning systems, etc. Conventional floating-gate
(FG) devices have their limitations, because of continued scaling of the device
structure. The tunnel oxide is thinner with the continued scaling down. So the
retention characteristics of memory devices may be degraded [5.1]. Recently,
memory-cell structure using discrete traps as the charge storage media has received
much attention as the promising candidate to replace conventional dynamic random
access memory or flash memories for future high speed and low power consuming
memory devices [5.2-5.3]. Nanocrystals memory devices employing distributed
nanodots as storage elements have exhibited great potential in device applications
[5.4-5.10]. Among the different materials of nanocrystals, the metal nanocrystals
memory possesses several advantages, such as stronger coupling with the conduction
channel, a wide range of available work functions, higher density of states around the
Fermi level, and smaller energy perturbation due to carrier confinement [5.3]. Besides,
using the high-k dielectric as the blocking oxide concentrates and releases the electric
fields across the tunnel oxide and the blocking oxide, respectively, under the
program/erase mode. Using a high-k dielectric as the blocking oxide leads to lower
program and erase voltage [5.11].
5.2 Experimental procedures
(100) oriented p-type silicon wafers were chemically cleaned by a standard
Radio Corporation of America cleaning, followed by formation of a 3-nm tunnel
oxide layer which was thermally grown at 1000℃ in a vertical furnace system.
Subsequently, a 3-nm amorphous silicon layer and a 3-nm-thick nickel layer were
deposited onto the tunnel oxide by electron beam evaporation, respectively. In
addition, a 10-nm amorphous silicon layer was deposited on some of the samples.
Oxidation at 800℃ 700℃ and 600 ℃ was performed at 5min, 10min and 10min
respectively to form nickel silicide nanocrystals. The 30-nm-thickness blocking oxide
(HfO2) layer was deposited by sputtering. Finally, an Al gate electrode was
patterned and sintered. Figure 5-1 presents the process flow. The structural analyses
were performed by transmission electron microscopy (TEM). The capacitance-voltage
(C-V) measurements were performed by a precision LCR meter HP 4284A to study
the electron charging and discharging effects of the nickel silicide nanocrystals.
5.3 Results and discussions
Figure 5-2 shows the forward and reverse sweep C-V characteristics, indicating
the electron charging and discharging effects of nickel silicide nanocrystals embedded
between the SiO2 and HfO2 layers. The bidirectional C-V sweeps were performed
from deep inversion to deep accumulation and in reverse, which exhibited an electron
charging effect. In Fig. 5-2, with the voltage swept from 8 to -8V and back to 8 V, an
outstanding threshold voltage shift of 0.7 V was observed. As the whisked voltage
was increased to 10V, a more obvious C-V shift of 1.3 V was seen. It is perceived that
the hysteresis is counterclockwise which is due to injection of electrons from the deep
inversion layer and injection of holes from the deep accumulation layer of Si substrate.
The resulting C-V shift indicates that the charging effects of nickel silicide
nanocrystals are more significant than that seen for semiconductor nanocrystals. The
high-k blocking oxide concentrates the electric fields across the tunnel oxide and
releases it across the blocking oxide under program and erase mode. This effect leads
to lower program and erase voltage. When the device is written or programmed, the
electrons directly tunnel from the Si substrate through the tunnel oxide, and are
trapped in the nickel silicide nanocrystals. On the other hand, as the device is erased,
the electrons may tunnel back to the deep accumulation layer of the Si substrate. The
blocking oxide is utilized to prevent the carriers from the gate electrode from being
injected directly into the nickel silicide nanocrystals by Fowler-Nordheim tunneling.
In addition, the nickel silicide nanocrystals do not exhibit a voltage drop from the gate
voltage, which means all the voltages provided from control gate are dropped to
tunnel oxide and control oxide and this provides an advantage over their
semiconductor counterparts. Figure 5-3 presents the cross-section TEM micrographs
of an HfO2/nickel silicide /SiO2/Si stacked structure with dry oxidation at 600℃. As
illustrated in Fig. 5-3, well-separated and spherical nickel silicide nanocrystals were
observed between the SiO2 layer and HfO2 layers. The nanocrystals were identified to
be a NiSi2 phase through analysis of the diffraction ring pattern shown in Fig. 5-4.
Figure 5-5 shows the capacitance-voltage (C-V) hysteresis of sample with
α-Si/Ni/α-Si structure after dry oxidation at 700℃. It was found that as the voltage
swept from 8 to -8V and back to 8 V, significant threshold voltage shift of 1.7 V was
observed. When the whisked voltage was increased to 10V, a more obvious C-V shift
of 2.1 V was seen. For samples oxidized at 600℃, these voltages were larger shift. In
figure 5-6, the voltage swept from 3 to -3V and back to 3 V, a threshold voltage shift
of 0.4 V was observed. When the whisked voltage was increased to 5V, a more
obvious C-V shift of 2 V was seen. Figure 5-7 presents the threshold voltage vs.
operation voltage for samples oxidized at different temperature. The sample which
used α–Si/Ni/α-Si structure had improved memory characteristics. As shown in
figure 5-1, the nickel silicide nanocrystals of α–Si/Ni/α-Si structure had random
distribution between SiO2 and HfO2. It was different from the α–Si/Ni conventional
device(distribution of plane) [5.10][5.12]. It shows that more charges were injected
into deep nickel silicide nanocrystals under programming mode. The charges which
were injected into deep nickel silicide nanocrystals resulted in the higher threshold
voltage. The operating voltage of the memory devices with a conventional floating
gate or semiconductor nanocrystals embedded in SiO2 is above 7V [5.13-5.14]. In our
approach to fabricate the nickel silicide nanocrystals embedded in SiO2 and HfO2, a
lower programming voltage of 4V and erasing voltage of -4 V realizes a significant
threshold voltage shift, 1.3 V, which is sufficient to be defined as “1” and “0” by a
typical sensing amplifier for a memory device.
5.4 Conclusions
A nonvolatile memory device with NiSi2 nanocrystals embedded in the SiO2 and
HfO2 layer has been fabricated. A significant memory effect is observed through the
electrical measurements. When a low operating voltage, 4V, is applied a significant
threshold-voltage shift, 1.3V, is observed. The processing of the structure is
compatible with the current manufacturing technology of semiconductor industry.
Fig. 5-1 The process flow of nickel silicide nanocrystals.