The advanced nonvolatile memory devices were fabricated and investigated for
solving the problem of conventional nonvolatile memory. This dissertation is divided
into eight chapters. The contents in each chapter are described as follows.
In chapter 1, general background of nonvolatile memory devices is introduced.
In chapter 2, the memory characteristics of Co nanocrystals memory device with
HfO2 as blocking oxide is investigated.
In chapter 3, the nickel nanocrystals with HfO2 blocking oxide for nonvolatile
memory application is studied.
In chapter 4, the fabrication and electrical characteristics of CoSi nanocrystals
nonvolatile memory with HfO2 blocking oxide for memory device applications is
presented.
In chapter 5, the nickel silicide nanocrystals embedded in SiO2 and HfO2 for
nonvolatile memory application are demonstrated.
In chapter 6, the using double layer CoSi2 nanocrystals to improve the memory
effects of nonvolatile memory devices are presented.
In chapter 7, comparison electric characteristics with metal and metal-silicide
nanocrystals memory device with HfO2 as blocking oxide
Finally, the summarization of all experimental results in this dissertation and the
suggestions for the future work are presented in chapter 8.
Fig. 1-1 The structure of the conventional floating gate nonvolatile memory device. Continuous poly-Si floating gate is used as the charge storage element and ONO sandwiched structure is used as the control oxide.
Fig. 1-2 The structure of the SONOS nonvolatile memory device. The nitride layer is used as the charge-trapping element.
Fig. 1-3 The structure of the nanocrystal nonvolatile memory device. The semiconductor nanocrystals or metal nano-dots are used as the charge storage element instead of the continuous poly-Si floating gate.
Nano-Dots
Fig. 1-4 The development of the gate stack of SONOS EEPROM memory devices. The optimization of nitride and oxide films has been the main focus in recent years.
Fig. 1-5 The energy band diagrams of the write/erase operation for a SONOS device.
Chapter 2
Memory characteristics of Co nanocrystals memory device with HfO
2as blocking oxide
2.1 Motivation
Nonvolatile memory devices with floating-gate structure are being used widely, for
example, in mp3 players, digital cameras and integrated circuit cards at present. The
most prominent one is the limited potential for continued scaling of the device
structure. When the tunnel oxide is thinner, the retention characteristics may be
degraded, and when the tunnel oxide is made thicker to take the isolation into account,
the speed of the operation will be slower. There is, therefore, a tradeoff between speed
and reliability and the thickness of the tunnel oxide is compromised to about 8-11 nm,
which is barely reduced over more than five generations of the industry [2.1].
Recently, memory-cell structure using discrete traps as the charge storage media has
received much attention as the promising candidate to replace conventional dynamic
random access memory or flash memories for future high speed and low power
consuming memory devices [2.2-2.4]. Nanocrystals memory devices employing
distributed nanodots as storage elements have exhibited great potential in device
applications [2.5-2.11]. Among the different materials of nanocrystals, the metal
nanocrystals memory possesses several advantages, such as stronger coupling with
the conduction channel, a wide range of available work functions, higher density of
states around the Fermi level, and smaller energy perturbation due to carrier
confinement [2.3]. Besides, using the high-k dielectric as the blocking oxide
concentrates and releases the electric fields across the tunnel oxide and the blocking
oxide, respectively, under the program/erase mode. Using the high-k dielectric as the
blocking oxide leads to lower program and erase voltage [2.12].
In this study,we demonstrated the electron charging and discharging effects of
Co nanocrystals embedded in SiO2 and HfO2, which is desirable for applications of
the nonvolatile memory technology. The characteristic of Co metal was its high work
function about 4.41eV. Once the charge trapping in the Co nanocrystals, it was more
difficult go back from nanocrystals during retention. Also, the Co metal was
compatible with the current manufacturing technology of semiconductor industry.
2.2 Experimental procedures
Figure 2-1 presents process flow of an HfO2/Co/SiO2/Si stacked structure. (100)
oriented p-type silicon wafers were chemically cleaned by a standard Radio
Corporation of America cleaning, followed by a 3-nm tunnel oxide was thermally
grown at 1000℃ in vertical furnace system. Subsequently, a 3-nm-thick cobalt layer
was deposited onto the tunnel oxide by electron beam evaporation. The Co
nanocrystals were formed by rapid thermal annealing in the N2 ambient at 500℃ for
60 s [2.13]. The 30-nm-thick blocking oxide (HfO2) was capped by sputtering. Finally,
Al gate electrode was finally patterned and sintered. The structural analyses were
performed by transmission electron microscopy (TEM). The capacitance-voltage
(C-V) measurements were performed by an HP 4284A precision LCR meter to study
the electron charging and discharging effects of the Co nanocrystals.
2.3 Results and discussions
AFM analyses of Co thin film are listed in Table 2-1. Mean roughness of the Co
metal film before and after thermal treatment are 0.230nm and 0.471nm, respectively.
It shows that the Co nanocrystals are formed after thermal treatment. Figure 2-2
presents typical bright-field, cross-section TEM images. It shows the structure of
HfO2/Co/SiO2/Si. As illustrated in Fig. 2-2, the well-separated and spherical Co
nanocrystals embedded between the SiO2 layer and HfO2 layers were observed. The
aerial density and mean size of the Co nanocrystals are measured to be
2.13×1012/cm2.and 2 nm, respectively.
Figure 2-3 shows the forward and reverse sweep C-V characteristics, indicating the
electron charging and discharging effects of Co nanocrystals embedded between the
SiO2 and HfO2 layers. The bidirectional C-V sweeps were performed from deep
inversion to deep accumulation and in reverse, which exhibited electron charging
effect. In Fig. 2-3, with the voltage swept from 5 to -5V and back to 5 V, an
outstanding threshold voltage shift of 1 V was observed. As the whisked voltage was
increased to 7V, a more obvious C-V shift of 1.8 V was seen. It is perceived that the
hysteresis is counterclockwise which is due to injection of electrons from the deep
inversion layer and injection of holes from the deep accumulation layer of Si substrate.
The result of C-V shift indicates that the charging effects of Co nanocrystals are more
significant than the semiconductor nanocrystals. The high-k blocking oxide
concentrates the electric fields across the tunnel oxide and releases it across the
blocking oxide under program and erase mode. This effect leads to lower program and
erase voltage. Figure 2-4 presents gate voltage dependence of the memory window.
The threshold voltage shift is increased with gate voltage. Figure 2-5 shows the band
diagrams of “program” and “erase” operations with different gate polarities of the
memory device. When the device is written or programmed, the electrons directly
tunnel from the Si substrate through the tunnel oxide, and are trapped in the Co
nanocrystals. On the other hand, as the device is erased, the electrons may tunnel back
to the deep accumulation layer of Si substrate. The blocking oxide is utilized to
prevent the carriers of gate electrode from injecting into the Co nanocrystals by
Fowler-Nordheim tunneling. In addition, the Co nanocrystals do not bear a voltage
drop from gate voltage, which means that all the voltages provided from control gate
are dropped to the tunnel oxide and control oxide and gain advantage over their
semiconductor counterparts. The operating voltage of the memory devices with
conventional floating gate or semiconductor nanocrystals embedded in SiO2 is above
7V. In our approach to fabricate the Co nanocrystals embedded in SiO2, a lower
programming voltage of 5V and erasing voltage of -5 V realize a significant threshold
voltage shift, 1 V, which is sufficient to be defined as “1” and “0” by a typical sensing
amplifier for a memory device.
The retention characteristics of the Co nanocrystals were measured at room
temperature, as shown in Fig. 2-6. If there are some leakage paths for the trapping
charges, the memory effect will gradually decrease. In Fig. 2-4, the good retention
characteristics and the memory effect without significant decreasing up to 104 s can be
founded. The charge loss rate only decreases to 21.95% after 104 s. The inset shows
that the threshold-voltage shift does not significantly decrease after long time (104 s).
It is clearly shown that the Co nanocrystals memory has excellent retention
characteristic.
In addition, the reliability of the memory device was also investigated. As shown in
Fig.2-7, the data endurance of the Co nanocrystals memory device retains an obvious
memory window of 0.86 V after 106 cycles and write/erase voltage was 5/(-5) V. The
good endurance behavior of the Co nanocrystals memory device can be founded.
2.4 Conclusions
In summary, the memory effects of the Co nanocrystals using tunneling and control
oxide, SiO2 and HfO2, were demonstrated in this letter. A significant C-V hysteresis of
Vt shift of 1V is observed under low operating voltage of 5V. The retention
characteristics are tested to be robust. Also, the endurance of the memory device is not
degraded up to 106 write/erase cycles.
Fig. 2-1 Process flow of an HfO2/Co/SiO2/Si stacked structure
Table 2-1 AFM analyses of Co thin film(scan area: 5 × 5 μm )
Fig. 2-2 The Cross-section TEM micrographs of an HfO2/Co/SiO2/Si
Fig. 2-3 The capacitance-voltage (C-V) hysteresis of Co nanocrystals memory device after bidirectional sweeps between 5V/(-5V) and 7V/(-7V).
Fig. 2-4 Gate voltage dependence of the memory window.
Gate Voltage (V)
0 1 2 3 4 5 6 7 8 9 10 11 12
T hr eshol d vol tage shi ft ( V )
0
1
2
3
4
5
6
7
Fig. 2-5 The band diagrams of the operation of the distributed charge storage with Co nano-dots.
Fig. 2-6. Data retention characteristics of the Co nanocrystals memory device.
Fig. 2-7. Endurance characteristics of the Co nanocrystals memory
Chapter 3
Nickel nanocrystals with HfO
2blocking oxide for nonvolatile memory application
3.1 Motivation
The commercial products contain poly-Si floating gate (FG) structure which is
taken as charge storage layer. Because of continued scaling of the device structure,
the tunneling oxide must thinner. Once the tunnel oxide is thinner, the electrical
characteristics such as endurance and retention may be degraded. Therefore
memory-cell structures which use discrete traps as the charge storage media have
received much attention. These memories can replace conventional dynamic random
access memory or flash memories for future high speed and low power consuming
memory devices [3.1-3.3]. Nanocrystal memory devices employing distributed
nanodots as storage elements have exhibited great potential in device applications
[3.4-3.10]. Among the different materials of nanocrystals, the metal nanocrystal
memory possesses several advantages: (1) stronger coupling with the conduction
channel; (2) a wide range of available work functions; (3) higher density of states
around the Fermi level; (4) smaller energy perturbation due to carrier confinement
[3.11]. Besides, we use the high-k dielectric as the blocking oxide. Its concentrates
and releases the electric fields across the tunnel oxide and the blocking oxide,
respectively, under the program/erase mode. At the same time, using the high-k
dielectric as the blocking oxide leads to lower program and erase voltage [3.12].In
this study,we demonstrated the memory characteristics of Ni nanocrystals embedded
in SiO2 and HfO2. Because Ni metal has higher work function (~ 4.96eV) than Co
metal(~ 4.41eV). It causes the retention different. Also Ni is compatible with the
current manufacturing technology of semiconductor industry.
3.2 Experimental procedures
Metal-oxide-silicon (MOS) capacitors were fabricated using silicon p-type wafers
[(100) orientation]. Figure 3-1 illustrates the process flow of fabricating Ni
nanocrystals. First, the wafers were chemically cleaned by a standard Radio
Corporation of America cleaning. The thin tunnel oxide (3nm) was thermally grown
at 1000℃ in vertical furnace system. Subsequently, a 3-nm-thick nickel layer was
deposited onto the tunnel oxide by electron beam evaporation. The Ni wetting layer
transformed the Ni nanocrystals after the Rapid thermal annealing (RTA) in the N2
ambient at 500℃ for 60 sec. A 30-nm-thickness blocking oxide (HfO2) was capped
by sputter. The parameter of the high-k sputtering is 0.3 Å/sec as rf power sputter in
150W under the working pressure of 20 mTorr. The flow rate of Ar/O2 is 20/5 SCCM
(SCCM denotes cubic centimeter per minute at STP). The dielectric constant of HfO2
is 20. Finally, Al gate electrode was patterned and sintered. The structural analyses
were performed by transmission electron microscopy (TEM). The capacitance-voltage
3.3 Results and discussions
(C-V) measurements were performed by a precision LCR meter HP 4284A to
study the electron charging and discharging effects of the Ni nanocrystals.
Table 3-1 presents AFM analyses of Ni thin film. Mean roughness of the Ni
metal film before and after thermal treatment are 0.229nm and 0.457nm, respectively.
It shows that the Ni nanocrystals are formed after thermal treatment. Figure 3-2 shows
the cross-section TEM of Ni nanocrystal memory structure. The figure presents the
structure of Si substrate/ tunneling oxide/ Ni nanocrystals. The well-separated and
spherical Ni nanocrystals are observed. The higher-resolution image confirms the
presence of Ni nanocrystals of approximately 5 nm in diameter. The aerial density of
the Ni nanocrystals is measured to be 3.9×1012/cm2.
Figure 3-3 presents the C-V characteristics of Ni nanocrystals embedded
between the SiO2 and HfO2 layers. It is found that a low operating voltage, 4 V,
causes a significant threshold-voltage shift up to ~ 1 V, which is sufficient to be
defined as ‘‘1’’ or ‘‘0’’ for the logic-circuit design. The electrons of the deep
inversion layer and holes of the deep accumulation layer were injected from the Si
substrate into the nanocrystals, so that the C-V hysteresis is counterclockwise. The
high-k blocking oxide concentrates the electric fields across the tunnel oxide and
releases it across the blocking oxide under program and erase mode. This effect leads
to lower program and erase voltage. The blocking oxide is utilized to prevent the
carriers of gate electrode from injecting into the Ni nanocrystals by Fowler-Nordheim
tunneling. In addition, the Ni nanocrystals do not bear a voltage drop from gate
voltage, which means all the voltages provided from control gate are dropped to
tunnel oxide and control oxide and gains advantage over their semiconductor
counterparts. Figure 3-4 presents gate voltage dependence of the memory window.
The threshold voltage shift is increased with gate voltage.
The retention characteristics of the Ni nanocrystals were measured at room
temperature, as shown in Fig. 3-5. If there are some leakage paths for the trapping
charges, the memory effect will gradually decrease. In Fig. 3-5, the good retention
characteristics can be founded and the memory effect without significant decreasing
up to 104 s. The charge loss rate only decreases to 15.65% after 104 s. It is clearly
shown that the Ni nanocrystals memory has excellent retention characteristic.
The programming characteristics of Ni nanocrystals memory were studied by
stressing samples with a pulse voltage of ±5 V and a pulse width of 5 ms during
programming and erasing (P/E). Figure 3-6 shows the endurance characteristics of Ni
nanocrystals memory after different stressing cycles at room temperature. The
threshold voltage shift as a function of stressing cycles shows superior endurance.
There was no degradation of the threshold voltage shift observed even after 106 P/E
cycles.
3.4 Conclusions
In summary, the nonvolatile memory device with Ni nanocrystals exhibits 1 V
threshold voltage shift under 4 V write operation, which is sufficient for a memory
device to define the signal “0” and “1”. The device has a long retention time with a
small charge lose rate. Besides, the endurance of the memory device is not degraded
up to 106 write/erase cycles.
3.5 Retention characteristics different with Co and Ni nanocrystals memory device
This section discusses the retention different between Co and Ni nanocrystals
memory device. Fig. 3-7 shows the retention characteristic for Co and Ni nanocrystals
memory device. The charge loss rate of Co metal and Ni metal are 21.95% and
15.65% respectively after 104 s. The charge loss rate of Co metal is more than Ni
metal. Because Ni metal has higher work function (~ 4.96eV) than Co metal(~ 4.41eV)
as shown in Fig. 3-8. Fig. 3-8 presents band diagram of Ni and Co nanocrystals
nonvolatile memory during retention. The electrons tunnel from the Si substrate
through the tunnel oxide, and are trapped in the Co and Ni nanocrystals when device
metal nanocrystals. The band offset between SiO2 tunnel oxide and nanocrystals
become high due to high work function of metal. The higher band offset between
SiO2 tunnel oxide and nanocrystals, the more difficult electrons go back Si substrate
from nanocrystals. The work function of Ni metal is about 4.96eV. Its more than Co
metal(~ 4.41eV). Therefore the retention characteristic of Ni nanocrystals is better
than Co nanocrystals.
Fig. 3-1 Process flow of an HfO2/Ni/SiO2/Si stacked structure
Table 3-1 AFM analyses of Ni thin film.
Fig. 3-2. Cross-section TEM micrographs of an Ni/SiO2/Si stacked structure.
Fig. 3-3. The capacitance-voltage (C-V) hysteresis of Ni nanocrystals memory device after bidirectional sweeps between 4V/(-4V) and 5V/(-5V).
Fig. 3-4 Gate voltage dependence of the memory window.
Gate Voltage (V)
0 1 2 3 4 5 6 7
T hr e s h ol d vol tage shi ft ( V )
0.0 0.5 1.0 1.5 2.0 2.5
Fig. 3-5. The retention characteristics of the Ni nanocrystals memory device at room temperature.
Fig. 3-6. The endurance characteristics of the Ni nanocrystals memory device at room temperature.
Fig. 3-7 Retention for Ni and Co nanocrystals nonvolatile memory.
Fig. 3-8 Band diagram of Ni and Co nanocrystals nonvolatile memory.
Chapter 4
Fabrication and electrical characteristics of CoSi nanocrystals nonvolatile memory with HfO
2blocking oxide for memory device applications
4.1 Motivation
The lots produced nonvolatile memory devices are based on the concept of a
continuous layer of floating gate up to now [4.1]. Although many popular products are
made by nonvolatile memory devices, it still has the difficulties of continue scaling
down [4.2]. It must compromise between long-term nonvolatility and high operating
speed [4.3]. Therefore the concept of distributed storage of charge has caught a lot of
attention lately. Tiwari et al. [4.4] was the first time demonstrated the Si nanocrystal
floating gate memory device in the early nineties to solve the scaling limits of the
conventional FG structure. The nanocrystal memory device can not only maintain
good retention characteristics when tunnel oxide is thinner but also lower the power
consumption [4.4-4.13]. Direct forming of the metal nanocrystals from metal (Co,Ni)
films have many problems. For example, the size of metal nanocrystals cannot be
controlled. The metal nanocrystals have more active with other materials during the
processes. It may cause the devices failure. So we search the materials which are more
stable than metal. In this study, we demonstrated the fabrication and memory
desirable for applications of the nonvolatile memory technology.
4.2 Experimental procedures
Silicon p-type wafers [(100) orientation] were chemically cleaned by a standard
Radio Corporation of America cleaning. The 3-nm tunnel oxide was thermally grown
at 1000℃ in vertical furnace system. Subsequently, 3-nm a-Si layer and 3-nm Cobalt
layer were deposited onto the tunnel oxide by electron beam evaporation. As shown in
figure 4-1, the stacked structure was oxidized at 700℃ for 5 minutes to form CoSi
nanocrystals. The nanocrystals were identified to be CoSi phase by the analysis of
electron diffraction pattern shown in figure 4-2 [4.14]. A 30-nm-thickness blocking
oxide (HfO2) was capped by sputter. Finally, Al gate electrode was finally patterned
and sintered. The structural analyses were performed by transmission electron
microscopy (TEM). The capacitance-voltage (C-V) measurements were performed by
a precision LCR meter HP 4284A to study the electron charging and discharging
effects of the CoSi nanocrystals.
4.3 Results and discussions
Figure 4-3 shows the capacitor-gate voltage(C-V) characteristics of CoSi
nanocrystal embedded between the SiO2 and HfO2 layers. The electrical C-V
measurements are performed by bidirectional voltage sweep. In Fig. 4-3, with the
voltage swept from 9 to (-9) V and back to 9 V, a significant threshold voltage shift of
1.6 V is observed. As the swept voltage is increased to 12V, a more pronounced C-V
shift is observed. The electrons of the deep inversion layer and holes of the deep
accumulation layer were injected from the Si substrate into the nanocrystals, so that
the C-V hysteresis is counterclockwise. The high-k blocking oxide concentrates the
electric fields across the tunnel oxide and releases it across the blocking oxide under
program and erase mode. This effect leads to lower program and erase voltage. The
blocking oxide is utilized to prevent the carriers of gate electrode from injecting into
blocking oxide is utilized to prevent the carriers of gate electrode from injecting into