100 101 102 103 104 105 106 107
Vth(volt)
4 5 6 7 8
Program Erase
Fig. 3-15 The SONOS-TFT with nanowire structure maintains a 3V Vth window after 106 P/E cycles.
Chapter 4 Conclusion
In this thesis, we have successfully fabricated poly-Si SONOS-TFTs with various numbers of channels. The SONOS-TFTs can be used for both driving device application and nonvolatile memory application.
For driving device application, the electrical characteristics with various channel numbers and different gate dielectric are compared and discussed in Section 2-4. It is clear that he SONOS-TFT with ONO gate dielectric can provide higher on-current than the standard TFT with oxide gate dielectric. The devices with multiple nanowire channels have lower threshold voltage, steeper subthreshold slope, and superior driving ability. However, the characteristics of devices with nanowire structure are about the same as compared to the SONOS-TFT and standard TFT. Hence devices with nanowire structure are dominated by the corner effect.
For nonvolatile memory application, the memory characteristics of SONOS-TFT with ten strips nanowire (65nm) structure and a single channel (1μ m) structure are compared and discussed in Section 3-4. The results reveal that the program and erase efficiency are greatly improved in the nanowire structure
due to the larger electric field. In addition, excellent retention and endurance characteristics can be obtained. Therefore, the SONOS-TFT with nanowire structure could become a promising technology for next-generation nonvolatile memories.
Because the SONOS-TFTs have the driving capability and nonvolatile memory property at the same time, driving devices and memory devices can be integrated on the same substrate without increasing the fabrication steps. Hence, SONOS-TFTs are promising candidates for the system-on-panel (SOP) applications in the future.
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簡歷
姓 名: 蔡 佳 州
出生日期:民國七十年十一月十四日 住 址:嘉義縣布袋鎮新民里 320 號
學 歷:
國立中山大學 物理學系 (89 年 9 月-93 年 6 月)
國立交通大學電子研究所碩士班 (93 年 9 月-95 年 6 月)
論文題目:
多層閘極介電層之奈米尺度薄膜電晶體之研究
Study on Nano-Scaled Poly-Si Thin-Film Transistor with Stacked Gate Dielectric.