In this chapter, the memory characteristics for SONOS-TFT, such as program/erase efficiency, retention and endurance, will be discussed. The SONOS-TFT can be used in three dimensional memory structures and the system-on-panel (SOP) applications.
3-1 The Fabrication of SONOS-TFT
The fabrication of the SONOS-TFT with ten strips nanowire channels and a single channel are the same as described in Chapter 2-1.
3-2 The Program/Erase Mechanism
Most novel nonvolatile memories, such as nanocrystal and SONOS memories are based on the concept of Flash memory. If a datum has to be stored in a bit of the memory, there are different procedures. The threshold voltage shift of a Flash transistor can be written as [1]:
FC
T C
V =− Q
Δ (3-1)
where Q is the charge stored in the floating gate, and C is the capacitances
between the floating gate (FG) and control gate. The threshold voltage of the memory cell can be altered by changing the amount of charge present between the gate and channel, corresponding to the two states of the memory cell, i.e., the binary values (“1” and “0”) of the stored bit. Figure 3-1 [2] shows the threshold voltage shift between two states in a Flash memory. To a nonvolatile memory, it can be “written” into either state “1” or “0” by either “programming” or
“erasing” methods, which are decided by the definition of memory cell itself.
There are many solutions to achieve “programming” or “erasing”. In general, hot electron injection (HEI), Fowler-Nordheim tunneling and band to band tunneling are the three kinds of operation mechanisms employed in nonvolatile memories.
The three mechanisms will lead to difference characteristics for nonvolatile memories.
3-2-1. Hot-Electron Injection
The physical mechanism of HEI is relatively simple to understand qualitatively. An electron traveling from the source to the drain gains energy from the lateral electric field and loses energy to the lattice vibrations (acoustic and optical phonons). At low fields, this is a dynamic equilibrium condition, which holds until the field strength reaches approximately 100 kV/cm [3]. For fields
exceeding this value, electrons are no longer in equilibrium with the lattice, and their energy relative to the conduction band edge begins to increase. Electrons are “heated” by the high lateral electric field, and a small fraction of them have enough energy to surmount the barrier between oxide and silicon conduction band edges (channel hot electron, CHE). Figure 3-2 [1] shows schematic representation of HEI MOSFET and the energy-distribution function with different electrical fields. On the other hand, the effective mass of hole is heavier than one of electron. It is too hard to obtain enough energy to surmount oxide barrier. Therefore, hot-hole injection is rarely employed in nonvolatile memory operation.
3-2-2. Tunneling Injection
Tunneling mechanisms are demonstrated in quantum mechanics. Basically, tunneling injection must have available states on the other side of the barrier for the carriers to tunnel into. If we assume elastic tunneling, this is a reasonable assumption due to the thin oxide thickness involved. Namely, no energy loss during tunneling processes. Tunneling through the oxide can be attributed to different carrier-injection mechanisms, which process applies depends on the oxide thickness and the applied gate field or voltage. Direct tunneling (DT),
Fowler-Nordheim tunneling (FN), modified Fowler-Nordheim tunneling (MFN) and trap assistant tunneling (TAT) are the main programming mechanisms employed in memory [4-6] as shown in Fig.3-3.
3-3 Retention and Endurance for Nonvolatile Fresh Memory
3-3-1. Retention
In any nonvolatile memory technology, it is essential to retain data for over ten years. This means the loss of charge stored in the storage medium must be as low as possible. For example, in modern Flash cells, FG capacitance is approximately 1 fF. A loss of only 1 fC can cause a 1V threshold voltage shift. If we consider the constraints on data retention in ten years, this means that a loss of less than five electrons per day can be tolerated [1].
Possible causes of charge loss are: 1) by tunneling or thermionic emission mechanisms; 2) defects in the tunnel oxide; and 3) detrapping of charge from insulating layers surrounding the storage medium.
First, several discharge mechanisms may be responsible for time and temperature dependent retention behavior of nonvolatile memory devices.
Figure 3-4 shows a bandgap diagram of a SONOS device in the excess electron
state [7], illustrating trap-to-band tunneling, trap-to-trap tunneling, and band-to-trap tunneling, thermal excitation and Poole-Frenkel emission retention loss mechanisms. These mechanisms may be classified into two categories.
The first category contains tunneling processes that are not temperature sensitive (trap-to-band tunneling, trap-to-trap tunneling, and band-to-trap tunneling). The second category contains those mechanisms that are temperature dependent. Trapped electrons may redistribute vertically inside the nitride by Poole–Frenkel emission, which will give rise to a shift in the threshold voltage. Moreover, at elevated temperatures, trapped electrons can also be thermally excited out of the nitride traps and into the conduction band of the nitride (thermal excitation), and drift toward the tunnel oxide, followed by a subsequent tunneling to the silicon substrate.
Secondly, the generation of defects in the tunnel oxide can be divided into an extrinsic and an intrinsic one. The former is due to defects in the device structure; the latter to the physical mechanisms that are used to program and erase the cell.
Electrons can be trapped in the insulating layers surrounding the storage medium during wafer processing, as a result of the so-called plasma damage, or even during the UV exposure normally used to bring the cell in a well-defined
state at the end of the process. The electrons can subsequently detrap with time, especially at high temperature. The charge variation results in a variation of the storage medium potential and thus in channel length decrease [8].
The retention capability of Flash memories has to be checked by using accelerated tests that usually adopt screening electric fields and hostile environments at high temperature.
3-3-2. Endurance
Endurance is the number of erase/write operations that the memory will complete and continue to operate as specified in the data sheet. Generally speaking, Flash products are specified for 106 erase/program cycles.
Nevertheless, the endurance requirement may be relaxed with the increase of memory density for the other applications. Figure 3-5 shows the Endurance requirement of NAND Flash memories [9]. The endurance requirement was relaxed to 100K cycles for 256 MB density. In the higher density, a certain cell in a block has less possibility to be written and erased since the memory operation on the cell is repeated after using up the whole memory blocks. The endurance requirement is sufficient for the user to take 700 photos with a 1MB size every day for 10 years [9].
A typical result of an endurance test on a single cell is shown in Fig. 3-6 As the experiment was performed applying constant pulses, the variations of program and erase threshold voltage levels are described as “program/erase threshold voltage window closure” and give a measure of the tunnel oxide aging [8] [10].
In particular, the reduction of the programmed threshold with cycling is due to trap generation in the oxide and to interface state generation at the drain side of the channel. The evolution of the erase threshold voltage reflects the dynamics of net fixed charge in the tunnel oxide as a function of the injected charge. The initial lowering of the erase is due to a pile-up of positive charge which enhances tunneling efficiency, while the long-term increase of the erase is due to a generation of negative traps.
Moreover, a high field stress on thin oxide is known to increase the current density at low electric field. The excess current component, which causes a significant deviation from the current–voltage curves from the theoretical FN characteristics at low field, is known as stress-induced leakage current (SILC).
SILC is clearly attributed by stress-induced oxide defects, which leads to a trap assisted tunneling (see Fig. 3-7). The main parameters controlling SILC are the stress field, the amount of charge injected during the stress, and the oxide
thickness. For fixed stress conditions, the leakage current increases strongly with decreasing oxide thickness [11-13].
3-4 The Electrical Characteristics of SONOS-TFT with Multiple Nanowire Channels.
3-4-1. Program / Erase Characteristics
In this study, the devices are programmed and erased by tunneling mechanism, the program and erase conditions for NW SONOS-TFT and S1 SONOS-TFT are listed at Table 3-1. Figure 3-8 (a) and (b) present the transfer ID-VG curves of S1 and NW structures with the various program time at a 15V program voltage. It is obviously found that the program efficiency of NW SONOS-TFT is better than S1 device. Similarly, the higher program speed is also observed in NW SONOS-TFT comparing S1 SONOS-TFT at a program voltage 20V, as shown in Fig. 3-9 (a) and (b). Figure 3-10 shows the program characteristics of NW and S1 SONOS-TFTs with different gate voltage. At a programming voltage of 15V, the device with nanowire structure can achieve 2.3V Vth shift in 1 ms, which is 1000 times faster than the programming speed with S1 structure. Figure 3-11 shows the erase characteristics of NW and S1
SONOS-TFTs with different gate voltage. At an erasing voltage of -15V, the device with nanowire structure can achieve -0.6V Vth shift in 10 ms, which is about 100 times faster than the erasing speed with S1 structure.
As mentioned as the Chapter 2-4, the device with multiple nanowire channels structure has the pronounced corner effect comparing the device with a single channel (S1) structure. Since the electrical field at the corner is obviously larger than that at the surface of the channel, the electron injection into the nitride layer at the corner region is easier than surface region. Since the NW SONOS-TFT has more corner numbers, it obtains higher programming and erasing efficiency.
3-4-2. Retention
The retention characteristics of NW SONOS-TFT and S1 SONOS-TFT at 85oC are shown in Fig. 3-12 given a 20V programming voltage for 2s. It is clear that the memory window loss of NW SONOS-TFT is lower than 0.5V after extrapolating to retention time of 10 years and still kept about 3V. On the other hand, although the Vth shift of S1 SONOS-TFT is larger at the beginning and also can be kept about 3V after long retention time, the memory window degradation is more serious than NW SONOS-TFT. Therefore, the NW
SONOS-TFT can provide a better reliability for retention.
We notice that S1 device has the larger Vth shift than NW device after programmed at 85 oC. The program characteristics are contrary to that at room temperature. As shown in Fig. 3-13, the electrons are injected from channel via tunneling through the tunnel oxide (path 1) in program operation. Some of the injected electrons are captured by the traps (path 2) of the nitride (either deep traps or shallow traps), while the others will inject into the gate (path3). In nitride layer, the thermal excitation electrons may detrap from trapping states and move to blocking oxide by the field-enhanced Poole-Frenkel (P-F) emission. However, at the high temperature, electrons captured in shallow traps can easily detrap and be drawn out in the high electric field (path 4). Only the electrons in the deep traps remain in the nitride trapping layer. Due to the electrical field in NW SONOS-TFT is larger than in S1, the threshold voltage shift is mainly due to electron trapped in deep trap states. Although the electrons trapped in deep states result in the smaller memory window, a superior retention can be obtained.
3-4-3. Endurance
Fig. 3-14 (a) and (b) present the transfer ID-VG curves of S1 and NW
structures with various P/E cycles. Comparing the device with S1 structure, the device with nanowire structure has a more stable endurance characteristic. As shown in Fig. 3-15, the SONOS-TFT with nanowire structure maintains a 3V Vth
window after 106 P/E cycles.
3-5 Summary
The SONOS-TFT with the nanowire structure is proposed and fabricated for memory applications. The NW SONOS-TFT can provide significant improvement in program/erase speed compared with S1 SONOS-TFT. In addition, the retention characteristics reveal that the NW SONOS-TFT has less memory window loss at raised temperature (850C). This is because that most injected electrons are captured by the deep traps in NW structure. The endurance shows the steady electrical characteristics and the 3V memory window after 106 P/E cycles operation. Hence, the NW SONOS-TFT could become a promising technology for next-generation nonvolatile memories.
device S1(NW)
Program voltage 15 15 15 15 20 20 20 20
Program time 1ms 10ms 100ms 1s 1ms 10ms 100ms 1s Erase voltage* -15 -15 -15 -15 -20 -20 -20 -20
Erase time 1ms 10ms 100ms 1s 1ms 10ms 100ms 1s Before erase, 25V 1ms program is the first.
Table 3-1. The program / erase condition for S1 and NW SONOS-TFT.
Fig. 3-1 I–V curves of an FG device when there is no charge stored in the FG (curve A) and when a negative charge is stored in the FG (curve B).
Fig. 3-2 Schematic cross section of MOSFET. The energy- distribution function at point X1; Y1 is also shown
Φ1
Fig. 3-3 Fourth approaches to programming methods, described by Hu and White
Fig. 3-4 Bandgap diagram of a SONOS device in the excess electron state, showing retention loss mechanisms: trap-to-band tunneling (TB), trap-to-trap tunneling (T-T), band-to-trap tunneling (B-T), thermal excitation (TE) and Poole–Frenkel emission (PF)
Fig. 3-5 Endurance requirement as a function of memory capacity.
Fig. 3-6 Threshold voltage window closure as a function of program/erase cycles on a single cell.
Fig. 3-7 Anomalous SILC modeling. The leakage is caused by a cluster of positive charge generated in the oxide during erase.
VG(volt)
10-7 STD15V 1ms Program 15V 10ms Program 15V 100ms Program 15V 1s Program
Fig. 3-8 (a) The transfer ID-VG curves of S1 structures with the different program time at a 15V program voltage.
VG(volt)
Fig. 3-8 (b) The transfer ID-VG curves of NW structures with the different program time at a 15V program voltage.
VG(volt)
Fig. 3-9 (a) The transfer ID-VG curves of S1 structures with the different program time at a 20V program voltage.
VG(volt)
Fig. 3-9 (b) The transfer ID-VG curves of NW structures with the different program time at a 20V program voltage.