2-1. The Fabrication of SONOS-TFT
In this work, a series of SONOS-TFTs with multiple channel nanowire will be fabricated. The gate length is 5μm, consisting of ten stripes of multiple 65 nm nanowire (NW) SONOS-TFT, five stripes of multiple 0.2μm channels (M5) SONOS-TFT, two stripes of multiple 0.5μm channels (M2) SONOS-TFT and a single-channel (S1) SONOS-TFT with 1μm, were fabricated. The control sample, the standard TFTs with oxide dielectric was also prepared for comparison. Figure 2-1 presents the schematic plot of SONOS-TFT and Fig. 2-2 presents the TFT with oxide gate dielectric. The top view of the NW SONOS-TFT structure is shown in Fig 2-3. Figure 2-4 presents the scanning electron microscopy (SEM) photography of the poly-Si active region of the NW SONOS-TFT. Figure 2-5 presents the transmission electron microscopy (TEM) of the 65nm nanowire channel and the ONO stacked layer in the NW SONOS-TFT.
Step1. Substrate
6-inch p-type single-crystal silicon wafers with (100) orientation were used
as the starting substrate. After a standard cleaning procedure of the silicon wafers, a 400-nm-thick SiO2 was thermally grown in steam oxygen ambient at 1000ºC.
Step2. Poly-Si thin film formation
Undoped 50-nm-thick amorphous-Si layers were deposited by low pressure chemical vapor deposition (LPCVD) at 550ºC. The amorphous-Si films were recrystallized by solid phase crystallization (SPC) method at 600ºC for 24hrs in N2 ambient. After electron beam direct writing and transferred by reactive ion etching (RIE), the device active region source, drain and multiple channels were formed.
Step3. Gate dielectric formation
After defining the active region, the wafers were cleaned in H2SO4/H2O2 and NH4OH/H2O2 solution to remove residue of polymer before gate dielectric deposition. A buffered HF dip was performed to remove the native oxide on the silicon surface. A total 50 nm-thick ONO multilayer gate dielectric, 10-nm-thick layer of tetra-ethyl-ortho-silicate (TEOS) bottom oxide was deposited by LPCVD at 700ºC, 20-nm-thick layer of silicon nitride high k dielectric was deposited by LPCVD at 780ºC, 20-nm-thick layer of TEOS top oxide was deposited by LPCVD at 700ºC. The standard TFT has 50 nm-thick TEOS oxide layer
deposited by LPCVD at 700ºC. The thickness of gate oxide was determined by N&K optical analyzer.
Step4. Gate electrode formation
After deposition of gate insulators, 150-nm-thick poly-silicon films were formed immediately on the gate insulators by LPCVD at 620°C. The second poly-Si layers were patterned by E-beam lithography and transformer couple plasma (TCP) etching to define the gate electrode and to serve as the mask for self-aligned implantation.
Step5. source/drain formation
After the gate definition, the self-aligned source and drain regions were formed by phosphorous ions implantation at a dosage of 5×1015 cm-2. After the source and drain formation, doping activation was performed by rapid thermal anneal (RTA) at 900°C for 30s, in nitrogen ambient.
Step6. Passivation layer and contact hole formation
After source and drain implantation, a 300 nm-thick TEOS oxide layer was deposited as the passivation layer by LPCVD at 700ºC. The 10×10 um2 contact holes were patterned by reactive ion etching (RIE) subsequently.
Step7. Metallization
The 300-nm-thick Al-Si-Cu layers were deposited by physical vapor
deposition (PVD) and then patterned to form the gate, source and drain contact metal pads. Finally, the devices were sintered at 400°C in forming-gas ambient for 30 min.
2-2. Carrier Transport Mechanism of Poly-Si TFTs
As mentioned in Section 1-1, the device characteristics of poly-Si TFTs are strongly influenced by the grain structure in poly-Si film. Even though the inversion channel region is also induced by the gate voltage as in MOSFETs, the existence of grain structure in channel layer bring large differences in carrier mobility. Many studies on the electrical properties and the carrier transport mechanism in poly-Si TFTs have been reported. A simple grain boundary-trapping model has been described by many authors in details.[1-8] In this model, it is assumed that the poly-Si material is composed of a linear chain of identical crystallite having a grain size and the grain boundary trap density ( ). The charge trapped at grain boundaries is compensated by oppositely charged depletion regions surrounding the grain boundaries. From Poisson’s equation, the charge in the depletion regions causes curvature in the energy bands, leading to potential barriers that impede the movement of any
Lg
Nt
remaining free carriers from one grain to another. When the dopant/carrier density is small, the poly-Si grains will be fully depleted. The width of the grain boundary depletion region extends to be on each side of the boundary, and the barrier height can be expressed as
n
As the dopant/carrier concentration is increased, more carriers are trapped at the grain boundary. The curvature of the energy band and the height of potential barrier increase, making carrier transport from one grain to another are more difficult. When the dopant/carrier density increases to exceed a critical value , the poly-Si grains turn to be partially depleted and excess free carriers start to spear inside the grain region. The depletion width and the barrier height can be expressed as
g
The depletion width and the barrier height will decrease with increasing dopant/carrier density, leading to improved conductivity in carrier transport.
The carrier transport in fully depleted poly-Si film can be described by the thermionic emission over the barrier. Its’ current density can be written as[8]
⎥⎦⎤
is the barrier height without applied bias, and is the applied bias across the grain boundary region. For small applied biases, the applied voltage divided approximately uniformly between the two sides of a grain boundary. Therefore, the barrier in the forward-bias direction decreases by an amount of . In the reserve-bias direction, the barrier increases by the same amount. The current density in these two directions then can be expressed as
VB Vg
The net current density is then given by
2 )
At low applied voltages, the voltage drop across a grain boundary is small compared to the thermal voltage kT /q, Eq. (2-7) then can be simplified as
)]
where μ0 represent the carrier mobility inside grain regions. It is found that the conduction in poly-Si is an activated process with activation energy of approximately equal to , which depends on the dopant/carrier concentration and the grain boundary trap density.
qVB
Applying gradual channel approximation to poly-Si TFTs, which assumes that the variation of the electric field in the y-direction (along the channel) is much less than the corresponding variation in the y-direction (perpendicular to the channel), as shown Fig 2-6. The carrier density n per unit area (cm-2) induced by the gate voltage can be expressed as
ch
where is the thickness of the inversion layer. Therefore, the drain current of poly-Si TFT then can be given by
tch ID
Obviously, this I-V characteristic is identical to that for MOSFETs, except that the mobility is modified.
2-3. Methods of Device Parameter Extraction
In this section, we will introduction the methods of typical parameters
extraction such as threshold voltage
( )
Vth , subthreshold swing (S.S.), On/Off current ratio, field-effect mobility (μFE).2-3-1. Determination of the threshold voltage
Many methods are used to determine the threshold voltage which is the most important parameter of MOSFET. In poly-Si TFTs, the method to determine the threshold voltage is the constant drain current method. The gate voltage at a specific drain current IN value is taken as the threshold voltage. This technique is
adopted in most studies of TFTs. Typically, the threshold current
eff eff D
N W
I L
I = is
specified at 10nA for =0.1V and 100 nA for =5V in most papers to extract the threshold voltage of TFTs.
D D
V V
2-3-2. Determination of the subthreshold swing
Subthreshold swing S.S. (V/dec) is a typical parameter to describe the
required to increase/decrease drain current by one order of magnitude. The subthreshold swing should be independent of drain voltage and gate voltage.
However, in reality, the subthreshold swing might increase with drain voltage due to short-channel effects such as charge sharing, avalanche multiplication, and punchthrough-like effect. The subthreshold swing is also related to gate voltage due to undesirable factors such as serial resistance and interface state. In this experiment, the subthreshold swing is defined as one-half of the gate voltage required to decrease the threshold current by two orders of magnitude (from 10-8A to 10-9A). The threshold current is specified to be the drain current when the gate voltage is equal to the threshold voltage.
2-3-3. Determination of On/Off current ratio
On/Off ratio is another important factor of TFTs. High On/Off ratio represents not only large turn-on current but also small off current (leakage current). It affects the bright and dark states of TFT screens directly. The leakage mechanism in poly-Si TFTs is much different from conventional MOSFETs since the channel layer of poly-Si TFTs is composed of polycrystalline. A large amount of trap densities in grain structure serve as lots of defect states in energy band gap to enhance tunneling effect. Therefore, the leakage current due to
trap-assisted tunneling effect is much larger in poly-Si TFTs than in the single crystal MOSFETs.
There are many methods to specify the on and off current. The easiest one is to define the maximum current as the on current and the minimum leakage current as the off current with a drain voltage of 5V.
2-3-4. Determination of the field-effect mobility
The field-effect mobility (μFE) is determined from the transconductance at low drain voltage. The transfer characteristics of poly-Si TFTs are similar to those of conventional MOSFETs, so the first order I-V relation in the bulk Si MOSFETs can be applied to the poly-Si TFTs, which can be expressed as
gm drain current can be approximated as:
TH
G V
V >
D
The transconductance is defined as
D
Therefore, the field-effect mobility can be obtained by gm
2-4. Results and Discussion
In this section, the electrical characteristics of SONOS-TFTs and the device reliability under static stress are discussed in Sec 2-4-1 and Sec 2-4-2,
respectively.
Figure 2-7 shows the typical ID-VG transfer characteristics of standard poly-Si TFT with TEOS oxide gate dielectric and the proposed TFT (SONOS-TFT) with ONO stack gate dielectric. The standard TFT has the maximum on-current of 7.5 μA, minimum leakage current of 68 pA, and an ON/OFF ratio of 1 × 105. The SONOS-TFT has the maximum on-current increased from 7.5 μA to 17.4 μA, minimum leakage current decreased from 68 pA to 33 pA, and the current ratio increased from 1 × 105 to 5 × 105. In addition, the smaller threshold voltage and subthreshold swing (S.S.) are also obtained in
the SONOS-TFT. The enhanced performance in electrical characteristics of the SONOS-TFT is mainly attributed to the increase of the effective gate dielectric constant. By calculating the total gate capacitance composed of the parallel multilayer capacitance, the estimated effective gate dielectric constant is 5.1.
Furthermore, the accumulation of N at the SiO2/ poly-Si interface atoms and its bonding with poly-Si of active layer result a lower interface trap density [9].
In this experiment, except the increasing of the effective gate dielectric constant by using ONO multilayer, the TFTs with multiple channels were also proposed to further improve the performance. There were four different structures single-channel (S1), two stripes of multiple 0.5μm channels (M2), five stripes of multiple 0.2μm channels (M5) and ten stripes of multiple 65nm nanowires (NW) fabricated and compared. Figure 2-4 shows the SEM micrograph of the NW SONOS-TFT, including the gate, source, drain and ten multiple nanowire channels. Figure 2-5 shows the TEM micrograph and the physical width of each channel is confirmed 65 nm.
Figure 2-8 presents the transfer ID-VG curves of the proposed all SONOS-TFTs with various numbers of channels with different widths. Obviously, the NW has the highest drain current, smallest threshold voltage and the most steep sub threshold slope than others TFTs.
Figure 2-9 shows the maximum normalized drain current of the SONOS-TFTs and the standard TFTs versus the different structures at VD = 5V.
The current of the SONOS-TFTs is increased significantly from 1.7 × 10-5 A to 1.1 × 10-4 A and the standard TFTs is increased from 7.5 × 10-6 A to 7.7 × 10-5 A in order from the S1 TFT to the NW TFT. The corner effect of the devices is the main reason for the improve resent of the electrical performance. Due to the crowding of gate fringing field at the corner edges, the electrical field at the corner is obviously larger than that at the surface of the channel. The higher carrier density is induced by the lager electrical field and the better gate control ability is also obtained across the corner in previous papers [10]. The corner effect is significant as the channel number increasing and its each channel width decreasing. Therefore, the pronounced enhancement of the NW TFT is attributed the most corner numbers and its corner effect.
Figure 2-10 shows the threshold voltage (Vth) of the SONOS-TFTs and standard TFTs versus the multiple channels with different widths. The Vth is defined as the normalized drain current at 10 nA for VD = 0.1 V. The Vth of the SONOS-TFT is decreased from 3.9 V to 2.5 V and the standard TFT is decreased from 5.3 V to 3.1 V in order from the S1 TFT to the NW TFT. The improvement of Vth is mainly attributed the corner effect. As reported in [11], it is
indicated that drain current of the corner turns on earlier the surface current of channel. The additional corner current can increase the drain current, thus the Vth was reduced by the constant current definition. In Fig 2-10, the Vth is reduced with the increasing corner numbers from the S1 TFT to the NW TFT. The NW TFT structure has most corner numbers, the lowest threshold voltage can be obtained both in the SONOS-TFT and the standard TFT.
Figure 2-11 shows the subthreshold swing (S.S.) of the SONOS-TFTs and standard TFTs versus the multiple channels with different widths. The S.S. is defined as the amount of gate voltage required to increase drain current by one order of magnitude. The S.S. of the SONOS-TFT is decreased from 0.83 V/decade to 0.6 V/decade and the standard TFT is decreased from 0.93 V/decade to 0.63 V/decade in order from the S1 TFT to the NW TFT. At the sub threshold region, the corner effect can enhance the sub threshold current with additional induced electron density at the corner region [12]. Therefore, the S.S.
is reduced with the corner numbers increasing in order from the S1 TFT to the NW TFT. In addition, the current of the corner is also related to its radius, so the device with the smaller radius has the larger corner current. The simulated current of the device at the corner with different radius is reported in [11]. It is found that the sub threshold swing with NW TFT in the SONOS-TFT and the
standard are almost the same, hence the gate control ability is dominated by the corner effect in the NW TFT structure.
Figure 2-12 show the output ID-VD curves of the SONOS-TFTs versus the multiple channels with different widths at VGS = 6 V. It is apparent that the saturation drain current is dramatically increased from the S1 TFT to the NW TFT because of the corner effect. Figure 2-13 shows the output characteristics of the standard TFTs and SONOS-TFT with S1 and NW TFT structures. For S1 TFT, the maximum drain output current of SONOS-TFT is 1.35 times of standard-TFT, consisting with the gate dielectric constant ratio KONO/KSiO2 = 1.31.
However, the current of the NW TFTs is equivalent both in the SONOS-TFTs and standard TFTs without gate dielectric constant ratio KONO/KSiO2 improved effect.
This result reveals that the electrical performance of NW TFTs is dominated by the corner effect.
2-5 Summary
This chapter has proposed a high performance TFT with a nanowire structure and multilayer ONO gate dielectric. The proposed TFT with ONO gate dielectric has the better electrical properties to the standard TFT with TEOS
oxide film. Furthermore, this study applied multiple channels structures to SONOS-TFT and standard TFT to promote device performance. Experimental results indicate that the device performance enhanced with the increasing of number channels, from S1, M2, M5 to NW SONOS-TFTs, because the structure with more corner numbers and shorter radius has the better gate control by the corner effect. Therefore, NW SONOS-TFTs exhibit superior electrical performance, including the high current drivability, low threshold voltage, steep subthreshold slope and favorable output characteristics. The results also reveal that the characteristics of devices with nanowire structure are almost the same comparing the SONOS-TFT and standard TFT, hence devices with nanowire structure are dominated by the corner effect. Such TFTs are thus very promising candidates for use in future high performance poly-Si TFT application.
Fig. 2-1 The schematic plot of SONOS-TFT.
Fig. 2-2 The standard poly-Si TFT.
Fig. 2-3 The top view of the NW SONOS-TFT structure
Fig. 2-4 The scanning electron microscopy (SEM) photography of the poly-Si active region of the NW SONOS-TFT.
Fig. 2-5 The transmission electron microscopy (TEM) of the 65nm nanowire channel and the ONO stacked layer in the NW SONOS-TFT.
Fig. 2-6 A schematic MOSFET cross section, showing the axes of coordinates and the bias voltages at the four terminals for the drain-current model.
Fig. 2-7 ID-VG transfer characteristics of standard poly-Si TFT with TEOS oxide gate dielectric and the proposed TFT (SONOS-TFT) with ONO stack gate
dielectric.
Fig. 2-8 The transfer ID-VG curves of the proposed all SONOS-TFTs with various numbers of channels with different widths.
Fig. 2-9 The maximum normalized drain current of the SONOS-TFTs and the standard TFTs versus the different structures at VD = 5V.
Fig. 2-10 The threshold voltage (Vth) of the SONOS-TFTs and standard TFTs versus the multiple channels with different widths.
Fig. 2-11 The sub threshold swing (S.S.) of the SONOS-TFTs and standard TFTs versus the multiple channels with different widths.
Fig. 2-12 ID-VD curves of the SONOS-TFTs versus the multiple channels with different widths at VGS = 6 V.
Fig. 2-13 ID-VD curves of the standard TFTs and SONOS-TFT with S1 and NW TFT structures.