This thesis contains six chapters, which include design, optimization, and performance analysis of new photodiode structures for CMOS active pixel sensor (APS) imager applications, a new CMOS pixel structure called pseudo active pixel sensor (PAPS) for low-dark-current and large-array-size still imager applications, and optimization design of CMOS pseudo active pixel sensor (PAPS) structure.
Chapter 1 introduces the background, describes the research motivation, and explains the main topics of this thesis.
In Chapter 2, a brief description of photodetectors in CMOS image sensors is outlined and their developments are reported. Then, the structures and operational requirements of CMOS image sensor are discussed. Finally, we will discuss and review the pixel circuits in CMOS image sensors including the state-of-the-art structures.
In Chapter 3, two new photodiode structures with low dark current and high spectral response are proposed. The pn junction of p-substrate and the lightly-doped sensor implant SN− is used as a photodiode in both structures. The regions of bird’s beak in the two proposed structures are completely embraced by the SN− implant and the p-field implant, thus not located in the pn junction depletion region. Both pn junction depletion located under the bird’s beak and surface damage due to high doping concentration can be avoided and the generation of dark current can be suppressed. Furthermore, the use of shallow and deep pn junctions can increase the photo-sensitivity for light of short and long wavelengths, respectively. Thus the spectral response can be improved. Systematic comparisons on measurement results of dark currents and spectral responses among the proposed photodiode structures and
other structures in CMOS technology with reasonable process modifications are presented. From the experimental results, it has been verified that the two proposed structures in the 5 µm x 5 µm APS cell of the CMOS imager have low dark currents of 30.6 mV/sec and 35.2 mV/sec at the reverse-biased voltage of 2 V as well as good spectral response. The two proposed photodiode structures have lower dark current and higher spectral response as compared to the conventional structure and other photodiode structures.
In Chapter 4, a new pixel structure called the pseudo active pixel sensor (PAPS) for the large-array-size still CMOS imagers with low dark current and high fill factor is proposed. A new readout circuit is also proposed to readout the sensor current to the column bus and performs the outside-pixel integration using the APS-like structure.
The new readout circuit keeps the biases of both photodiode and parasitic pn junctions in the column bus at or near zero bias to achieve low dark current, low column leakage current, and high linearity. The improved double delta sampling (DDS) circuit is used to reduce fixed pattern noise, clock feedthrough noise, and the noise from the effect of channel charge injection. An experimental chip of the proposed PAPS CMOS imager with the format of 352 x 288 (CIF) has been fabricated by using 0.25 µm single-poly-five-level-metal (1P5M) N-well CMOS process. The pixel size is 5.8 µm x 5.8 µm. The pixel readout speed is from 100 kHz to 10 MHz, corresponding to the maximum frame rate above 30 frames/sec. The proposed still CMOS imager has a fill factor of 58%, chip size of 3110 µm x 2760 µm, and power dissipation of 24 mW under the power supply of 3.3 V. The experimental chip has successfully demonstrated the function of the proposed new PAPS structure. It can be applied in the design of large-array-size still CMOS imager systems with low dark current and high resolution.
In Chapter 5, the optimal design of the structure of PAPS for the large-array-size
CMOS imagers with low dark current is presented and analyzed. In the proposed optimal PAPS (OPAPS) structure, a buffer circuit called the zero-biased buffer direct injection (ZBBDI) is shared by limited number of pixels to keep the photodiodes at zero or near zero bias and readout the selected pixel current [37]. Then the integration of readout current is performed by using an APS-like circuit. A new factor called the photocurrent-to-dark-current ratio per pixel area (PDRPA) is defined and optimized for the OPAPS structure. In the OPAPS design, both column sampling circuit and output correlated double sampling (CDS) circuit are used to reduce fixed pattern noise, clock feedthrough noise, and the noise from the effect of channel charge injection. An experimental chip of the proposed OPAPS CMOS imager with the format of 352 x 288 (CIF) has been designed and fabricated by using 0.25 µm single-poly-five-level-metal (1P5M) N-well CMOS process. In the fabricated CMOS imager, one shared zero-biased-buffer is used for four pixels where the PDRPA is equal to 47.29 µm-2. The fabricated OPAPS CMOS imager has a pixel size of 8.2 µm x 8.2 µm, fill factor of 42%, and chip size of 3630 µm x 3390 µm. Moreover, the measured maximum frame rate is 30 frames/sec and the dark current is 82 pA/cm2. Additionally, the measured optical dynamic range is 6 5dB. It is found that the proposed OPAPS structure has lower dark current, higher fill factor, and higher optical dynamic range as compared with the active pixel sensor (APS) and the conventional passive pixel sensor (PPS). Thus the proposed OPAPS structure has high potential for the applications of high-quality and large-array-size CMOS imagers.
Finally, the main results and conclusions of this thesis are summarized in Chapter 6. Some suggestions for the future works about the implementations of photodiode structure, pixel circuits, and readout circuits are also addressed in this chapter.
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