CONCLUSIONS AND FUTURE WORKS 1
6.2 FUTURE WORKS
In the proposed two new photodiode structures, the dark current has been reduced and the spectral response has been improved. In future research, the integration of the proposed photodiode structures with APS, PAPS, and OPAPS imagers will be performed. Although, more costs are needed in the use of the proposed photodiode structures because the additional mask of SN− is used, a good design trade-off between cost and performance can be obtained.
In the proposed PAPS pixel structure for the still CMOS imager application, the integration time can be adjusted according to the background light intensity. If high frame rate is required, the background light intensity should be increased to decrease the required integration time. Thus, in order to use the proposed PAPS CMOS imager with the frame rate as fast as that of APS CMOS imager, the appropriate background light is needed. In the future, low noise current amplifier with background current suppression can also be developed and designed to amplify the photocurrent, suppress background current, and improve the performance of frame rate. The proposed PAPS CMOS imager can also be applied in nano CMOS technology because the pixel size can be further shrunk due to its high fill factor and low dark current. In addition, it can be combined with biochemical reactions to form biochip.
In the proposed OPAPS pixel structure, it is a design trade-off between dark current and frame rate. However, the pixel size cannot be greatly shrunk in the used CMOS technology due to the distance between two N-wells with different potentials.
Although the distance can be further shrunk depending on the fabricating fabs., the
noise coupling between the two N-wells will degrade the image performance. Thus more different pixel shape like the hexagon and one buffer shared by more pixels can be developed and designed to decrease the effective pixel size while keeping the image performance.
In the fabricated PAPS and OPAPS CMOS imager chips, on-chip A/D conversion is replaced by a data acquisition card with the function of A/D converter. The on-chip A/D conversion is an advanced circuit technology which is applied to CMOS imager chips more recently [22], [88], [91]. Through the conversion, the digital output signal of CMOS imager chips instead of analog one can avoid noise coupling during signal transferring out of imager chips. Thus the system design can be simplified and the cables and IC chip counts can be reduced. However, the additional power and area consumptions may not be acceptable in some applications. Thus, the on-chip A/D conversion is usually used in high-performance applications. Some new structures of on-chip A/D conversion have been proposed for the design of CMOS imagers [22], [91].
In this thesis, new photodiode structures for CMOS active pixel sensor (APS) imagers and new CMOS pixel structures for low-dark-current and large-array-size imager applications are proposed, analyzed, and designed. All the structures and technologies discussed above have their uniqueness and features for different applications. Due to the development of new photodiode structures and pixel circuits and the fast advancement of CMOS technologies, high-performance and low-cost CMOS imaging system will be developed through the inventions of new device structure and circuit techniques. With innovative development of CMOS imager chips, a new generation of CMOS imaging systems is highly expected.
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