LOW-DARK-CURRENT AND LARGE-ARRAY-SIZE STILL IMAGER APPLICATIONS
4.4 SIMULATION AND EXPERIMENTAL RESULTS
The simulation results of the voltage at node of D and the voltage difference
between Vout_r and Vout_s of the output CDS circuit in Fig. 4.7 are shown in Figs.
4.10(a) and 4.10(b), respectively, where the input photocurrent is from 20 pA to 80 pA under the readout frame rate of 30 frames/sec. As may be seen from these figures, the linearity of the readout circuit is greater than 90% and the maximum output swing is equal to 1.29 V. The readout speed is from 100 kHz to 10 MHz, corresponding to the maximum frame rate above 30 frames/sec.
In the experimental chip, a CIF CMOS imager using the proposed PAPS structure is designed and fabricated by using 0.25 µm 1P5M N-well CMOS process.
The depth of N+ diffusion, P+ diffusion, N-well, and deep N-well of this CMOS process are summarized in Table 4.5. The pixel size is 5.8 µm x 5.8 µm and can be further shrunk. The layout diagram of a single pixel is shown in Fig. 4.11 where the source of row select transistor is connected directly to the P+ diffusion of the photodiode without contacts to increase sensor area and fill factor. The corner of the photodiode is clipped at 135° to reduce the effect of leakage current at the right angle.
The fill factor in the PAPS pixel is 58% that is larger than that of APS pixel reported so far. The fill factor can be designed larger by moving the N-well contact outside the pixel. Thus the pixel size in the proposed PAPS structure can be designed smaller than that of APS pixel if their fill factor is the same.
To obtain the uniform characteristics of the sensor array, two layers of dummy photodiodes are added around the active sensor array. The P+ regions of the dummy photodiodes are connected to N-well to maintain zero bias such as the photodiodes in the active sensor array. The dummy photodiodes are completely shielded by metal 5.
In addition, double guard rings are inserted around the sensor cell array to reduce substrate coupling of the digital switching noise. The analog-to-digital converter is not implemented to simplify the design of the test chip. The final chip photograph is shown in Fig. 4.12 where the area except the regions of sensor and capacitor are
covered by metal 5 from light shielding. The total chip size is 3110 µm x 2760 µm.
To test the fabricated CIF PAPS CMOS imager chip, a data acquisition card with the function of A/D converter is utilized to capture the image. The measurement setup of image pattern, lens, and imager chip is shown in Fig. 4.13. The original image and the measured grayscale image captured by the fabricated 352 x 288 (CIF) PAPS CMOS imager chip under the white light intensity of 24 lux and Vcom of 1.79 V are shown in Fig. 4.14(a) and 4.14(b), respectively. The blurs produced in Fig. 4.14(b) is due to light bulb and can be avoided by using more uniform light sources. The measured images under the white light intensity of 24 lux and different values of Vcom are shown in Figs. 4.15(a)-(h). When the value of Vcom is 1.79 V, the image quality in Fig. 4.15(a) is good and no observable fixed pattern noise is presented. With the decrease of Vcom from 1.79 V to 1.45 V as shown in Figs. 4.15(b)-(h), the image quality is degraded by the effect of leakage current in the parasitic pn junctions of deselected row switches. The image cannot be clearly seen when the value of Vcom is smaller than 1.45 V because the leakage current from the parasitic pn junctions of deselected pixels is larger than the photocurrent from the selected pixel. Thus the function of the proposed new PAPS CMOS imager is successfully verified.
The measurement results of the proposed PAPS CMOS imager with the value of Vcom equal to 1.79 V are summarized in Table 4.6 where the corresponding parameters of the APS CMOS imager are also given for comparisons. The total power dissipation of the fabricated CMOS imager chip is equal to 24 mW under the power supply of 3.3 V. Dark current was measured by varying the master clock rate and thus linearly controlling the integration time in the dark [99]. An output-referred dark-current-induced-signal of 5.8 mV/sec was measured at room temperature. Based on the conversion gain, the dark current in PAPS CMOS imager is equal to 93 pA/cm2 which is smaller than that of APS [100], [101] and PPS CMOS imager. The output
swing of 1.2 V is smaller than that of simulation results because of the process variations in the threshold voltage of MOSFETs. The photo-sensitivity is shown in Fig.
4.16 and is equal to 0.16 V/lux⋅s after calculations. The optical dynamic range defined as the ratio of the brightest illuminance without reaching the saturation level of output voltage to the weakest with the output voltage larger than noise level is equal to 72 dB.
The sensitivity in the PAPS CMOS imager is smaller than that of APS and PPS CMOS imager due to the low quantum efficiency of P+/N-well photodiode. But the optical dynamic range in PAPS CMOS imager is larger than that of APS [100], [101]
and PPS CMOS imager because the dark current in PAPS structure is smaller and the use of the optional capacitor of Cint in Fig. 4.4. There are two sources of FPN, namely, pixel FPN, which is caused by mismatch in the pixel circuit, and column FPN, caused by mismatch in the column readout circuit [100]. The fixed pattern noise (FPN) is 5.3 mV which is smaller than that of APS CMOS imager with DDS circuits [100] due to the larger pixel FPN in APS CMOS imager although the PAPS CMOS imager has major FPN due to column differences which is larger than that of APS CMOS imager.
Thus the proposed PAPS CMOS imager can be used in the low-dark-current and high-resolution still imager applications by keeping the value of Vcom equal to or slightly smaller than 1.8 V.
4.5 SUMMARY
In this chapter, a new pixel structure for still CMOS imager application called the pseudo active pixel sensor (PAPS) structure has been proposed and analyzed. In the PAPS structure, the PPS-like pixel circuit, the APS-like column circuit, and the new readout structure called the zero-bias column buffer-direct-injection (ZCBDI) are used to reduce column leakage current, decrease pixel area, and increase fill factor.
The gain loss in the source follower of NMOS devices can be avoided by using the mask of deep N-well to increase the output voltage dynamic range. The improved double delta sampling (DDS) circuits are also used to suppress fixed pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of CIF PAPS CMOS imager is designed, fabricated, and measured. The measurement results verify the function of the new proposed PAPS structure.
With the advantageous characteristics of small pixel area, high fill factor, and low dark current, it is expected that the proposed new PAPS CMOS imager structure can be applied to the design of high-quality and large-array-size still CMOS imagers.
Table 4.1 The values of Id1, Id2, Ip1, Ip2, Ip1/Id1, and Ip2/Id2
Id1 0.13 fA
Id2 18.10 fA
Ip1 570 fA
Ip2 880 fA
Ip1/Id1 4384.61
Ip2/Id2 48.62
Table 4.2 The values of ISP, IS1, IS2, α, and width/length of Mrsel
ISP 1.97×10-17 A
IS1 4.20×10-22 A
IS2 3.02×10-20 A
α 0.99
width/length of Mrsel 0.50 µm / 0.35 µm
Table 4.3 The device parameters in the circuit diagram of the gain stage
Width/length
Mp1 0.78 µm / 0.30 µm
Mp2 0.60 µm / 0.65 µm
Mp3 0.60 µm / 0.65 µm
Mn1 0.58 µm / 0.90 µm
Mn2 0.58 µm / 0.90 µm
Table 4.4 The values of Chold, V1LSB, GPGA, Ileak, and Tint
Chold 0.24 pF
V1LSB 0.3 mV
GPGA 8
Ileak 0.45 fA
Tint 30 ms
Table 4.5 The depth of N+ diffusion, P+ diffusion, N-well, and Deep N-well in 0.25 µm 1P5M N-well CMOS process
N+ diffusion 0.1 µm
P+ diffusion 0.1 µm
N-well 1.2 µm
Deep N-well 2.5 µm
Table 4.6 The measurement results of the proposed PAPS CMOS imager with the value of Vcom equal to 1.79 V and its comparisons with that of APS CMOS imager [101]
Pixel Structure PAPS APS [101]
Technology 0.25 µm 1P5M N-well CMOS 0.35 µm 1P3M N-well CMOS
Power Supply 3.3 V 3.3 V
Integration Capacitor 8.2 ~ 208.2 fF −
Output Swing 1.2 V 0.8 V (estimate)
Readout Speed 30 frames/sec 30 frames/sec
Linearity 92% 80% (estimate)
Dark Current 93 pA/cm2 (room temperature) 370 pA/cm2 (room temperature)
Photo-sensitivity 0.16 V/lu⋅s 0.52 V/lu⋅s
Optical Dynamic Range 72 dB 53 dB
Fixed Pattern Noise (FPN) 5.3 mV 8 ~ 24 mV (estimate)
Chip Size 3110 µm x 2760 µm 5840 µm x 5010 µm
Pixel Area 5.8 µm x 5.8 µm 7.4 µm x 7.4 µm
Array Size 352 x 288 (CIF) 640 x 480
Area of Pixel Array 2041.6 µm x 1670.4 µm 4736 µm x 3552 µm
Fill Factor 58% 25% ~ 40% (estimate)
Fill Factor / Pixel Area 0.0172 µm-2 0.00457 µm-2 ~ 0.0073 µm-2 (estimate)
Operating Temperature 25°C 25°C
Power Dissipation 24 mW 31 mW
Vpix
light
photocurrent
Rsel
Mrsel
column bus (Vcom) A
Fig. 4.1 The circuit of the pseudo active pixel sensor (PAPS).
-6 -5 -4 -3 -2 -1 0
-40 -30 -20 -10 0
Dark current Id (fA)
(0 , Id1)
(-3 , Id2)
Reverse-biased voltage VR of photodiode (volts)
(a)
-6 -5 -4 -3 -2 -1 0
Reverse-biased voltage VR of photodiode (volts)
(b)
Fig. 4.2 The measured (a) dark current Id and (b) photocurrent Ip of the fabricated P+/N-well photodiode.
N-well (Vpix)
Fig. 4.3 The circuit diagram of PAPS when the row select switch of Mrsel is off.
Iin
_
+
A
Vdd
Vb1 Mp2 Pixel circuit
1.8V Other
off pixels
Rsel
Mrsel 3.3V
CB