Improved Double Delta Sampling (DDS) Operation Circuit

The improved DDS operation circuit is shown in Fig. 4.7. The column sampling circuit is used in each column whereas the output CDS circuit is shared by all the columns. In the column sampling circuit as shown in Fig. 4.7, the NMOS devices of MS and MR controlled by the signals of SHS and SHR, respectively, are sampling switches whereas Mvce controlled by Vce is the equalization switch. The signals generated by the integration of photocurrent and the reset signal transferred through the source follower Mp1/Mp2 are sampled by the two NMOS devices of MS and MR, respectively. Both the effects of clock feedthrough and channel charge injection resulted from the sampling operation of MS and MR in the original DDS circuit [99]

will degrade the performance of signal readout. In the improved DDS circuit of Fig.

4.7, the effect of signal-dependent channel charge injection caused by MS and MR during the falling edges of SHS and SHR is reduced by the two added dummy NMOS devices Ma and Mb with their drain and source connected together and their gates connected to the outputs of the two inverters invA and invB, respectively. The size of Ma and Mb is designed to be about one half of the size of MS and MR, respectively, because only the channel charges injected to the source regions of MS and MR are to be compensated by those to both drain and source regions of Ma and Mb, respectively.

The signals after the sampling are held at the nodes of A and B until they are readout to the output CDS circuit when the column switches Mn1 and Mn3 are on.

Since the column readout sampling is performed simultaneously in each column and the sampled column signals are readout to the output CDS circuit successively, the signal from the last column is held for the longest time that is almost equal to the integration time of the photocurrent. The held signal voltages at the last column will be decreased by the leakage currents at the nodes of A and B. An extra capacitor of 0.12 pF is added to the nodes of A and B to avoid the held voltage level from decreasing lower than 1 LSB of the output analog-to-digital converter. The extra capacitor of 0.12 pF is determined by the leakage current Ileak at the nodes of A and B, the gain GPGA of the programmable gain amplifier (PGA) before the A/D converter, the node capacitances at the nodes of A and B Chold, and the integration time of photocurrent Tint. The equation can be represented as

(Chold + 0.12 pF) V1LSB = GPGA (Ileak x Tint) (4.7) The values of Chold and Ileak are determined from the process parameter. All the values of Chold, V1LSB, GPGA, Ileak, and Tint are summarized in Table 4.4.

The photosignal (reset) voltage is sampled to the gate of Mn2(Mn4) of the second source follower composed of Mn2, Mn1, and Mn5(Mn4, Mn3, and Mn6) and sent out to the output CDS circuit through the column select switches Mn1(Mn3), Csela, and Cselb. The second source follower is composed of NMOS devices because PMOS devices are used in the first source follower. Thus the voltage dynamic range at the output of the second source follower is not reduced by the level shifting of threshold voltage. In the conventional N-well CMOS process, the substrates of all NMOS devices must be connected to the ground together due to the use of a single P-well. Under this circumstance, the source follower composed of NMOS devices suffers from the gain attenuation due to the body effect. However, the 0.25 µm 1P5M CMOS technology used in the design of the imager chip has the mask of deep N-well beneath the P-well. In other words, the potential of the P-well at the top of deep

N-well can be set to any value. Thus the substrates of Mn2 and Mn4 can be connected to their source and the gain in the NMOS source follower is not attenuated by the body effect. The dynamic range of the output voltage is almost equal to that of the voltage at the integrating capacitor although two types of the source follower are used in the design of column readout circuit. The equalization of both photosignal path and reset signal path controlled by Vce is performed after the readout of the held voltage.

The equalized voltage at the two nodes of A and B is then readout to the output CDS circuit.

To reduce the load of the column sampling circuits to the output CDS circuit in the high-resolution CMOS imager and increase the readout speed, every eight column switches are connected together to one switch Csela whereas eight Csela switches are further connected to one switch Cselb [99]. In the output CDS circuit, the NMOS devices Mn7(Mn8) controlled by the signal Clamp is to clamp the voltage at the gate of Mp3(Mp5) in the output source follower Mp3 and Mp4 (Mp5 and Mp6) to Vb3.

The capacitor of 2.3 pF are used to perform the operation of correlated double sampling (CDS).

The major operational timing diagram is shown in Fig. 4.8. Firstly, the row select signal Rsel#1 is low and the Reset control signal is high to reset the voltage at the integrating capacitor to 0 V. After the reset operation, the photocurrents of all pixels in the Row#1 are integrated at the gate of Mp1 of Fig. 4.7 during the integration time. Then the control signal of SHS is on to sample the photo-signal in the output of the first source follower Mp1/Mp2 to the node A of Fig. 4.7 as VS. After that, the Reset control signal is on again and then the control signal of SHR is on to sample the reset signal in the output of the first source follower to the node B of Fig.

4.7 as VR when the Reset control signal is off. As in the APS structure, the duration of reset time is kept long enough to eliminate the amount of residual charges due to

incomplete reset. That is, the amount of KTC noise generated by the trapping of the switch thermal noise in the integration-reset function at the node D of Fig. 4.7 is the same in VS and VR if the settling time of the voltage at the node D of Fig. 4.7 during the reset operation is shorter than the reset time [86]. Thus the KTC noise due to the reset operation can be reduced by the CDS operation. The reset signal must be sampled after the Reset control signal is off because the effect of clock feedthrough on VS and VR from the Reset control signal is the same which can be reduced by the CDS operation. The integration time Tint and frame rate are expressed as

Tint = NTodr (4.8) Frame rate = 1/[M(N+3)Todr] (4.9) where M, N, and Todr are row number of imager, column number of imager, and the reciprocal of output data rate, respectively. The registration time of one image is equal to the reciprocal of frame rate.

In the still imager application, the integration time can be adjusted according to the background light intensity. The photo-generated charges in the PAPS CMOS imager can be the same as that in the conventional APS CMOS imager by increasing the integration time. Under this circumstance, the value of signal-to-noise ratio (SNR) is increased due to the lower dark current which leads to lower shot noise. But the frame rate is smaller than that of APS CMOS imager. If high frame rate is required, the background light intensity should be increased to decrease the required integration time. Under this Circumstances, the optional capacitor Cint is not used because the voltage saturation at the node D of Fig. 4.4 will not be occurred.

The clamp signal in the output CDS circuit is then turned on to clamp the gate voltages of MP3 and MP5 to Vb3. Then, Csel, Csela, and Cselb are on to transfer the signal from the column sampling circuit to the output CDS circuit. Finally, Clamp is off and Vce is on, the voltage at both nodes of A and B of Fig. 4.7 becomes

(VS+VR)/2. If no loss in the stored charges of the capacitor, then the voltage change at the capacitor of 2.3 pF is transferred to the output node of the output source follower composed of Mp3 and Mp4(Mp5 and Mp6) as shown in Fig. 4.7. Thus we have [99]

2 Vb3 VS

Vout_s≅ VR− + +Vcf,Mvce+VSG,Mp3 (4.10)

2 Vb3 VR

Vout_r≅ VS− + +Vcf,Mvce+VSG,Mp5 (4.11)

where V^cf,Mvce is the effect of clock feedthrough on the node of A and B of Fig. 4.7 when the MOSFET of Mvce is on and VSG,Mp3(VSG,Mp5) is the voltage drop between source and gate of Mp3(Mp5). As may be seen from (4.10) and (4.11), the CDS operation is realized in the output CDS circuit. The fixed pattern noise in the NMOS source follower of column sampling circuit can be reduced by this CDS operation.

The two output signals are sent out and subtracted each other by the subtraction circuit in the off-chip data acquisition (DAQ) card. Thus the complete operation of the double delta sampling circuit is realized. The fixed pattern noise caused in the PMOS source follower of ZCBDI circuit in Fig. 4.7 can be reduced by the subtraction in DAQ card. The effect of clock feedthrough by switching the signal of Vce to equalize the voltages at the two nodes of A and B can also be reduced from the subtraction.

The final result after the subtraction of DAQ card can be written as [99]

VR VS Vout_s

Vout_r− ≅ − + V^SG,Mp5 − VSG,Mp3 (4.12)