O RGANIZATION

This thesis is organized into seven chapters and this introduction is the first one.

Chapter 2 introduces design issues for mixed-voltage I/O interface and prior solutions.

Chapter 3 describes the design of mixed-voltage I/O interface using floating n-well and gate-tracking circuit. Chapter 4 presents the conventional crystal oscillator circuit and a new idea of mixed-voltage crystal oscillator circuit I with an extra control signal.

In chapter 5, a new mixed-voltage crystal oscillator circuit II without an extra control signal is proposed. In chapter 6, the experimental results are shown. Finally, chapter 7 summarizes this work and discusses the further works.

Table 1.1

Key Features of the Semiconductor Scaling Trend (High-Performance Logic Technology) [1]

2006 2007 2008 2009 2010 2011 2012

Gate Length, L (nm) 28 25 22 20 18 16 14

Oxide Thickness, tox (Å) 11 11 9 7.5 6.5 5 5

Power Supply Voltage,

VDD (V) 1.1 1.1 1 1 1 1 0.9

Threshold Voltage, Vt

(mV) 168 165 160 159 151 146 148

NMOS Drain Current

(μA/μm) 1130 1200 1570 1810 2050 2490 2300

Fig. 1.1 Power supply voltage and I/O voltage on different technology generation.

ig. 1.2 The diagram of hot-carrier effect.

F

Chapter 2

Prior Designs of Mixed-Voltage I/O Buffer

In this chapter, the conventional I/O buffer and the issues in mixed-voltage I/O interface are introduced first, and then the prior solution concept is presented. Finally, a mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit reported in [14] is introduced before the proposed reliable mixed-voltage I/O buffers in the thesis. The mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit is designed to be tolerant of 2xVDD.

2.1 CONVENTIONAL I/OBUFFER

Fig. 2.1 shows the block diagram of a bidirectional input/output (I/O) buffer. As the output enable signal OE is high (VDD), the mixed-voltage I/O buffer is operating in transmit mode to transmit output signal from Dout to I/O PAD. On the other hand, the mixed-voltage I/O is operating in receive mode to receive input signals from I/O PAD to Din (internal circuit) if the OE is low (0V). In dual-oxide (thin-oxide and thick oxide) CMOS process, the core circuits usually use thin-oxide devices with low power supply voltage to reduce power consumption and silicon area while the interface circuits use thick-oxide to tolerant higher voltages and prevent reliability problems in traditional mixed-voltage I/O buffers.

2.2 ISSUES IN MIXED-VOLTAGE I/OINTERFACE

The conventional tri-state I/O buffer with 1.2-V gate-oxide devices in a 0.13-µm CMOS process is shown in Fig. 2.2, where the power supply voltage (VDD) is 1.2 V.

However, the input signal at the I/O pad in the mixed-voltage I/O interface may rise up to 2.5 V in the tri-state input (receive) mode. In the receive mode, the gate voltages of the pull-up PMOS device and the pull-down NMOS device in the I/O buffer are traditionally controlled at 1.2 V and 0 V to turn off the pull-up PMOS device and the pull-down NMOS device by the pre-driver circuit, respectively. When the input signal at the I/O pad raises up to 2.5 V in the tri-state input mode, the parasitic drain-to-well pn-junction diode in the pull-up PMOS device will be forward biased. Therefore, an undesired leakage current path flows from the I/O pad to the power supply voltage (VDD) through the parasitic pn-junction diode. Besides, because the gate voltage of the pull-up PMOS device is 1.2 V and the input signal at I/O pad is 2.5 V, the pull-up PMOS device will be turned on in such tri-state input mode to conduct another undesired leakage current path from the I/O pad to the power supply voltage (VDD).

Such undesired leakage currents cause not only more power consumption in the electronic system but also malfunction in the whole electronic system.

Moreover, because the gate-drain voltage (Vgd) of the pull-down NMOS device and the gate-source voltage (Vgs) of the input buffer in Fig. 2.2 with 2.5-V input signal are higher than their voltage levels in the normal operation, such high voltage across the thin gate oxide of the pull-down NMOS device and the input buffer results in the gate-oxide overstress reliability issue [5], [15]. In addition, the pull-down NMOS device and the input buffer with a 2.5-V input signal may suffer serious hot-carrier degradation if their drain-source voltages are too high [13].

2.3 PRIOR MIXED-VOLTAGE SOLUTIONS

The design concept is shown in Fig. 2.3. To solve the problem of gate-oxide reliability, a CMOS technology with a dual-oxide option [16], [17] is used. Because the thick gate-oxide can avoid the instances of gate-oxide breakdown, transistors that may suffer excessive gate-oxide stress should be replaced with thick oxide devices, and other transistors remain unchanged. To solve the problem of undesired leakage paths by the pull-up PMOS and the parasitic drain-to-well pn-junction diode, a gate-tracking circuit and a higher external voltage (VDDH) are used.

In Fig. 2.3, the mixed-voltage I/O buffer transmits GND-to-VDD (low voltage level) output signals and receives GND-to-VDDH (high voltage level) input signals.

The pre-driver circuit generates control signals to output transistors MN and MP. In the mixed-voltage I/O buffer, the output transistors, gate-tracking circuits, and input circuit, INV, are thick-oxide devices to overcome reliability problems. The pre-driver circuit uses thin-oxide devices since the input data come from internal core circuit with low voltage level. In order to avoid leakage current path from the I/O PAD to the power supply (VDD) through the parasitic drain-to-well pn-junction diode in the pull-up PMOS device, MP, a higher external voltage (VDDH) is used to bias the N-well of the MP. In addition, a gate-tracking circuit is required to avoid the leakage current path induced by the incorrect conduction of the MP. Such mixed-voltage interface applications with dual-oxide devices can successfully overcome the gate-oxide reliability and hot-carrier degradation problem.

Although the mixed-voltage I/O buffer with dual-oxide devices and an external N-well bias voltage can successfully solve these problems, there are some drawbacks in these mixed-voltage I/O buffers. Fist of all, an extra pad and another power supply (VDDH) are required for the external bias voltage, which results in the increase of

silicon area and cost. Second, the driving capacity is decreased due to higher threshold voltage of thick-oxide device when the gates of output transistors are controlled by pre-driver circuit with thin-oxide devices. Thirdly, the threshold voltage of the pull-up PMOS device (MP) is also increased since the N-well of the pull-up PMOS device (MP) is connected to a higher voltage (VDDH), which results in body effect. Because the driving capacity is decreased, the larger device dimension is required for the pull-up PMOS device to achieve the desired driving specifications.

As a result, the silicon area in such I/O buffers is increased. Moreover, the manufacturing time of thick-oxide device is even three times large than that of thin-oxide device. For these reasons, the mixed-voltage I/O buffer with dual-oxide devices and an external n-well bias is unsuitable for the low-cost commercial ICs.

Considering these limitations, several mixed-voltage I/O buffers with only thin-oxide devices have been reported in [18]-[21], [24]-[26].

Fig. 2.4 re-draws the mixed-voltage I/O buffer with stacked pull-up PMOS devices reported in [24]. Signal OE is the output-enable control signal. In the transmit mode, transistor MN1 is turned on and transistor MP2 is turned off, so that this I/O buffer drives the I/O pad according to the output signal Dout. In the tri-state input mode, transistor MN1 is turned off and transistor MP2 is turned on by the control signal OE at logic zero. If the input signal at the I/O pad is 5 V, the gate voltage of transistor MP1 and the floating n-well are pulled up to 5 V through transistor MP2 and the parasitic drain-to-well pn-junction diode in transistor MP0 to prevent the undesired leakage current paths from I/O pad to power supply voltage (VDD), respectively. Although this I/O buffer is simple, transistors MN0, MN1, and MP2 have the gate-oxide reliability problem in the tri-state input mode when the input signal has a 5-V voltage level. Besides, because the stacked PMOS devices with the floating n-well is applied to this I/O buffer, the PMOS devices in stacked

configuration occupy more silicon area.

Fig. 2.5 re-draws another mixed-voltage I/O buffer with stacked pull-up PMOS devices and stacked pull-down NMOS devices [25]. This I/O buffer uses transistors MP2, MN3, and MN4 as the gate-tracking circuit and transistors MP0, MP3, and MP4 as the dynamic n-well bias circuit. In the tri-state input mode with the control signal OE at GND, transistor MN4 is turned off and transistor MP2 is turned on. If the input signal at the I/O pad is 5 V, the gate voltage of transistor MP3 is biased at 5 V through transistors MP0 and MP2 to avoid the undesired leakage current path due to the incorrect conduction of transistor MP3. The floating n-well is biased at ~5 V through the parasitic drain-to-well pn-junction diode of transistor MP0. In the transmit mode with the OE control signal at VDD, transistor MN4 is turned on so that transistor MP3 is turned on, and transistor MP2 is kept off. Hence, this I/O buffer drives the I/O pad according to the output signal Dout. When the signal at the I/O pad is 0 V, the floating n-well is biased at 2.5 V through transistor MP4. When the input signal at the I/O pad is 2.5 V, the floating n-well is biased at ~2.5 V through the parasitic source-to-well pn-junction diodes of transistors MP3 and MP4. However, transistor MP2 has the gate-oxide reliability problem when the input signal at the I/O pad is 5 V in the tri-state mode. Besides, because the I/O buffer uses two PMOS devices, MP0 and MP3, in stacked configuration to drive the I/O pad, the stacked devices occupy more silicon area.

The mixed-voltage I/O buffer with a depletion PMOS device is re-drawn in Fig.

2.6 [18]. The depletion PMOS device MP2 in the I/O buffer is used as the gate-tracking circuit. In the tri-state mode, if the input signal at I/O pad is 5 V, the gate voltage of transistor MP0 is biased at 5 V through the depletion PMOS device MP2 to avoid the undesired leakage current path through the transistor MP0. This I/O buffer uses an extra pad that is connected to 5-V power supply (VDDH) to avoid the

undesired leakage current path through the parasitic drain-to-well pn-junction diode.

However, using the depletion device increases mask layer and process modification.

Thus, the fabrication cost of such I/O buffer design will be increased. In addition, using the extra n-well bias (VDDH) not only degrades the driving capacity of output device MP0 due to the body effect, but also increases the system cost.

Fig. 2.7 re-draws the mixed-voltage I/O buffer realized with only thin-oxide devices reported in [26]. In Fig. 2.7, the gate-tracking circuit and the dynamic n-well bias circuit are formed by transistors MP1, MP2, MP3, MP4, MN2, MN3, MN4, and MN5. In the transmit mode with signal OE at logic “1”, transistor MN4 is turned on to keep transistors MP3 and MP4 on. Thus, this I/O buffer drives the I/O pad according to signal Dout. Besides, because transistor MP3 is turned on, the floating n-well is biased at 2.5 V by transistor MP3 in the transmit mode. In the tri-state input mode with signal OE at logic “0”, transistor MN4 is kept off. If the input signal at the I/O pad is 5 V, the gate voltages of transistors MP0 and MP4 are biased at 5 V through transistor MP1 and MP2 to avoid the undesired leakage paths through the transistors MP0 and MP4. Besides, the floating n-well is also biased at ~5 V to avoid the undesired leakage path through the parasitic drain-to-well pn-junction diode of transistor MP0 when the voltage at the I/O pad is 5 V in tri-state input mode. When the input signal at the I/O pad is 0 V in the tri-state input mode, transistor MN3 is turned on to keep transistor MP3 on. So, the floating n-well is biased at 2.5 V.

Another mixed-voltage I/O buffer realized with only thin-oxide devices is re-drawn in Fig. 2.8 [19]. The gate-tracking circuit in Fig. 2.8 is composed of transistors MN3, MN4, MP2, MP3, and MP4. The dynamic n-well bias circuit in Fig.

2.8 is formed by transistors MN5, MP5, MP6, and MP7. Besides, the body terminals of all PMOS transistors in the gate-tracking circuit and the dynamic n-well bias circuit are connected to the floating n-well. Such I/O circuit shown in Fig. 2.8 can overcome

the gate-oxide reliability problem and avoid the undesired leakage paths. However, there are too many devices used to realize the desired functions of the gate-tracking circuit and the dynamic n-well bias circuit. More devices used in the mixed-voltage I/O cause more complex metal routing connection in the I/O cells.

2.4 AMIXED-VOLTAGE I/OBUFFER WITH BLOCKING NMOS AND

DYNAMIC GATE-CONTROLLED CIRCUIT

The block diagram of mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit proposed in [14] is depicted in Fig. 2.9. Here, VDDH has a high voltage of 2xVDD, which can be generated by the on-chip charge pump circuit [22] or other high-voltage generators. Transistor MN1 is used to protect the conventional I/O buffer from the high-voltage overstress. The operations of the dynamic gate-controlled circuit in the proposed I/O buffer with blocking NMOS are listed in Table 2.1. When the I/O buffer is in the receive mode, the gate terminal (node 2) of MN1 is biased at VDD by the dynamic gate-controlled circuit, whereas the pull-up device MP0 and pull-down device MN0 are both turned off by the pre-driver.

At this moment, if an input signal of logic ‘0’ (0V) is received from the I/O PAD, node 1 is discharged to 0 V through the transistor MN1, and this input signal can be successfully transferred to the node Din. When a logic ‘1’ (VDDH) signal is received at the I/O pad, the gate terminal of transistor MN1 is still biased at VDD, so the voltage on node 1 is pulled to “VDD−Vth”. A feedback device MP1 is added to restore the voltage level on node 1 to VDD, which avoids the undesired static dc current through the inverter INV1. In this design, MN1, MP1, and inverter INV1 can convert the VDDH input signal to VDD signal successfully. Therefore, MN1 can protect the I/O buffer without suffering high-voltage overstress in both steady states of transmit

mode and receive mode.

Fig. 2.10 depicts the dynamic gate-controlled circuit of the I/O buffer in Fig 2.9, where MP2 and MP3 are designed with the cross-coupled structure. If the gate voltage of MP2 (or MP3) is pulled down, this transistor is turned on and pulls up the gate voltage of the other transistor to VDDH (2xVDD) to turn it off. For example, if the voltage on node 5 is lower than “VDDH−|Vtp|” and the voltage on node 6 is VDDH, MN2 is turned on to keep the node 5 at VDD. Capacitors C1 and C2 are used to couple the signals from nodes 3 and 4 to nodes 5 and 6, respectively. The voltages across these capacitors are always VDD, because the voltage levels on the top plate and bottom plate of capacitors C1 and C2 are either VDD and 0V or 2xVDD and VDD. With these capacitors, when node 3 converts the voltage level from VDD to 0V, the voltage on node 5 is pulled down to VDD and then the voltage level on node 6 is pulled up to 2xVDD by transistor MP3. On the contrary, when the voltage level on node 4 is converted from VDD to 0V, the voltage on node 6 is pulled down to VDD, and that on node 5 is pulled up to 2xVDD by MP2. Initially, the voltages on nodes 3, 4, 5, and 6 could be unknown. If the voltages on nodes 5 and 6 are 2xVDD and VDD, and the voltages on nodes 3 and 4 are 0V and VDD, the voltages across capacitors C1 and C2 are 2xVDD and 0V, respectively, instead of both VDD. In order to overcome this problem, diode strings DS1 and DS2 are added. The turn-on voltages of the diode strings are designed to a little higher than VDD by using multiple diodes in stacked configuration. In order to prevent the leakage current path to the grounded p-type substrate, the diode-connected MOSFET or poly diode [23] is suggested. With these diode strings, if the voltage on node 3 is at 0V and that on node 4 is at VDD initially, the voltage on node 5 is clamped at the turn-on voltage (~VDD) of DS1. Therefore, MP3 is turned on to pull up the voltage on node 6 to 2xVDD. Thus, the voltages across capacitors C1 and C2 are both VDD.

In this mixed-voltage I/O buffer, the bulk of the blocking NMOS MN1 can be coupled to 0V (GND) without any gate-oxide reliability problem, even if the gate voltage of MN1 may be as high as VDDH (2xVDD). The reason is that this blocking NMOS MN1 is always turned on and the voltage across the gate oxide of MN1 is from the gate to the conducting channel, but not from the gate to its bulk. The gate oxides of all NMOS devices in the dynamic gate-controlled circuit are also safe because these NMOS devices are turned on when their gates are pulled up to VDDH.

Table 2.1

Operations of the dynamic gate-controlled circuit in the mixed-voltage I/O buffer with blocking NMOS [14].

Mode Transmitted Signals (Dout)

Gate Voltage of MP0 (PU)

Gate Voltage of MN1 (Node 2)

Receive Mode X VDD VDD

Transmit Mode Low (0 V) VDD VDD

Transmit Mode High (VDD) 0 V VDDH (2xVDD)

Fig. 2.1 Block diagram of bidirectional I/O buffer.

Fig. 2.2 Conventional tri-state I/O buffer will suffer the circuit leakage and gate-oxide reliability issues in the mixed-voltage I/O interface.

Fig. 2.3 Block diagram of a mixed-voltage I/O buffer with dual-oxide devices and an external n-well bias voltage.

Fig. 2.4. Mixed-voltage I/O buffer with stacked pull-up PMOS devices [24].

Fig. 2.5. Mixed-voltage I/O buffer with stacked pull-up PMOS devices and stacked pull-down NMOS devices [25].

Fig. 2.6. Mixed-voltage I/O buffer with a depletion PMOS device MP2 [18].

Fig. 2.7. Mixed-voltage I/O buffer realized with only thin-oxide devices [26].

Fig. 2.8. Mixed-voltage I/O buffer realized with only thin-oxide devices [19].

Fig. 2.9 The mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit.

Fig. 2.10 Circuit implementation of the dynamic gate-controlled circuit in the Fig. 2.9.

Chapter 3

1.2/2.5-V Mixed-Voltage I/O Buffer with

Gate-Tracking Circuit and Dynamic N-well Bias Circuit by Only Using Thin Gate-Oxide Devices

3.1 INTRODUCTION

There are a lot of drawbacks in the previous mixed-voltage I/O interface design with a dual-oxide option, like as extra voltage source and process cost. The prior designs of I/O interface are complicated and had been described in the chapter 2 already. In this chapter, a better mixed-voltage I/O interface is presented and proposed without extra process and voltage source in [21]. The presented design of mixed-voltage I/O interface buffer is simpler than the prior designs.

3.2 DESIGN CONCEPT

Fig. 3.1 shows the presented mixed-voltage I/O buffer realized with a dynamic n-well bias circuit, and a gate-tracking circuit by only using thin gate-oxide devices [18]-[19], [24]-[26]. The stacked NMOS devices, MN0 and MN1, are used to avoid the high-voltage overstress on their gate oxide. The gate-tracking circuit shown in Fig.

Fig. 3.1 shows the presented mixed-voltage I/O buffer realized with a dynamic n-well bias circuit, and a gate-tracking circuit by only using thin gate-oxide devices [18]-[19], [24]-[26]. The stacked NMOS devices, MN0 and MN1, are used to avoid the high-voltage overstress on their gate oxide. The gate-tracking circuit shown in Fig.