C ONCLUSION

A new mixed-voltage I/O buffer with the stacked NMOS technique, dynamic n-well technique, and gate-tracking circuit have been successfully designed and implemented in UMC 0.13-μm 1.2-V CMOS process, which can be operated in the 1.2/2.5-V signal environment without the gate-oxide reliability problem. The new mixed-voltage I/O buffer can be applied for high-speed applications without the

gate-oxide reliability problem and the circuit leakage issue. The new mixed-voltage I/O buffer realized with 1xVDD devices can be easily applied in 1xVDD/2xVDD mixed-voltage interface.

Table 3.1

Comparison on features among the mixed-voltage I/O buffer designs.

Mixed-voltage I/O designs

N-well

bias Extra pad Gate-oxide reliability issue

Pre-driver

Fig. 3.1 Basic design concept for mixed-voltage I/O buffer realized with only thin-oxide devices.

Fig. 3.2 The mixed-voltage I/O buffer with gate-tracking circuit and dynamic n-well bias circuit proposed in [21].

Fig. 3.3 The function block of completed mixed-voltage I/O cell with gate-tracking circuit and dynamic n-well bias circuit.

Fig. 3.4 The circuit schematic of completed mixed-voltage I/O cell with gate-tracking circuit and dynamic n-well bias circuit.

Dout

I/O PAD Floating

N-Well

(a)

Dout

I/O PAD Floating

N-Well

(b)

(Continued to the next page of Fig. 3.5)

I/O PAD

(c)

Fig. 3.5 The simulated waveforms of the new proposed mixed-voltage I/O cell with a 20-pF load and 50-MHz I/O signal in (a) the transmit mode, (b) the tristate input (receive) mode, and (c) the transient simulation of pull-up for floating pad in 200-KHz.

Mixed-Voltage I/O Cells

Fig. 3.6 The die photo of the 1.2/2.5-V mixed-voltage I/O cells with gate-tracking circuit and dynamic N-well bias shown by only using only thin oxide devices.

Fig. 3.7 The layout view of the new 1.2/2.5-V mixed-voltage I/O cell with gate-tracking circuit and dynamic n-well bias.

Fig. 3.8 The measurement setup for testing the new 1.2/2.5-V mixed-voltage I/O cell with only thin oxide devices and dynamic n-well bias in transmit mode and receiving mode with 0/1.2-V input signal.

(a)

(b)

Fig. 3.9 The measurement results of the new 1.2/2.5-V mixed-voltage I/O cell in transmit mode and receiving mode with (a)1-MHz and (b)5-MHz 0/1.2-V input signal.

Fig. 3.10 The measurement setup for testing the new 1.2/2.5-V mixed-voltage I/O cell with gate-tracking circuit and dynamic n-well bias in transmit mode and receiving mode with 0/2.5-V input signal.

(a)

(Continued to the next page of Fig. 3.11)

(b)

Fig. 3.11 The measurement results of the new 1.2/2.5-V mixed-voltage I/O cell in transmit mode and receiving mode with (a)1-MHz and (b)5-MHz 0/2.5-V input signal.

Fig. 3.12 The measurement result of the new 1.2/2.5-V mixed-voltage I/O cell for Pull-up function.

Chapter 4

New Proposed Mixed-Voltage Crystal Oscillator Circuit I

4.1 INTRODUCTION

In the advanced CMOS process technology, the complication and the requirement of precision have greatly increased in ICs, and also the clock rate is getting fast. In the same time, it becomes an important subject to sustain a high stability and precision of clock signal. And that is why a crystal oscillator is one of the most widely used circuits in modern digital ICs due to its stable and precise oscillation frequency.

A conventional crystal oscillator circuit is connected with a crystal between the output (XO) pad and the input (XI) pad for oscillation to generate the stable clock signal in the chip [27], [28]. In some applications, the clock signal will be directly provided from the external clock sources and sent into the chip through the input (XI) pad with the output (XO) pad floating. But, the conventional crystal oscillator circuit design with 1xVDD CMOS devices is unsuitable to receive the external clock signal with voltage level over 1xVDD, due to the gate-oxide reliability issue [5], [15] and the hot-carrier degradation issue [6].

The mixed-voltage I/O circuits had been discussed and presented in some prior papers [18]-[19], [24]-[26], but the mixed-voltage crystal oscillator circuit was never discussed before. In this chapter, a new mixed-voltage crystal oscillator circuit I realized with low-voltage CMOS devices is proposed without suffering the gate-oxide

reliability issue and undesired leakage current path. The new proposed mixed-voltage crystal oscillator circuit I has been designed and realized in UMC 130-nm 1.2-V CMOS process to server 1.2/2.5V mixed-voltage interface applications and TSMC 90-nm 1-V CMOS process to server 1/1.8V mixed-voltage interface applications.

4.1.1 Basic Resonance Theory

Fig. 4.1 shows a basic architecture of an oscillator circuit. This circuit includes two parts, an amplifier that provides a voltage gain A(s) and a feedback network β(s).

When a trigger signal Ss is applied to the circuit, a total transfer function Af(s) of the loop can be got by

It means the signal with frequency ω0 could be held and amplified in the loop without keeping the signal Ss. In order for an oscillator circuit to operate and by the condition of the equation (4-2), two conditions must be met: (A) The loop gain must be equal to unity; (B) The loop phase shift must be equal to 0, 2Pi, 4Pi, etc. radians. And these two conditions are called Barkhausen criterion.

4.1.2 Equivalent Circuit of Crystal

Quartz crystal units serve as the controlling element of oscillator circuits by conversion of mechanical vibrations to electrical current at a specific frequency. This is accomplished by means of the "Piezoelectric" effect. Piezoelectricity is electricity created by pressure. In a piezoelectric material, the application of mechanical pressure along an axis will result in the creation of an electrical charge along an axis at right angles to the first. In some materials, the obverse piezoelectric effect is found, which means that the imposition of an electric field on the ends of an axis will result in a mechanical deflection along an axis at right angles to the first. Quartz is uniquely suited, in terms of mechanical, electrical and chemical properties, for the manufacture of frequency control devices. Quartz crystal units which oscillate within certain frequency and temperature ranges have been developed over the years.

The equivalent circuit of a crystal is shown in Fig. 4.2. Rs is the effective series resistance in the crystal; as well as Ls and Cs are the motional inductance and capacitance of the crystal. Cp is the parasitic shunt capacitance due to the electrodes.

In parallel resonant mode, the crystal will look inductive to the circuit. At the resonant frequency, the crystal will look and perform like a low resistance. And some typical crystal parameters in different oscillation frequency are listed in Table 4.1.

Fig. 4.3 shows the reactance-frequency plot of the crystal. And the equivalent circuit impedance is given by the equation (4-4)

2

When the crystal is operating at series resonance, it looks purely resistive and the series resonance frequency (fs) is given by the equation (4-5)

1

When the crystal is operating in parallel resonant mode, it looks inductive. In this mode, the frequency (fa) of oscillation is given by the equation (4-6)

1

The conventional Pierce-type crystal oscillator circuit is shown in Fig. 4.4. This circuit consists of two parts. One is an inverting amplifier that supplies a voltage gain and 180 degree phase shift, which is integrated into the chip with the XI and XO pads.

The other is a frequency selective feedback network, which is out of the chip. The crystal combined with C1 and C2 to form a feedback network that tends to stabilize the frequency and supply 180 degree phase shift to the feedback path. The feedback resistance, Rf, is used to bias the inverting amplifier around half of power supply voltage, therefore the inverting amplifier is operating in the high gain linear region. In steady state, this circuit has an overall phase shift around 360 degree. This satisfies one of the conditions required to sustain oscillation. The other condition for proper start-up and sustaining oscillation is that the closed loop gain should be over or equal to unity.

4.1.4 Evaluation of Minimum Inverting Gain g_m

Fig. 4.5 (a) and Fig. 4.5 (b) show the used Pierce oscillator circuit with its

equivalent circuit diagram, in which the crystal is replaced by Ls, Cs, Rs and Cp. The inverter is replaced by its output impedance Ro and the output current from the transconductance gain: Iout= gm*V1. Rf is a feedback resistance to force the gate input to its threshold level to provide starting up. In most microcontroller-types the feedback transistor Rf is already integrated as a semiconductor resistor parallel to the inverting gate.

A very convenient way and also rather easy to prove the oscillation condition is to transfer all these elements in series with Rs by means of the power dissipation rule, saying that the elements Ro, Rf and gm*V1 are replaceable by a resistor in series with Rs, if this gives the same dissipation or damping to the circuit. Then the oscillation condition is true, if the total value of the resistive elements, including the own damping Rs of the crystal is less than zero.

After transferring all resistive elements into the series branch, the simplified resonance calculation model of fig. 4.6 can be used. In this figure, Co is the total parallel capacitance, including load capacitance Cload formed by the capacitances C1

and C2 in series and the parasitic capacitance Cpar at input and output parallel with the gate and Cp as following:

2

Combining these equations, we obtain for the total series resistance:

1 2 1

The circuit will oscillate, if the value of Rt is zero or negative. So the minimum value of gm should be:

The first two products of this equation are reduced to a minimum value with C1 = C2.

To achieve minimum requirement of oscillation, both load capacitances should be equal. In this case we find:

2

In the advanced CMOS process, the devices with thinner gate oxide can be operated at a higher operating speed under a lower VDD supply voltage. The power supply voltage level has been decreased from 2.5V to around 1V to maintain the gate-oxide reliability and to overcome the hot-carrier degradation. However, many other components on the board or in the system are still operated at another higher voltage level such as 3.3V or 5V. This is also a challenge to the interface circuit to avoid the gate-oxide reliability problem.

Fig. 4.7 shows the conventional crystal oscillator circuit realized with the 1×VDD devices. When this circuit was used in the mixed-voltage interface, it will suffer the gate-oxide reliability issues. When the EN signal is kept at VDD and the external input clock signal at the XI pad rises up to 2×VDD. The pull-up PMOS and pull-down NMOS will suffer the gate-oxide overstress issue. In order to avoid the gate-oxide reliability issue, the devices which suffer the gate-oxide overstress could be replaced by the thick-oxide devices. However, with both of the thick-oxide and thin-oxide devices in a chip, the fabrication cost of CMOS process is increased.

4.3 CIRCUIT DESCRIPTION

Fig. 4.8 shows the new proposed mixed-voltage crystal oscillator circuit I realized with only the thin gate-oxide (1×VDD) devices. XI pad and XO pad are the input and output pads of the proposed mixed-voltage crystal oscillator circuit I, respectively. EN and PA signals are controlled by the internal circuits of IC. XC is the clock signal which is produced by crystal oscillator circuit or to receive the external clock signal into the IC.

When the voltage level of PA signal is VDD, the proposed mixed-voltage crystal oscillator circuit I is operated with crystal and two load capacitances to generate the sinusoidal-wave signal at both XI pad and XO pad. Transmission gates TRAN1 and TRAN2 are turned off, so that the sinusoidal-wave signal can’t pass through the upper path of this circuit from XI pad to XO pad. Besides, transistor MN4 is turned on to keep transistor MN2 off and transistor MP3 on in order to keep the output terminal of the upper nand gate at VDD. The gate terminal of transistor MP4 is directly connected to the output terminal of the upper nand gate, so the transistor MP4 is turned off. The input terminal (N01) of the upper nand gate will follow the voltage level of XI pad, while the output terminal of upper nand gate keeps at VDD. Meanwhile, transmission gates TRAN3 and TRAN4 are turned on and the generated sinusoidal-wave signal will pass through the lower path of this circuit from XI pad to XO pad. The signal EN can be transmitted to one input terminal of the lower nand gate to enable or disable the lower nand gate. Besides, transistor MN7 and MP7 are turned off.

When the voltage level of PA signal is GND, the proposed mixed-voltage crystal oscillator circuit is operated to receive an external clock input signal whose voltage level could be 1×VDD or 2×VDD. Transmission gates TRAN1 and TRAN2 turn on and the external clock signal will pass through the upper path from XI pad to XC. The

signal EN can be transmitted to one input terminal of the upper nand gate to enable or disable the nand gate. Besides, transistor MN4 is turned off. Transistor MN1 and MP4 with upper nand gate are used to transfer the external clock signal from the XI pad to the XO pad. Transistor MN1 is used to limit the voltage level of external clock input signal reaching to the gate oxide of the upper nand gate. Because the gate terminal of transistor MN1 is connected to the power supply voltage (VDD), the input (N01) voltage of the upper nand gate is limited to VDD-Vt when the voltage level of external clock signal is even up to 2×VDD. Then, transistor MP4 will pull the input node (N01) of the upper nand gate up to VDD, when the output node of upper nand gate is pulled to GND. The external clock signal can be successfully transferred into the internal input node XC. Meanwhile, transmission gates TRAN3 and TRAN4 turn off. Transistor MN7 is turned on to keep transistor MN6 off and transistor MP6 on in order to keep the output terminal of the lower nand gate at VDD. Transistor MP7 is also turned on to keep the node between MN5 and MN6 at VDD. Thus, when the XI pad is with the input signal voltage level of 2×VDD, any voltage drop between the gate terminal and source/drain terminal of transistor MN5 and MP5 is still limited to VDD. So, the new proposed crystal oscillator circuit I can receive external clock signal of 2×VDD without suffering the gate-oxide overstress issue.

4.4 SIMULATION RESULTS

Fig. 4.9 shows the simulation waveforms of the proposed mixed-voltage crystal oscillator circuit I in a 130-nm 1.2-V CMOS process to serve 1.2/2.5-V mixed-voltage interface. As shown in Fig. 4.9(b), with the 30-MHz external clock signal of 2×VDD into XI pad and 20-pF load capacitance in XC, the input terminal (N01) voltage of the upper nand gate can be limited and biased at the desired voltage levels (1.2 V). The

final signal voltage level reaching to the XC node is successfully shifted down to 1×VDD. The proposed mixed-voltage crystal oscillator circuit I can be operated correctly without the gate-oxide reliability issue. In Fig. 4.9(a), the proposed mixed-voltage crystal oscillator circuit I with the crystal of 30-MHz fundamental frequency and a load capacitance 20-pF at the pad can successfully generate the clock signal of 30-MHz at the XC node under the power supply of 1×VDD. As these simulations, the desired functions of this mixed-voltage crystal oscillator circuit I have been verified.

Fig. 4.10 shows the simulation waveform of the proposed mixed-voltage crystal oscillator circuit I in a 90-nm 1-V CMOS process to serve 1/1.8-V mixed-voltage interface. As shown in Fig. 4.10(b), with the 30-MHz external clock signal of 2×VDD into XI pad and 20-pF load capacitance in XC, the input terminal (N01) voltage of the upper nand gate can be limited and biased at the desired voltage levels (1V). The final signal voltage level reaching to the XC node is successfully shifted down to 1×VDD.

The proposed mixed-voltage crystal oscillator circuit I can be operated correctly without the gate-oxide reliability issue. In Fig. 4.10 (a), the proposed mixed-voltage crystal oscillator circuit I with the crystal of 30-MHz fundamental frequency and a load capacitance 20-pF at the pad can successfully generate the clock signal of 30-MHz at the XC node under the power supply of 1×VDD. As these simulations, the desired functions of this mixed-voltage crystal oscillator circuit I have been verified.

4.5 EXPERIMENTAL RESULTS

Fig. 4.11 shows the layout view of the new proposed mixed-voltage crystal oscillator circuit I implemented in UMC 0.13-μm CMOS process. The cell size of XI, as well as XO, is only 183μm×60μm (including the bond pad), which is the same as

that of digital or analog I/O cell in a standard I/O cell library. The feedback resistance Rf, implemented by the poly resistance, is also included into the layout. ESD protection is also provided by following the ESD design rules given by the foundry to draw the layout for NMOS and PMOS devices which are directly connected to the pads.

Fig. 4.12 shows the layout view of the new proposed mixed-voltage crystal oscillator circuit I implemented in TSMC 90-nm 1-V CMOS process. The cell size of XI, as well as XO, is only 190.5μm×60μm (including the bond pad), which is the same as that of digital or analog I/O cell in a standard I/O cell library. The feedback resistance Rf, implemented by the poly resistance, is also included into the layout.

ESD protection is also provided by following the ESD design rules given by the foundry to draw the layout for NMOS and PMOS devices which are directly connected to the pads.

Fig. 4.13 is the die photo of the new proposed mixed-voltage crystal oscillator circuit I implemented in TSMC 90-nm CMOS process. To test the function of the new proposed mixed-voltage crystal oscillator circuit I in oscillation mode, the measurement setup is shown in Fig. 4.14 for an external crystal of fundamental frequency 4-MHz and 20-MHz. Here, an external crystal is connected between the input pad (XI) and the output pad (XO) of the new proposed mixed-voltage crystal oscillator circuit I with two external capacitors respectively connected in the input pad (XI) and the output pad (XO). The control signal EN and PA are both at VDD. As the measurement results shown in Fig. 4.15 The new proposed mixed-voltage crystal oscillator circuit I can successfully oscillate and correctly generate the clock signals of frequency 4-MHz and 20-MHz at XC node in Figs. 4.15(a) and 4.15(b), respectively.

To test the function of the new proposed mixed-voltage crystal oscillator circuit I in receiving mode, the measurement setup is shown in Fig. 4.16 for a 0/1-V external

clock signal of frequency 4-MHz at the input pad (XI). Here, the XI pad of the new proposed mixed-voltage crystal oscillator circuit I is used as the input pad to receive the external clock signal from the pulse generator and the external clock signal will be transmitted to the oscilloscope by the XC pad. The control signal EN is at VDD and PA is at GND. As the measurement results shown in Fig. 4.17, the new proposed mixed-voltage crystal oscillator circuit I can successfully transmit the 0/1-V clock signal of frequency 4-MHz to the XC node.

To test the function of the new proposed mixed-voltage crystal oscillator circuit I in receiving mode for a 0/1.8-V external clock signal of frequency 4-MHz at the input pad (XI), the measurement setup is shown in Fig. 4.18. Here, the XI pad of the new proposed mixed-voltage crystal oscillator circuit I is used as the input pad to receive

To test the function of the new proposed mixed-voltage crystal oscillator circuit I in receiving mode for a 0/1.8-V external clock signal of frequency 4-MHz at the input pad (XI), the measurement setup is shown in Fig. 4.18. Here, the XI pad of the new proposed mixed-voltage crystal oscillator circuit I is used as the input pad to receive