A M IXED -V OLTAGE I/O B UFFER WITH B LOCKING NMOS AND D YNAMIC

DYNAMIC GATE-CONTROLLED CIRCUIT

The block diagram of mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit proposed in [14] is depicted in Fig. 2.9. Here, VDDH has a high voltage of 2xVDD, which can be generated by the on-chip charge pump circuit [22] or other high-voltage generators. Transistor MN1 is used to protect the conventional I/O buffer from the high-voltage overstress. The operations of the dynamic gate-controlled circuit in the proposed I/O buffer with blocking NMOS are listed in Table 2.1. When the I/O buffer is in the receive mode, the gate terminal (node 2) of MN1 is biased at VDD by the dynamic gate-controlled circuit, whereas the pull-up device MP0 and pull-down device MN0 are both turned off by the pre-driver.

At this moment, if an input signal of logic ‘0’ (0V) is received from the I/O PAD, node 1 is discharged to 0 V through the transistor MN1, and this input signal can be successfully transferred to the node Din. When a logic ‘1’ (VDDH) signal is received at the I/O pad, the gate terminal of transistor MN1 is still biased at VDD, so the voltage on node 1 is pulled to “VDD−Vth”. A feedback device MP1 is added to restore the voltage level on node 1 to VDD, which avoids the undesired static dc current through the inverter INV1. In this design, MN1, MP1, and inverter INV1 can convert the VDDH input signal to VDD signal successfully. Therefore, MN1 can protect the I/O buffer without suffering high-voltage overstress in both steady states of transmit

mode and receive mode.

Fig. 2.10 depicts the dynamic gate-controlled circuit of the I/O buffer in Fig 2.9, where MP2 and MP3 are designed with the cross-coupled structure. If the gate voltage of MP2 (or MP3) is pulled down, this transistor is turned on and pulls up the gate voltage of the other transistor to VDDH (2xVDD) to turn it off. For example, if the voltage on node 5 is lower than “VDDH−|Vtp|” and the voltage on node 6 is VDDH, MN2 is turned on to keep the node 5 at VDD. Capacitors C1 and C2 are used to couple the signals from nodes 3 and 4 to nodes 5 and 6, respectively. The voltages across these capacitors are always VDD, because the voltage levels on the top plate and bottom plate of capacitors C1 and C2 are either VDD and 0V or 2xVDD and VDD. With these capacitors, when node 3 converts the voltage level from VDD to 0V, the voltage on node 5 is pulled down to VDD and then the voltage level on node 6 is pulled up to 2xVDD by transistor MP3. On the contrary, when the voltage level on node 4 is converted from VDD to 0V, the voltage on node 6 is pulled down to VDD, and that on node 5 is pulled up to 2xVDD by MP2. Initially, the voltages on nodes 3, 4, 5, and 6 could be unknown. If the voltages on nodes 5 and 6 are 2xVDD and VDD, and the voltages on nodes 3 and 4 are 0V and VDD, the voltages across capacitors C1 and C2 are 2xVDD and 0V, respectively, instead of both VDD. In order to overcome this problem, diode strings DS1 and DS2 are added. The turn-on voltages of the diode strings are designed to a little higher than VDD by using multiple diodes in stacked configuration. In order to prevent the leakage current path to the grounded p-type substrate, the diode-connected MOSFET or poly diode [23] is suggested. With these diode strings, if the voltage on node 3 is at 0V and that on node 4 is at VDD initially, the voltage on node 5 is clamped at the turn-on voltage (~VDD) of DS1. Therefore, MP3 is turned on to pull up the voltage on node 6 to 2xVDD. Thus, the voltages across capacitors C1 and C2 are both VDD.

In this mixed-voltage I/O buffer, the bulk of the blocking NMOS MN1 can be coupled to 0V (GND) without any gate-oxide reliability problem, even if the gate voltage of MN1 may be as high as VDDH (2xVDD). The reason is that this blocking NMOS MN1 is always turned on and the voltage across the gate oxide of MN1 is from the gate to the conducting channel, but not from the gate to its bulk. The gate oxides of all NMOS devices in the dynamic gate-controlled circuit are also safe because these NMOS devices are turned on when their gates are pulled up to VDDH.

Table 2.1

Operations of the dynamic gate-controlled circuit in the mixed-voltage I/O buffer with blocking NMOS [14].

Mode Transmitted Signals (Dout)

Gate Voltage of MP0 (PU)

Gate Voltage of MN1 (Node 2)

Receive Mode X VDD VDD

Transmit Mode Low (0 V) VDD VDD

Transmit Mode High (VDD) 0 V VDDH (2xVDD)

Fig. 2.1 Block diagram of bidirectional I/O buffer.

Fig. 2.2 Conventional tri-state I/O buffer will suffer the circuit leakage and gate-oxide reliability issues in the mixed-voltage I/O interface.

Fig. 2.3 Block diagram of a mixed-voltage I/O buffer with dual-oxide devices and an external n-well bias voltage.

Fig. 2.4. Mixed-voltage I/O buffer with stacked pull-up PMOS devices [24].

Fig. 2.5. Mixed-voltage I/O buffer with stacked pull-up PMOS devices and stacked pull-down NMOS devices [25].

Fig. 2.6. Mixed-voltage I/O buffer with a depletion PMOS device MP2 [18].

Fig. 2.7. Mixed-voltage I/O buffer realized with only thin-oxide devices [26].

Fig. 2.8. Mixed-voltage I/O buffer realized with only thin-oxide devices [19].

Fig. 2.9 The mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit.

Fig. 2.10 Circuit implementation of the dynamic gate-controlled circuit in the Fig. 2.9.

Chapter 3

1.2/2.5-V Mixed-Voltage I/O Buffer with

Gate-Tracking Circuit and Dynamic N-well Bias Circuit by Only Using Thin Gate-Oxide Devices

3.1 INTRODUCTION

There are a lot of drawbacks in the previous mixed-voltage I/O interface design with a dual-oxide option, like as extra voltage source and process cost. The prior designs of I/O interface are complicated and had been described in the chapter 2 already. In this chapter, a better mixed-voltage I/O interface is presented and proposed without extra process and voltage source in [21]. The presented design of mixed-voltage I/O interface buffer is simpler than the prior designs.

3.2 DESIGN CONCEPT

Fig. 3.1 shows the presented mixed-voltage I/O buffer realized with a dynamic n-well bias circuit, and a gate-tracking circuit by only using thin gate-oxide devices [18]-[19], [24]-[26]. The stacked NMOS devices, MN0 and MN1, are used to avoid the high-voltage overstress on their gate oxide. The gate-tracking circuit shown in Fig.

3.1 is used to prevent the leakage current path which is resulted from the incorrect conduction of the pull-up PMOS device when the input signal is higher than VDD. As the mixed-voltage I/O buffer is operating in the transmit mode, the gate-tracking circuit must transmit the signal from the pre-driver circuit to the gate terminal of the

pull-up PMOS device, MP0, exactly. In the receive mode (tri-state input mode) with an input signal of 2xVDD, the gate-tracking circuit will charge the gate terminal of the MP0 to 2xVDD to completely turn off the MP0, and to avoid the leakage current from the I/O pad to the power supply (VDD). On the contrary, the gate-tracking circuit will keep the gate terminal of the MP0 at VDD to completely turn off the MP0, and to prevent the overstress on the gate oxide of the MP0 when the 0-V input signal is received from I/O PAD. Moreover, the dynamic n-well bias circuit shown in Fig.

3.1 is designed to prevent the leakage current path due to the parasitic drain-to-well pn-junction diode in the pull-up PMOS device MP0. In the transmit mode, the dynamic n-well bias circuit must keep the floating n-well bias at VDD so that the threshold voltage of the pull-up PMOS device isn’t increased due to the body effect.

In the receive mode with an input signal of 2xVDD, the dynamic n-well bias circuit will charge the floating n-well to 2xVDD to prevent the leakage current from the I/O pad to the power supply (VDD) through the parasitic pn-junction diode. On the other hand, the dynamic n-well bias circuit will bias the floating n-well at VDD when the input signal at the I/O pad is 0V.

As shown in Fig. 3.1, the extra transistors, MN2 and MP1, which are compared to Fig. 2.3, are added in the input circuit. The transistor MN2 is used to limit the voltage level of input signal reaching to the gate oxide of inverter INV1. The transistor MP1 is used to prevent unnecessary leakage current in the inverter INV1.

Because the gate terminal of transistor MN2 is connected to the power supply voltage (VDD), the input terminal of inverter INV1 will rise up to “VDD-Vth” when the input signal at the I/O pad is 2xVDD in the receive mode. The transistor MP1 will pull the input node of inverter INV1 up to VDD when the output node of inverter INV1 is pulled down to 0V. Therefore, the gate-oxide reliability problem of the input buffer can be solved.

3.3 CIRCUIT DESCRIPTION

Fig. 3.2 shows the mixed-voltage I/O buffer with the dynamic n-well bias circuit and gate-tracking circuit proposed in [21]. When the output control signal OE is at VDD (logic “1”), the mixed-voltage I/O buffer is operated in the transmit mode. The signal at the I/O pad follows the signal Dout, which is controlled by the internal circuits of IC. The pull-down signal, PD, produced by pre-driver is directly connected to the gate terminal of the pull-down NMOS device, MN1. The pull-up signal, PU, is connected to the gate terminal of the pull-up PMOS device, MP0, through the gate-tracking circuit which is composed of NMOS transistors MN2-MN4 and PMOS transistors MP2, MP3 and MP5. The transistors MN2 and MP2 comprise a transmission gate. The transistor MN3 in Fig. 3.2 is used to protect the transistor MN4 from gate-oxide reliability problem. The dynamic n-well bias circuit is composed of transistors MP4 and MP6. If the mixed-voltage I/O buffer is operating in transmit mode (OE = VDD), the gate terminal of MP4 will be biased at 0V to keep the floating n-well at VDD by turning on the transistor MP4. At this time, the PU signal is fully transmitted to the gate terminal of the pull-up PMOS device MP0 through the transmission gate, MN2 and MP2. As 0-V output signal is transmitted, the PD signal is set to VDD to turn on the transistor MN4. In the meanwhile, the PU signal is set to VDD to turn off the pull-up device MP0. Consequently, the voltage at the I/O pad and the gate voltage of transistor MP5 are discharged to 0 V through transistors MN0 and MN1. Transistor MP5 is turned on until the gate terminal of transistor MP2 is discharged to |Vtp| through transistors MN3 and MN4, where Vtp is the threshold voltage of PMOS device.

When the proposed I/O buffer is operated in the receive mode, the PU and PD signals are kept at VDD and 0V, respectively, to turn off transistors MP0 and MN1.

Signal Din follows the signal at the I/O pad in the receive mode. In order to prevent the undesired leakage current from the I/O pad to the power supply (VDD) through the pull-up PMOS device MP0, transistor MP3 is used to track the signal at the I/O pad and to control the gate voltage of transistor MP0. When the voltage level at the I/O pad exceeds “VDD+|Vtp|,” such as 2xVDD, transistor MP3 is turned on to charge the gate terminal of transistor MP0 up to 2xVDD. Thus, transistor MP0 is completely turned off to prevent the leakage current through its channel. If a 0-V input signal is received at I/O PAD, the floating n-well is biased at VDD through transistor MP4. As the mixed-voltage I/O is operating in the receive mode with an input signal of 2xVDD, another PMOS device MP6 is turned on to bias the floating n-well at 2xVDD. Also, transistor MP4 is turned off to prevent the leakage path by pulling up the gate terminal of MP4 to 2xVDD through transistor MP5. As a result, there is no leakage current path from the I/O pad to the power supply (VDD). Whenever the proposed mixed-voltage I/O buffer is in the transmit mode or the receive mode, the floating n-well is biased at VDD or 2xVDD directly. Thus, the subthreshold leakage problems do not occur in this proposed I/O buffer. Besides, transistor MP5 is also turned on to keep transistor MP2 off in order to prevent another leakage path from the gate terminal of transistor MP0 to the UP signal when the signal at the I/O pad is 2xVDD.

Transistors MN0 and MP1 with inverters INV1 and INV2 are used to transmit the input signal from the I/O pad to the internal node Din in the receive mode.

Transistor MN0 is used to limit the voltage level of input signal reaching to the gate oxide of inverter INV1. The signal at the I/O pad can be successfully transmitted to the internal input node Din. This I/O buffer can be correctly operated with neither gate-oxide reliability problem nor any circuit leakage issue in the receive mode.

3.4 SIMULATION RESULTS

In this work, a completed I/O cell is constructed. The function block diagram is shown in Fig. 3.3 and the circuit schematic is shown in Fig. 3.4. This mixed-voltage I/O cell circuit includes input stage and output stage, pull-up resistor for floating I/O PAD, pre-driver circuit, gate-tracking circuit, floating n-well circuit and ESD protect device. The SPICE simulation waveforms of the mixed-voltage I/O cell with a 20-pF load at I/O pad are shown in Fig. 3.5 in UMC 0.13-μm 1.2-V CMOS process. Fig.

3.5(a) shows the behavior in transmit mode. The signal Dout with 0.5-ns rising and falling time is correctly transmitted to the I/O pad and the voltage level of floating N-well normally keeps at VDD. Fig. 3.5(b) shows that in receive mode (tristate mode).

The signal Din correctly follows the signal with 0.5-ns rising and falling time at I/O pad and the voltage level of floating N-well is successfully pulled up to 2xVDD when the signal is 2xVDD at I/O pad. Fig. 3.5(c) shows the simulation waveform of the operation of the pull-up resistor, where the voltage level can be successfully pull up to weakly high when the pull-up resistor is turned on.

3.5 EXPERIMENTAL RESULTS

Fig. 3.6 is the die photo of the 1.2/2.5-V mixed-voltage I/O buffer with gate-tracking circuit and dynamic N-well bias circuit by only using thin gate-oxide devices. Fig. 3.7 shows the layout view of the 1.2/2.5-V mixed-voltage I/O buffer implemented in the UMC 130-nm 1.2-V CMOS process. The cell size of I/O cell is only 187μm×60μm (including the bond pad), which is the same as that of analog or power/ground cell in a standard I/O cell library.

To test the function of proposed I/O cell in transmit mode and receiving mode,

two proposed I/O cells are used and connected as the measurement setup in Fig. 3.8 for receiving 0/1.2-V signal of 1-MHz and 5-MHz. Here, the I/O cell_1 is used as the input cell to receive the external input signal from the pulse generator (81110A). The I/O cell_2 is used as the output cell to transmit the signal to the oscilloscope. As the measurement results shown in Fig. 3.9, the proposed I/O cell can successfully receive the 0/1.2-V input signal at the pad of the I/O Cell_1 and transmit to the pad of the I/O Cell_2.

To test the function of proposed I/O cell for receiving 0/2.5-V signal of 1-MHz and 5-MHz, two proposed I/O cells are used and connected as the measurement setup in Fig. 3.10. Here, the I/O cell_1 is used as the input cell to receive the external input signal from the pulse generator (81110A). The I/O cell_2 is used as the output cell to transmit the signal to the oscilloscope. As the measurement results shown in Fig. 3.11, the proposed I/O cell can successfully receive the 0/2.5-V input signal at the pad of the I/O Cell_1 and transmit to the pad of the I/O Cell_2 with the signal shifted in 0/1.2-V.

In Fig 3.12, the pull-up function is successfully verified with the voltage level at the pad pulled up to 0.92-V. From the measurement results, the 1.2/2.5-V mixed-voltage I/O buffer with gate-tracking circuit and dynamic N-well bias circuit by only using thin gate-oxide devices can be successfully operated in such a 1.2V/2.5V mixed-voltage I/O environment. The maximum operation frequency of the proposed I/O buffer depends on the output load and the device size of output circuit.

3.6 COMPARISONS

Table 3.1 lists the features among these mixed-voltage I/O buffers. Since the new mixed-voltage I/O buffers and the prior I/O buffers reported in [19] and [24]-[26]

use the dynamic n-well biased technique, no extra pad and power supply is required.

The new mixed-voltage I/O buffers in this work occupy smaller silicon area than the I/O buffers reported in [18]-[19], [24]-[25]. Although the circuit structures of the mixed-voltage I/O buffers reported in [24], [25] are simpler, these two I/O buffers have the gate-oxide reliability problem. In Fig. 2.4, transistors MN0, MN1, and MP2 have the gate-oxide reliability problem in the tri-state input mode when the input signal has a 5-V voltage level. In Fig. 2.5, transistor MP2 has the gate-oxide reliability problem when the input signal at the I/O pad is 5 V in the tri-state mode. In fig. 2.6, since the depletion PMOS is used to improve the gate-tracking circuit of the mixed-voltage I/O buffer reported in [18], extra mask and process modification are required to realize the depletion device. In fig. 2.4, fig. 2.5 and fig. 2.7 The prior mixed-voltage I/O buffers reported in [24]-[26] may have the subthreshold leakage problem, but the prior mixed-voltage I/O buffer reported in [19] and the new mixed-voltage I/O buffer don’t have. However, the new mixed-voltage I/O buffers occupy smaller silicon area than the prior I/O buffers [19], [24]-[26]. Thus, if the subthreshold leakage issue in the given CMOS process is serious, such as the 90-nm, 65-nm or more advanced CMOS process, the new mixed-voltage I/O buffer is recommended.

3.7 CONCLUSION

A new mixed-voltage I/O buffer with the stacked NMOS technique, dynamic n-well technique, and gate-tracking circuit have been successfully designed and implemented in UMC 0.13-μm 1.2-V CMOS process, which can be operated in the 1.2/2.5-V signal environment without the gate-oxide reliability problem. The new mixed-voltage I/O buffer can be applied for high-speed applications without the

gate-oxide reliability problem and the circuit leakage issue. The new mixed-voltage I/O buffer realized with 1xVDD devices can be easily applied in 1xVDD/2xVDD mixed-voltage interface.

Table 3.1

Comparison on features among the mixed-voltage I/O buffer designs.

Mixed-voltage I/O designs

N-well

bias Extra pad Gate-oxide reliability issue

Pre-driver

Fig. 3.1 Basic design concept for mixed-voltage I/O buffer realized with only thin-oxide devices.

Fig. 3.2 The mixed-voltage I/O buffer with gate-tracking circuit and dynamic n-well bias circuit proposed in [21].

Fig. 3.3 The function block of completed mixed-voltage I/O cell with gate-tracking circuit and dynamic n-well bias circuit.

Fig. 3.4 The circuit schematic of completed mixed-voltage I/O cell with gate-tracking circuit and dynamic n-well bias circuit.

Dout

I/O PAD

I/O PAD