This thesis was devoted to the design of Millimeter-wave frequency doubler and new broadband switches using InGaAs pHEMT. It consists of six chapters Chapter 1 gives the introduction of the MMIC design for various applications and the organization of this thesis.
In Chapter 2, we will deal with the design methodology of frequency multiplier.
The nonlinear devices characteristics are described; in the meantime, different biasing points and architectures with appropriate matching and biasing circuits are discussed to obtain an excellent performance of the frequency doubler.
Chapter 3 exhibits a 35-to-70 GHz frequency doubler using InGaAs pHEMT based on the theory which is introduced in Chapter 2. The special measurement techniques used in the millimeter-wave frequency range are also detailed for the circuit characterization. Last of all, both the simulated and measured results will be brought to comparison.
In Chapter 4, the design methodology of broadband switches will be introduced, along with various switching devices and switch configurations that will be presented. The Fisher’s equivalence is also described for the wideband switches design.
Chapter 5 demonstrates a 24-to-65 GHz SPST switch and a 30.5-to-64.5 GHz SPDT switch using InGaAs pHEMT. These designs utilize the Fisher’s equivalence as described in Chapter 4 to achieve the wideband performance.
Chapter 6 will combine the summary and indicates some suggestions for the MMIC design in the future.
Chapter 2
D ESIGN M ETHODOLOGY OF F REQUENCY M ULTIPLIER
2.1 Overview
It is an extremely difficult and inefficient progress to generate signal sources directly in the millimeter-wave frequency range. On the contrary, it is feasible to realize a low phase noise VCO with some standard components at low frequency.
Therefore, we usually utilize the VCO to generate the signal source at low frequency then convert it to the millimeter-wave frequency via a frequency multiplier. The design methodology of frequency multiplier will be introduced in this chapter.
2.2 Nonlinear Devices
In contrast to the operation of power amplifiers and oscillators, which may be visualized as an essentially linear circuit problem perturbed by nonlinear effects, frequency multiplication relies specifically on the nonlinear device behavior as the basic operation mechanism. Therefore, one of the most essential portions in frequency multiplier design is the nonlinear device. In general, there are tow choices.
One is passive diodes and the other is active FETs.
Passive Diodes The Schottky barrier diode (SBD) has been the primary nonlinear device for millimeter-wave frequency multiplier [2]. Fig. 2.1(a) shows the general structure of a SBD and Fig. 2.1(b) indicates its equivalent circuit. Also indicated are the key equations defining the nonlinearities, Cj and Rj, which are responsible for the multiplying operation. The parasitic series resistance, Rs, has to be minimized, in order to achieve high diode cut-off frequency and low multiplier conversion loss. This requires a low resistance current path within the diode
structure, which is implemented by a highly doped active layer below the cathode.
Active FETs FETs are widely used in MMIC frequency multipliers, as many monolithic foundry processes are based on the MESFET/HEMT structure.
Consequently, FET frequency multipliers can be fabricated on the same chip with other FET-based circuits, such as amplifiers, oscillators, mixers and switches, to form integrated subsystems. In the large-signal modeling [3] shown in Fig. 2.2, the following six elements were assumed to be nonlinear: Rfs, Rfd, Cgs, Cgd, Gm and Gds. However, the values of Rfs and Rfd remain very large and do not contribute to the generation of higher harmonics when the input power level is not large enough to cause the gate of the Schottky junction to conduct in the forward direction.
Furthermore, active FET frequency multipliers offer the potential to achieve conversion gain. Generally, they also require less input power, have higher isolation and give comparable noise performance to diode frequency multipliers.
2.3 Biasing Points Considerations
In a frequency multiplier design with passive diodes, the biasing point chosen from 0V to several hundred millivolts is generally acknowledged. It can generate higher harmonics caused by the current clipping of the diodes.
By contrast, the biasing point selection, in a frequency multiplier design with active FETs, is more complicated. Among the four major nonlinearities considered in Section 2.2, the transconductance (Gm) and the output conductance (Gds) are the major elements which cause the drain current clipping and generate higher harmonics. The capacitances (Cgs and Cgd) can be considered as parasitic elements which degrade the device gain and isolation at high frequencies. Following the quasi-static approximation of [4], the current at the drain port can be expressed as
∫
where vT is a gate bias value determined for best convergence from large to small signal S-parameter under small signal excitation. From (2.1), it can be inferred that there are two possible ways to generate higher harmonics: one usage is the nonlinearity of Gm and the other is that of Gds, Fig. 2.3(a) shows the behavior of Ids versus Vgs and Vds, and Fig. 2.3(b) indicates Ids, Gm versus Vgs characteristics of the FETs. Each biasing point is further discussed in the following.
2.3.1 Class A
For a class A amplifier operation [5], the quiescent gate voltage must be selected so that the drain current is set to Id0 = IDSS/2 and the drain voltage is set to Vd0 = (BVds-Vk)/2, which corresponds to a biasing point of point A in Fig. 2.3(a).
The resultant maximum Gm is shown in Fig. 2.3(b). Small-signal class A operation is linear as illustrated in Fig. 2.4(a), while large-signal class A operation introduces some nonlinearities in the output signal as illustrated in Fig. 2.4(b). As depicted in Fig. 2.4(b), the nonlinear trapezoidal wave function x(t) can be expressed as
According to the Fourier series expansion [6], the Fourier coefficients Xn of the trapezoidal wave function x(t) can be expressed as
the trapezoidal wave is composed of odd harmonic frequencies exclusively. Hence it appears that, in large-signal class A operation the output signal contains only odd harmonics of the fundamental signal. Consequently, the class A biasing condition is the favored choice when designing a tripler and other odd order multipliers.
2.3.2 Class B
For a class B amplifier operation [5], the bias is arranged to shut off the output device half of every cycle. In other words, the quiescent gate voltage must be set to Vg0 = Vp, and the drain voltage is set to Vd0 = (BVds-Vk)/2, which the biasing point is the same as point B, as shown in Fig. 2.3(a), near the pinch-off voltage as shown in Fig. 2.3(b). As illustrated in Fig. 2.5, when a sinusoidal signal is injected into a class B amplifier, the output signal will be half rectified, which is caused by the drain current clipping. As depicted in Fig. 2.5, the half-rectified sinusoidal wave function x(t) can be expressed as
According to the Fourier series expansion, the Fourier coefficients Xn of the half-rectified sinusoidal wave function x(t) can be expressed as
except for the fundamental, the half-rectified sinusoidal wave is composed of even harmonic frequencies exclusively. Hence it appears that, in class B operation the output signal contains only even harmonics of the fundamental signal. Therefore, the class B biasing condition is the favorite choice when designing a doubler, quadrupler or other even order multipliers.
The operation of a class B amplifier has a smaller time-averaged transconductance value than a class A amplifier. The pinch-off point B, however, has a lower Cgs value, smaller power consumption and is free of forward conduction current at the gate. Point B is preferable to A for high frequency operation due to the lower leakage current through Cgs; the conductance associated with Cgs becomes more significant at high frequencies and the leakage currents through the capacitance degrade the device gain and conversion gain.
2.3.3 Resistive Concept
Another possible biasing point corresponds to point C as indicated in Fig.
2.3(a). Here, the variation of Gds is the major factor to generate higher harmonics of the drain current. The channel of a FET, at low drain voltage, is a very linear resistor.
It becomes significantly nonlinear only when the drain voltage becomes great enough to accelerate the electrons to their saturated drift velocity. In most FETs, this occurs at a few tenths of a volt to one volt, depending on the gate voltage. Therefore, at normal small-signal voltage of a few millivolts, the FET’s resistive channel Gds is
very linear. The resistance of this linear channel can be varied by applying a large signal to the gate. The large signal changes the depth of the depletion region under the gate and consequently the resistance of the entire channel. When the gate voltage drops below Vp, the FET’s cutoff voltage, the resistance is virtually infinite; when the gate voltage reaches its maximum value, the channel resistance is very low, usually a few ohms. The range of resistances is entirely adequate to achieve good performance of producing higher harmonics, in which the concept is similar to the resistive mixer design theory [7]. However, the efficiency of generating higher harmonics is better with Gm than Gds.
2.4 Frequency Multiplier Design
2.4.1 Architectures of Frequency Multipliers
In general, there are two different methods to design a frequency multiplier [8].
One is single-ended and the other is balanced.
Single-ended “Single-ended” means the usage of a single nonlinear device.
Fig. 2.6 indicates the circuit of a single-ended FET frequency multiplier. This FET can generate higher harmonics to achieve a better multiplication with an appropriate bias.
Balanced Fig. 2.7 illustrates the circuit of a balanced FET frequency
multiplier. Like the single-ended configuration, it also needs an applicable bias.
Moreover, the balanced configuration can be used to reduce the unwanted fundamental frequency, in which the cancellation is caused by the 180o out-of-phase.
The balanced configuration has several advantages over the single-ended circuit. One is the nature of the phase cancellation for the fundamental frequency.
The second advantage is that, like other balanced circuits, the FET balanced
frequency multiplier has greater bandwidth and 3 dB output power than the single-ended circuit. The third is that it is often easier to realize the load impedance of a balanced frequency multiplier than that of a single-ended circuit. Nevertheless, there are many drawbacks of the balanced configuration. The unit uses two FETs, consumes more DC power, and occupies larger chip area than that of the single-ended circuit. The usage of the coupler and combiner circuits, in a balanced configuration, is the other major die area consumption.
2.4.2 Input and Output Matching Network Configurations
The device-circuit interaction not only at the fundamental frequency, but also at the harmonic frequencies, is very crucial to the multiplication process. Although in the case of a frequency doubler it is mainly the fundamental frequency and its second harmonic to be concerned with, this still leaves transistor input and output impedance matching conditions at both these frequencies to be accounted for as potentially influential design considerations, in addition to the general dependence on the drive levels [9], [10].
The basic FET frequency doubler configuration is shown in Fig. 2.8, exhibiting a FET in common source configuration flanked by matching networks which match the gate-source port of the device to the generator at the fundamental frequency and the device drain-source port to the external load at the second harmonic frequency. A more rigorous design must be capable of undesired harmonics suppression such as a quarter-wavelength short-circuited stub, with respect to fundamental frequency, at the gate-source port of the device to suppress second harmonic frequency leakage and a quarter-wavelength open-circuited stub, with respect to fundamental frequency, at the drain-source port of the device to suppress fundamental frequency leakage. In addition, biasing circuits for the gate-source and drain-source port are also involved.
(a) (b)
Fig. 2.2 The large-signal model of a FET
Fig. 2.1 The Schottky barrier diode (SBD) with (a) general structure, (b) its equivalent circuit.
(b) (a)
Fig. 2.3 DC characteristics of the FET. (a) Ids versus Vgs and Vds, (b) Ids and Gm versus Vgs at Vds = 1.5 V.
(b) (a)
Fig. 2.4 Class A operation with (a) small-signal, (b) large-signal.
Fig. 2.5 Class B operation.
Fig. 2.6 The single-ended configuration of a frequency multiplier.
Fig. 2.8 The basic configuration of a frequency doubler.
Fig. 2.7 The balanced configuration of a frequency multiplier.
Chapter 3
F REQUENCY M ULTIPLIER USING I N G A A S P HEMT
3.1 Overview
Based on the analysis and design methodology described in Chapter 2, this chapter demonstrates a 35-to-70 GHz millimeter-wave frequency doubler using InGaAs pHEMT. The fabrication, design and simulations of the circuit will be presented in the following. The measurement considerations are also specified in detail and the measured results are depicted in the last section.
3.2 MMIC Foundry Description
The pHEMT device used in this design is fabricated by WIN Semiconductor Corp. with a standard 0.15-um high-power InGaAs pHEMT MMIC process. The process employs a hybrid lithographic approach using direct-write electron beam (E-beam) lithography for sub-micron T-gate definition and optical lithography for the other process steps. The pHEMT devices are grown using molecular beam epitaxy (MBE) on 6-inch semi-insulating (SI) GaAs substrates. The pHEMT device has a typical unit current gain cutoff frequency (ft) of 85 GHz and maximum oscillation frequency (fmax) of 200 GHz. The peak DC transconductance (Gm) at -0.45 V gate-source voltage is 495 mS/mm. The gate-drain breakdown voltage is 10 V, and the maximum drain current at 0.5 V gate-source voltage is 650 mA/mm.
Other passive components include thin-film resistor (TFR), mesa-resistor (epitaxial layer), metal-insulator-metal (MIM) capacitors, spiral inductors, and air-bridges. The wafer is thinned to 100 um for the backside metal plating and reactive ion etching (RIE) via-holes are used for DC grounding.
3.3 35-to-70 GHz Frequency Doubler using InGaAs pHEMT
3.3.1 Circuit Design
Fig. 3.1 indicates the schematic diagram of the 35-to-70 GHz frequency doubler. In order to minimize the chip area and the DC power consumption, the single-ended frequency doubler configuration was adopted. This circuit was designed using microstrip transmission lines. The nonlinear device is an InGaAs pHEMT with 4 x 75 um gate width. An effective way to employ an InGaAs pHEMT as a frequency doubler is to use it as a half-wave rectifier which is described in Section 2.3.2. Consequently, the operating condition near the pinch-off region (Vgs = -0.95V, Vds = 1.45V) with 14.5 mW power consumption was chosen to generate higher even harmonic power level. One quarter-wavelength open-circuited radial stub functions as a 35 GHz bandstop filter to reject the fundamental frequency at drain. The radial stub has wider bandwidth and higher rejection of more than 20 dB.
The gate bias is injected through a thin-film resistor connected to a decoupling MIM capacitor and a high impedance transmission line. This resistor stabilizes the InGaAs pHEMT at low frequencies. The combination of the resistor, capacitor and high impedance transmission line impedance is equivalent to a quarter-wavelength to yield the open condition at the input line. The decoupling circuit for the drain bias is realized via the similar method. The input port, with a DC blocking MIM capacitor, was matched to receive maximum power at the fundamental frequency of 35 GHz.
The output port, with a DC blocking coupled-line, was matched to deliver maximum power at second harmonic frequency of 70 GHz. The matching networks at the input and output of the circuit are achieved using 50O open-circuited stubs. A layout of the 35-to-70 GHz frequency doubler with chip size of 2 x 1 mm2 is accomplished by
the Cadence tools and is depicted in Fig. 3.2.
3.3.2 Simulated Results
The nonlinear InGaAs pHEMT model used in the simulation is a HP EEsof scalable nonlinear HEMT model (EE_HEMT model) provided by the foundry. The 35-to-70 GHz frequency doubler performance is simulated via the harmonic balance technique implemented in the commercial computer-aided design (CAD) software Agilent Advanced Design System (ADS). All the matching, biasing and other passive circuits are simulated through an electromagnetic (EM) full-wave simulator SONNET.
Conversion and rejection performances are the important specifications for a frequency doubler design. The definition of conversion gain is that the second harmonic output power minus the fundamental input power. The fundamental rejection is defined as the fundamental output power minus the fundamental input power, and the third harmonic rejection is defined as the third harmonic output power minus the fundamental input power. They are usually expressed in decibels.
The simulated conversion gain, fundamental rejection, third harmonic rejection and output power versus input power from -10 to 15 dBm at input frequency of 35 GHz are plotted in Fig. 3.3 and Fig. 3.4. It is observed that, for an input power level at 3 dBm, the conversion performance achieves a maximum conversion gain of -6.5 dB.
The saturated output power at 70 GHz is almost 0 dBm for 15 dBm input power. Fig.
3.5(a) and Fig. 3.5(b) also indicate the simulated conversion gain, fundamental rejection and third harmonic rejection as a function of input frequency from 32 to 38 GHz with an input power level of 1 and 6 dBm. It has around 1 GHz bandwidth centered at 35 GHz for a flat conversion gain. The simulated small-signal S-parameters from 20 to 50 GHz and 60 to 80 GHz, illustrated in Fig. 3.6(a) and Fig
3.6(b), give some assurances that the input and output ports are matched to nearly 50O standard. Fig. 3.7 shows the simulated large-signal S-parameters from 30 to 40 GHz with input frequency of 35 GHz and output frequency of 70 GHz for 1 dBm input power.
3.3.3 Measurement Considerations
In the millimeter-wave frequency range, two significant concerns of the 35-to-70 GHz frequency doubler should be taken into account. One is the power measurement and the other is the stability assurance.
Power Measurement To acquire the absolutely accurate power level at 70 GHz, a V-band waveguide power sensor is required. The power sensor calculates each power value of the in-band frequencies resulting in a total power level.
Accordingly, only the 70 GHz signal can exist to guarantee an accurate measurement. Indeed, a power meter, with calibrated calibration factors (CF) at each frequency, must be connected to the power sensor to depict the value of the measured power level.
Stability Assurance The stability assurance is the key point to certify the
accuracy for the power measurement. A spectrum analyzer (SA) can be used to verify whether the undesired oscillation occurs or not. Nevertheless, the commercially available SAs are not capable of directly measurement up to the V-band, W-band or higher frequencies. An external harmonic mixer should be applied with the SA to perform the down-conversion of the V-band, W-band or higher frequencies down to the lower frequency band. Therefore, we can still validate the frequency spectrum of the V-band, W-band or higher frequencies via the commercially available SAs and external harmonic mixers with the calibrated conversion loss (CL) and reference level offset. The harmonic mixing causes many
mixer products (mfRF + nfLO) at the intermediate frequency (IF) output. As a result, within a single harmonic band, a single input signal can produce multiple responses on the analyzer display as illustrated in Fig. 3.8 (in this case, the 76 GHz signal is valid), only one of which is valid. These responses come in pairs, where members of the valid response pair are separated almost to 2fIF and either the right-most (for negative harmonics) or left-most (for positive harmonics) member of the pair is the correct response. To identify the actual signals from the undesired images and spurs, a frequency-shift method can be applied. The altered quantity of the actual signals must consist with the shift of the radio frequency (RF) or local oscillator (LO) when either the RF or LO frequency is shifted. Otherwise, the remains are the undesired images and spurs. For some newer types of the SAs, identification of valid responses is achieved by simply turning on the signal-identification (SIG ID) feature.
3.3.4 Measured Results
The 35-to-70 GHz frequency doubler was measured via on-wafer probing. Fig.
3.9(a) and Fig. 3.9(b) illustrate the test setups used for the circuit characterization.
The former is established for power measurement and the latter verifies the stability
The former is established for power measurement and the latter verifies the stability