Chapter 2 Design Methodology of Frequency Multiplier
2.4 Frequency Multiplier Design
2.4.2 Input and Output Matching Network Configurations
The device-circuit interaction not only at the fundamental frequency, but also at the harmonic frequencies, is very crucial to the multiplication process. Although in the case of a frequency doubler it is mainly the fundamental frequency and its second harmonic to be concerned with, this still leaves transistor input and output impedance matching conditions at both these frequencies to be accounted for as potentially influential design considerations, in addition to the general dependence on the drive levels [9], [10].
The basic FET frequency doubler configuration is shown in Fig. 2.8, exhibiting a FET in common source configuration flanked by matching networks which match the gate-source port of the device to the generator at the fundamental frequency and the device drain-source port to the external load at the second harmonic frequency. A more rigorous design must be capable of undesired harmonics suppression such as a quarter-wavelength short-circuited stub, with respect to fundamental frequency, at the gate-source port of the device to suppress second harmonic frequency leakage and a quarter-wavelength open-circuited stub, with respect to fundamental frequency, at the drain-source port of the device to suppress fundamental frequency leakage. In addition, biasing circuits for the gate-source and drain-source port are also involved.
(a) (b)
Fig. 2.2 The large-signal model of a FET
Fig. 2.1 The Schottky barrier diode (SBD) with (a) general structure, (b) its equivalent circuit.
(b) (a)
Fig. 2.3 DC characteristics of the FET. (a) Ids versus Vgs and Vds, (b) Ids and Gm versus Vgs at Vds = 1.5 V.
(b) (a)
Fig. 2.4 Class A operation with (a) small-signal, (b) large-signal.
Fig. 2.5 Class B operation.
Fig. 2.6 The single-ended configuration of a frequency multiplier.
Fig. 2.8 The basic configuration of a frequency doubler.
Fig. 2.7 The balanced configuration of a frequency multiplier.
Chapter 3
F REQUENCY M ULTIPLIER USING I N G A A S P HEMT
3.1 Overview
Based on the analysis and design methodology described in Chapter 2, this chapter demonstrates a 35-to-70 GHz millimeter-wave frequency doubler using InGaAs pHEMT. The fabrication, design and simulations of the circuit will be presented in the following. The measurement considerations are also specified in detail and the measured results are depicted in the last section.
3.2 MMIC Foundry Description
The pHEMT device used in this design is fabricated by WIN Semiconductor Corp. with a standard 0.15-um high-power InGaAs pHEMT MMIC process. The process employs a hybrid lithographic approach using direct-write electron beam (E-beam) lithography for sub-micron T-gate definition and optical lithography for the other process steps. The pHEMT devices are grown using molecular beam epitaxy (MBE) on 6-inch semi-insulating (SI) GaAs substrates. The pHEMT device has a typical unit current gain cutoff frequency (ft) of 85 GHz and maximum oscillation frequency (fmax) of 200 GHz. The peak DC transconductance (Gm) at -0.45 V gate-source voltage is 495 mS/mm. The gate-drain breakdown voltage is 10 V, and the maximum drain current at 0.5 V gate-source voltage is 650 mA/mm.
Other passive components include thin-film resistor (TFR), mesa-resistor (epitaxial layer), metal-insulator-metal (MIM) capacitors, spiral inductors, and air-bridges. The wafer is thinned to 100 um for the backside metal plating and reactive ion etching (RIE) via-holes are used for DC grounding.
3.3 35-to-70 GHz Frequency Doubler using InGaAs pHEMT
3.3.1 Circuit Design
Fig. 3.1 indicates the schematic diagram of the 35-to-70 GHz frequency doubler. In order to minimize the chip area and the DC power consumption, the single-ended frequency doubler configuration was adopted. This circuit was designed using microstrip transmission lines. The nonlinear device is an InGaAs pHEMT with 4 x 75 um gate width. An effective way to employ an InGaAs pHEMT as a frequency doubler is to use it as a half-wave rectifier which is described in Section 2.3.2. Consequently, the operating condition near the pinch-off region (Vgs = -0.95V, Vds = 1.45V) with 14.5 mW power consumption was chosen to generate higher even harmonic power level. One quarter-wavelength open-circuited radial stub functions as a 35 GHz bandstop filter to reject the fundamental frequency at drain. The radial stub has wider bandwidth and higher rejection of more than 20 dB.
The gate bias is injected through a thin-film resistor connected to a decoupling MIM capacitor and a high impedance transmission line. This resistor stabilizes the InGaAs pHEMT at low frequencies. The combination of the resistor, capacitor and high impedance transmission line impedance is equivalent to a quarter-wavelength to yield the open condition at the input line. The decoupling circuit for the drain bias is realized via the similar method. The input port, with a DC blocking MIM capacitor, was matched to receive maximum power at the fundamental frequency of 35 GHz.
The output port, with a DC blocking coupled-line, was matched to deliver maximum power at second harmonic frequency of 70 GHz. The matching networks at the input and output of the circuit are achieved using 50O open-circuited stubs. A layout of the 35-to-70 GHz frequency doubler with chip size of 2 x 1 mm2 is accomplished by
the Cadence tools and is depicted in Fig. 3.2.
3.3.2 Simulated Results
The nonlinear InGaAs pHEMT model used in the simulation is a HP EEsof scalable nonlinear HEMT model (EE_HEMT model) provided by the foundry. The 35-to-70 GHz frequency doubler performance is simulated via the harmonic balance technique implemented in the commercial computer-aided design (CAD) software Agilent Advanced Design System (ADS). All the matching, biasing and other passive circuits are simulated through an electromagnetic (EM) full-wave simulator SONNET.
Conversion and rejection performances are the important specifications for a frequency doubler design. The definition of conversion gain is that the second harmonic output power minus the fundamental input power. The fundamental rejection is defined as the fundamental output power minus the fundamental input power, and the third harmonic rejection is defined as the third harmonic output power minus the fundamental input power. They are usually expressed in decibels.
The simulated conversion gain, fundamental rejection, third harmonic rejection and output power versus input power from -10 to 15 dBm at input frequency of 35 GHz are plotted in Fig. 3.3 and Fig. 3.4. It is observed that, for an input power level at 3 dBm, the conversion performance achieves a maximum conversion gain of -6.5 dB.
The saturated output power at 70 GHz is almost 0 dBm for 15 dBm input power. Fig.
3.5(a) and Fig. 3.5(b) also indicate the simulated conversion gain, fundamental rejection and third harmonic rejection as a function of input frequency from 32 to 38 GHz with an input power level of 1 and 6 dBm. It has around 1 GHz bandwidth centered at 35 GHz for a flat conversion gain. The simulated small-signal S-parameters from 20 to 50 GHz and 60 to 80 GHz, illustrated in Fig. 3.6(a) and Fig
3.6(b), give some assurances that the input and output ports are matched to nearly 50O standard. Fig. 3.7 shows the simulated large-signal S-parameters from 30 to 40 GHz with input frequency of 35 GHz and output frequency of 70 GHz for 1 dBm input power.
3.3.3 Measurement Considerations
In the millimeter-wave frequency range, two significant concerns of the 35-to-70 GHz frequency doubler should be taken into account. One is the power measurement and the other is the stability assurance.
Power Measurement To acquire the absolutely accurate power level at 70 GHz, a V-band waveguide power sensor is required. The power sensor calculates each power value of the in-band frequencies resulting in a total power level.
Accordingly, only the 70 GHz signal can exist to guarantee an accurate measurement. Indeed, a power meter, with calibrated calibration factors (CF) at each frequency, must be connected to the power sensor to depict the value of the measured power level.
Stability Assurance The stability assurance is the key point to certify the
accuracy for the power measurement. A spectrum analyzer (SA) can be used to verify whether the undesired oscillation occurs or not. Nevertheless, the commercially available SAs are not capable of directly measurement up to the V-band, W-band or higher frequencies. An external harmonic mixer should be applied with the SA to perform the down-conversion of the V-band, W-band or higher frequencies down to the lower frequency band. Therefore, we can still validate the frequency spectrum of the V-band, W-band or higher frequencies via the commercially available SAs and external harmonic mixers with the calibrated conversion loss (CL) and reference level offset. The harmonic mixing causes many
mixer products (mfRF + nfLO) at the intermediate frequency (IF) output. As a result, within a single harmonic band, a single input signal can produce multiple responses on the analyzer display as illustrated in Fig. 3.8 (in this case, the 76 GHz signal is valid), only one of which is valid. These responses come in pairs, where members of the valid response pair are separated almost to 2fIF and either the right-most (for negative harmonics) or left-most (for positive harmonics) member of the pair is the correct response. To identify the actual signals from the undesired images and spurs, a frequency-shift method can be applied. The altered quantity of the actual signals must consist with the shift of the radio frequency (RF) or local oscillator (LO) when either the RF or LO frequency is shifted. Otherwise, the remains are the undesired images and spurs. For some newer types of the SAs, identification of valid responses is achieved by simply turning on the signal-identification (SIG ID) feature.
3.3.4 Measured Results
The 35-to-70 GHz frequency doubler was measured via on-wafer probing. Fig.
3.9(a) and Fig. 3.9(b) illustrate the test setups used for the circuit characterization.
The former is established for power measurement and the latter verifies the stability assurance. A microphotograph of the 35-to-70 GHz frequency doubler is shown in Fig. 3.10.
The measured conversion gain, fundamental rejection, third harmonic rejection and output power versus input power from -10 to 15 dBm at input frequency of 35 GHz are plotted in Fig. 3.11 and Fig. 3.12. It is observed that, for an input power level at 1 dBm, the conversion performance achieves a maximum conversion gain of -8.4 dB. The saturated output power at 70 GHz is -2.6 dBm for 15 dBm input power.
Fig. 3.13(a) and Fig. 3.13(b) also indicate the measured conversion gain, fundamental rejection and third harmonic rejection as a function of input frequency
from 32.5 to 37.5 GHz with an input power level of 1 and 6 dBm. It has almost 1 GHz bandwidth centered at 35 GHz for a flat conversion gain. The measured small-signal S-parameters from 20 to 50 GHz and 75 to 80 GHz, illustrated in Fig.
3.14(a) and Fig. 3.14(b), give some agreements with that the input and output ports are matched to nearly 50O standard.
As discussed in Section 3.3.3, stability assurance is an important factor to guarantee the accuracy of the power measurement. Fig. 3.15 and Fig. 3.16 depict the frequency spectrum from 58 to 75 GHz and 75 to 110 GHz. Only the 70 and 105 GHz signals are valid and the others are images and spurs. It can be confirmed by the RF-shift technique. When the fundamental 35 GHz input signal was shifted by 1 MHz, not only the second harmonic 70 GHz output signal was shifted by 2 MHz as illustrated in Fig. 3.17(a), but also the third harmonic 105 GHz output signal was shifted by 3 MHz as illustrated in Fig. 3.17(b). If an oscillating signal appears within 58 to 110 GHz, the shift must be zero caused by the unchanged LO frequency. For example, the 61.2 and 78.09 GHz signals are shifted by 1.75 and 2.258 MHz as indicated in Fig. 3.17(c) and Fig 3.17(d). Consequently, they are not actual signals.
Similarly, the others which are verified by RF-shift, are also images and spurs except for the 70 and 105 GHz signals. Fig. 3.18(a) indicates none of the low frequency oscillations from DC to 40 GHz. The 35 GHz signal is the leakage from the input signal. A more rigorous inspection from DC to 1 GHz frequency spectrum is shown in Fig 3.18(b). Therefore, we can confirm that this 35-to-70 GHz frequency doubler is stable for the above frequency bands. Furthermore, if a low frequency oscillation caused by the impurity of power supply or other defects occurs, an out-of-chip capacitor can be added to the drain or gate port to eliminate the oscillation.
Fig. 3.1 The schematic diagram of the 35-to-70 GHz frequency doubler.
Fig. 3.2 Layout of the 35-to-70 GHz frequency doubler.
Fig. 3.3 The simulated conversion gain, 1f0 and 3f0 rejection versus input power of the 35-to-70 GHz frequency doubler.
Fig. 3.4 The simulated output power versus input power of the 35-to-70 GHz frequency doubler.
(a)
(b)
Fig. 3.5 The simulated conversion gain, 1f0 and 3f0 rejection versus frequency of the 35-to-70 GHz frequency doubler at (a) Pin = 1dBm, (b) Pin = 6dBm.
(a)
(b)
Fig. 3.6 The simulated small-signal S-parameters of the 35-to-70 GHz frequency doubler. (a) From 20 to 50 GHz for S11 and S21, (b) from 60 to 80 GHz for S22.
Fig. 3.7 The simulated large-signal S-parameters of the 35-to-70 GHz frequency doubler from 30 to 40 GHz for S11, S21 and S22.
Fig. 3.8 Signal responses produced by a 76 GHz signal in W-band.
(a)
(b)
Fig. 3.10 The microphotograph of the 35-to-70 GHz frequency doubler.
Fig. 3.9 The test setups for the 35-to-70 GHz frequency doubler characterization. (a) Power measurement, (b) stability assurance.
Conversion Gain and Rejections
Fig. 3.11 The measured conversion gain, 1f0 and 3f0 rejection versus input power of the 35-to-70 GHz frequency doubler.
Fig. 3.12 The measured output power versus input power of the 35-to-70 GHz frequency doubler.
(a)
Fig. 3.13 The simulated conversion gain, 1f0 and 3f0 rejection versus frequency of the 35-to-70 GHz frequency doubler at (a) Pin = 1dBm, (b) Pin = 6dBm.
(a)
(b)
Fig. 3.14 The measured small-signal S-parameters of the 35-to-70 GHz frequency doubler. (a) From 20 to 50 GHz for S11 and S21, (b) from 75 to 80 GHz for S22.
Fig. 3.15 Frequency spectrum from 58 to 75 GHz produced by a 70 GHz signal.
Fig. 3.16 Frequency spectrum from 75 to 110 GHz produced by a 105 GHz signal.
(a) (b)
(c) (d)
(a) (b)
Fig. 3.17 (a) A 70 GHz real signal, (b) a 105 GHz real signal,
(c) a 61.2 GHz spurious signal, (d) a 78.09 GHz spurious signal.
Fig. 3.18 Frequency spectrum produced by a 35 GHz leakage signal, (a) from 0 to 40 GHz, (b) from 0 to 1 GHz.
Chapter 4
D ESIGN M ETHODOLOGY OF B ROADBAND S WITCHES
4.1 Overview
A switch can be applied to perform the multiple accesses, which is widely used and considered as a major choice in communications. It also reduces the duplicate of the circuits with identical functions. In the low frequency below several GHz, the design of switches merely concerns the parasitics and transmission-line effects. On the contrary, these effects appear significantly in the millimeter-wave frequency range and must be taken into account in the switch design. This chapter has a full discussion on the design methodology of broadband switches and presents the Fisher’s equivalence [11] in order to broaden the bandwidth of switches.
4.2 Switching Devices
Two types of devices used commonly in the control circuits are PIN diodes and FETs. Before looking at the circuit design methods, we briefly review the significant properties of these devices.
PIN Diodes A PIN diode is a pn junction device that has a very minimally
doped or intrinsic region located between the p-type and n-type contact regions as illustrated in Fig. 4.1(a). The addition of the intrinsic or i-region results in characteristics that is very superior for certain device applications. In reverse bias the intrinsic region results in very high values for the diode breakdown voltage, whereas the device capacitance is reduced by the increased separation between the p- and n-region. In forward bias the conductivity of the intrinsic region is controlled or modulated by the injection of charge from the end regions. A practical PIN diode
consists of a lightly doped p- or n-region between the highly doped p-type and n-type contact regions, as shown in Fig. 4.1(b) and Fig. 4.1(c). To identify very lightly doped p and n material, the Greek letters are used; consequently, lightly doped p material is called p-type and lightly doped n material is called ?-type. The diode is a bias-current-controlled resistor with preferable linearity and low distortion.
PIN diodes can provide faster switching speed and can handle medium to large RF power levels. They also make excellent RF switches, phase shifters and limiters.
Sometimes the Schottky barrier diode (SBD) is applied for faster switching speed.
FETs In recent years PIN diode switches have been increasingly replaced by FETs based monolithic switches, especially for low to medium power applications. The FET switches are three-terminal devices, in which the gate bias voltage Vg controls the states of the switch. The FET acts as a voltage-controlled resistor, in which the gate bias controls the drain-to-source resistance in the channel.
The intrinsic gate-to-source and gate-to-drain capacitances and device parasitics limit the performance of the FET switches at higher frequencies. In switching applications, a low-impedance (nearly short) state is obtained by making the gate voltage equal to zero. When the negative gate-source bias is larger than the pinch-off voltage in magnitude, the FET is in a high-impedance (nearly open) state. Fig. 4.2 shows these two linear operational regions of the FET graphically [12]. Fig. 4.3 indicates the configuration of a switching FET [13]. A low-impedance state can be adequately modeled by a DC “on” resistance (Ron) which is series connection to a parasitic inductor (Lon) between the source and the drain as depicted in Fig. 4.4(a).
Additional parasitic elements exist, but have no influential RF effects, particularly if the gate bias circuitry is isolated with a large value resistor (Riso), as is indicated in Fig. 4.3. A complete equivalent circuit in a high-impedance state is illustrated in Fig.
4.4(b). This equivalent circuit is based on the device geometry and has been
described previously in [12], [14]. The off-state drain-to-source leakage resistance (Rds) is generally large enough to be neglected in circuit modeling. The drain and the source are directly capacitive-coupled (Cds) and also through the gate (Cgs and Cgd).
All of these capacitances have series parasitic resistive elements (Rgs and Rgd for Cgs
and Cgd; Rs and Rd for Cds). A simplified FET model can be used without sacrificing accuracy as shown in Fig. 4.5(a) and Fig. 4.5(b). The parasitic inductor was neglected for the on-state equivalent circuit. The off-state equivalent circuit has been reduced to a simple series resistor (Roff) and capacitor (Coff). For the simplification, it is assumed that the magnitudes of the reactances of the various capacitances are much greater than the various parasitic resistances. This assumption yields the following relationships:
Note that these relationships for Roff and Coff are frequency independent. The additional terms that have been ignored are frequency dependent. It is important to note that virtually no DC power is required by the FET switches in either state. The other advantage of FET switches is that additional biasing circuits are unnecessary because of the natural DC isolation between gate and drain (or source). The negligible DC power consumption and DC biasing isolation of the FET switches are superior to the PIN diode switches.
4.3 Broadband Switch Design
4.3.1 Basic Switch Configurations
There are two basic configurations [15] that may be used for a simple switch designed to control the flow of millimeter-wave signals along a transmission line.
One is series-type switch and the other is shunt-type switch. The third configuration that consists of the combination of the series-type and shunt-type switches is called series-shunt switch.
Before we go into the details, two essential parameters of switches must be specified. Insertion loss (IL) is defined as the ratio of the power delivered to the load in the on-state of the ideal switch to the actual power delivered by the practical switch. It is usually expressed in decibels. Isolation is a measure of the performance for the switch when it is in the off-state. Isolation (ISO) is defined as the ratio of the power delivered to the load for an ideal switch in the on-state to the actual power delivered to the load when the switch is in the off-state.
Series-type Switches Fig. 4.6(a) illustrates the equivalent circuit of a
series-type switch. The low-impedance state of the FET allows the signal to propagate, while in the high-impedance state, the incident power on the switch is mostly reflected back. Accordingly, the low- and high-impedance states of the FET are called on-state and off-state for a series-type switch. The insertion loss may be
series-type switch. The low-impedance state of the FET allows the signal to propagate, while in the high-impedance state, the incident power on the switch is mostly reflected back. Accordingly, the low- and high-impedance states of the FET are called on-state and off-state for a series-type switch. The insertion loss may be