Chapter 3 Frequency Multiplier using InGaAs pHEMT
4.3 Broadband Switch Design
4.3.4 Single-Pole m-Throw Switch
The single-pole m-throw (SPmT) switch has a single input, a single output on-arm and (m-1) output off-arms. We proposed that a SPmT shunt-type switch can also be realized using the stub filter approach. The FETs are located a quarter-wavelength apart from the input in each of the m output arms. The (m-1) off-arms have a nearly short circuit produced by the low-impedance FETs, which result in an equivalent quarter-wavelength short-circuited stub with the characteristic admittance of (m-1)Y0 shunted with the transmission path to the on-arm. Each stub must have the characteristic admittance, Y0, of the through line since it represents a transmission path when it becomes an on-arm. The last of the quarter-wavelength short-circuited stubs for each paths must have the characteristic admittance of (m-1)Y0 which is corresponding to the equivalent quarter-wavelength short-circuited stub resulted from the (m-1) shunted off-arms. Therefore, the bandwidth of this proposed SPmT switch can be almost unrestricted if an appropriate design is employed.
(a)
(b)
Fig. 4.2 Linear operational regions of a FET switch.
(c)
Fig. 4.1 (a) A general structure of the PIN diode, (b) ?-type, (c) p-type.
Fig. 4.3 The FET in switching configuration.
(a) (b)
(b)
Fig. 4.6 Series-type switch configuration, (a) transmission line model, (b) equivalent circuit model.
(a) (b)
(a) Fig. 4.4 Complete equivalent circuit for,
(a) low-impedance state, (b) high-impedance state.
Fig. 4.5 Simplified equivalent circuit for, (a) low-impedance state,
(b) high-impedance state.
(b) (a)
(b) (a)
Fig. 4.7 Shunt-type switch configuration, (a) transmission line model, (b) equivalent circuit model.
Fig. 4.8 Series-shunt switch configuration, (a) transmission line model, (b) equivalent circuit model.
ω0C / YE YT / YE θT (degree)
0.000 1.000 90.0
0.100 0.985 84.2
0.200 0.956 78.4
0.300 0.915 71.8
0.400 0.850 64.8
0.500 0.760 56.7
0.600 0.627 46.2
0.700 0.436 31.9
0.750 0.300 21.8
0.780 0.120 8.75
0.7854(π/4) 0.000 0.00 Fig. 4.9 Circuit model used for Fisher’s equivalent circuit.
Fig. 4.10 Summary of Fisher’s equivalence for simulating a quarter-wavelength stub with a capacitor and its parallel tuner.
Table 4.1 Tuned capacitor values for simulating a quarter-wavelength stub.
Fig. 4.11 Equivalent circuit for the maximally flat stub filter.
Y1 / Y0 Y2 / Y0
Table 4.2 Mumford’s design tables for the maximally flat stub filters.
Fig. 4.12 Equivalent circuit for the transmission state of the SPST switch.
(a) (a)
Fig. 4.14 (a) SPDT switch implemented by Fisher’s equivalence, (b) the equivalent filter circuit for the transmission state.
(b)
Fig. 4.13 The SPDT switch with, (a) series-type configuration, (b) shunt-type configuration.
(b)
Chapter 5
N EW B ROADBAND S WITCHES USING I N G A A S P HEMT
5.1 Overview
This chapter exhibits two newly broadband millimeter-wave switches, including a 24-to-65 GHz SPST switch and a 30.5-to-64.5 GHz SPDT switch using InGaAs pHEMT. These circuits are based on the analysis and design methodology described in Chapter 4. The fabrication, design and simulations of the circuits will be presented in the following. The measurement considerations are also specified in detail; furthermore, the measured results are depicted.
5.2 MMIC Foundry Description
The pHEMT device used in this design is fabricated by WIN Semiconductor Corp. with a standard 0.15-um high-power InGaAs pHEMT MMIC process. The process employs a hybrid lithographic approach using direct-write electron beam (E-beam) lithography for sub-micron T-gate definition and optical lithography for the other process steps. The pHEMT devices are grown using molecular beam epitaxy (MBE) on 6-inch semi-insulating (SI) GaAs substrates. The pHEMT device has a typical unit current gain cutoff frequency (ft) of 85 GHz and maximum oscillation frequency (fmax) of 200 GHz. The peak DC transconductance (Gm) at -0.45 V gate-source voltage is 495 mS/mm. The gate-drain breakdown voltage is 10 V, and the maximum drain current at 0.5 V gate-source voltage is 650 mA/mm.
Other passive components include thin-film resistor (TFR), mesa-resistor (epitaxial layer), metal-insulator-metal (MIM) capacitors, spiral inductors, and air-bridges. The wafer is thinned to 100 um for the backside metal plating and reactive ion etching
(RIE) via-holes are used for DC grounding.
5.3 24-to-65 GHz Single-Pole-Single-Throw Switch using InGaAs pHEMT
5.3.1 Circuit Design
Fig. 5.1 indicates the schematic diagram of the 24-to-65 GHz SPST switch. In order to maximize the bandwidth of SPST switch, Fisher’s method, as described in Section 4.3.2, is applied and extended to the millimeter-wave frequency range. This circuit was designed using microstrip transmission lines. The switching device is an InGaAs pHEMT with 2 x 100 um gate width. A four quarter-wavelength short-circuited stubs filter is utilized to achieve sufficient isolation. Each of the short-circuited stubs shunts with the drain port of the InGaAs pHEMT switching device. Accordingly, the drain is automatically biased at 0 V via the short-circuited stubs. The control gate bias is injected through a thin-film isolation resistor (Riso) and a high-impedance transmission line to reduce the significantly coupling leakage between the drain to gate port for the millimeter-wave signals. A general rule to employ an InGaAs pHEMT as a switching device is to bias the control voltage (Vg) at -2.0 V for the high-impedance state and 0 V for the low-impedance state. A layout of the 24-to-65 GHz SPST switch with chip size of 1.2 x 2 mm2 is accomplished by the Cadence tools and is depicted in Fig. 5.2. Nevertheless, the actually used chip area is only 1.05 x 1.3 mm2.
5.3.2 Simulated Results
The switching InGaAs pHEMT model used in this simulation is a HP EEsof scalable nonlinear HEMT model (EE_HEMT model) provided by the foundry. The 24-to-65 GHz SPST switch performance is simulated via the S-parameters and
harmonic balance techniques implemented in the commercial CAD software Applied Wave Research (AWR) Microwave Office. All the biasing and passive circuits are simulated through an electromagnetic (EM) full-wave simulator SONNET.
The simulated insertion loss and the on-state return loss from 20 to 80 GHz are plotted in Fig. 5.3. It is observed that the insertion loss is less than 3 dB and the on-state return loss is better than 8.6 dB from 24.5 to 66 GHz. Fig. 5.4 illustrates the simulated isolation and the off-state return loss from 20 to 80 GHz with the isolation better than 34 dB and the off-state return loss less than 2 dB from 22 to 80 GHz. It has almost 41.5 GHz bandwidth centered at 45.25 GHz for a flat insertion loss. The output power versus input power simulation is also exercised at 38 GHz as shown in Fig. 5.5. As indicated from the simulated data, the 1 dB compression was observed at 38 GHz for the input power of 20.5 dBm.
5.3.3 Measurement Considerations
In the millimeter-wave frequency range, two significant concerns of the 24-to-65 GHz SPST switch should be taken into account. One is the S-parameters measurement and the other is the 1 dB compression point (P1dB).
S-Parameters To acquire the S-parameters in the millimeter-wave
frequency range, the V-band and W-band test sets of the vector network analyzer (VNA) are required. The Through-Reflect-Line (TRL) or Line-Reflect-Match (LRM) calibrations must be applied to receive an accurate measurement.
1dB Compression The P1dB can be obtained by measuring the output power
versus input power where the output power gain, comparing to the small-signal gain, drops by 1 dB. In general, the P1dB of SPST switches are in the order of 20 dBm or may be higher.
5.3.4 Measured Results
The 24-to-65 GHz SPST switch was measured via on-wafer probing. Fig. 5.6(a) and Fig. 5.6(b) present the test setups used for the circuit characterization. The first and second are established for the S-parameters measurement and the P1dB, respectively. A microphotograph of the 24-to-65 GHz SPST switch is depicted in Fig.
5.7.
The control voltage for each state is 0 V for the off-state and -8V for the on-state. The measured insertion loss and the on-state return loss from 20 to 80 GHz are plotted in Fig. 5.8. It is observed that the insertion loss is less than 3 dB and the on-state return loss is better than 8.2 dB from 24 to 65 GHz. Fig. 5.9 illustrates the measured isolation and the off-state return loss from 10 to 80 GHz with the isolation better than 30 dB and the off-state return loss less than 2 dB from 10 to 80 GHz. The best isolation is 60 dB around 24 GHz. It has almost 41 GHz bandwidth centered at 44.5 GHz for a flat insertion loss. The output power versus input power measurement is also exercised at 38 GHz as shown in Fig. 5.10. As indicated from the measured data, the 1 dB compression was observed at 38 GHz for the input power of 20 dBm.
5.4 30.5-to-64.5 GHz Single-Pole-Double-Throw Switch using InGaAs pHEMT
5.4.1 Circuit Design
Fig. 5.11 illustrates the schematic diagram of the 30.5-to-64.5 GHz SPDT switch. In order to maximize the bandwidth of SPDT switch, Fisher’s method, as described in Section 4.3.2, is also applied and extended to the millimeter-wave frequency range. This circuit was designed using microstrip transmission lines. The
switching device is an InGaAs pHEMT with 2 x 100 um gate width. The four quarter-wavelength short-circuited stubs filter is utilized to achieve enough isolation.
Each of the short-circuited stubs shunts with the drain port of the InGaAs pHEMT switching device. Accordingly, the drain is automatically biased at 0 V via the short-circuited stubs. The SPDT switch must have two identically short-circuited stub filters: one is the through-path, and the other is the isolation-path. The control gate bias is injected through a thin-film isolation resistor (Riso) and a high-impedance transmission line to reduce the significantly coupling leakage between the drain to gate port for the millimeter-wave signals. A general rule to employ an InGaAs pHEMT as a switching device is to bias the control voltage (Vg) at -2.0 V for the high-impedance state and 0 V for the low-impedance state. A layout of the 30.5-to-64.5 GHz SPDT switch with chip size of 1.8 x 2 mm2 is performed by the Cadence tools and is depicted in Fig. 5.12. Nevertheless, the common via-holes, placed on the center of this chip, can save the die size by the reduction of 5 via-holes;
the actually used chip area is reduced to 1.65 x 1.5 mm2 only.
5.4.2 Simulated Results
The switching InGaAs pHEMT model used in this simulation is a HP EEsof scalable nonlinear HEMT model (EE_HEMT model) provided by the foundry. The 30.5-to-64.5 GHz SPDT switch performance is simulated via the S-parameters and harmonic balance techniques implemented in the commercial CAD software AWR Microwave Office. All the biasing and passive circuits are simulated through an EM full-wave simulator SONNET.
The simulated on-arm insertion loss, input and output return loss from 30 to 80 GHz are plotted in Fig. 5.13. It is observed that the on-arm insertion loss is less than 6 dB with the input and output return loss is better than 5 dB and 7.2 dB from 31 to
70.5 GHz. Fig. 5.14 illustrates the simulated off-arm isolation, input and output return loss from 30 to 70 GHz with the isolation better than 34 dB and the output return loss better than 2.8 dB from 30 to 70 GHz. It has almost 30 GHz bandwidth centered at 45 GHz for a flat insertion loss. The output power versus input power simulation is also exercised at 38 GHz as shown in Fig. 5.15. As indicated from the simulated data, the 1 dB compression was observed at 38 GHz for the input power of 19.5 dBm.
5.4.3 Measurement Considerations
Similarly, two significant concerns of the 30.5-to-64.5 GHz SPDT switch should be taken into account. One is the S-parameters measurement and the other is P1dB.
S-Parameters To acquire the S-parameters in the millimeter-wave
frequency range, the V-band and W-band test sets of the VNA are required. The TRL or LRM calibrations must be applied to receive an accurate measurement. The SPDT switch has three ports; therefore, the third port must be well-terminated by 50O standard.
1dB Compression The P1dB can be obtained by measuring the output power
versus input power where the output power gain, comparing to the small-signal gain, drops by 1 dB. In general, the P1dB of SPDT switches are also in the order of 20 dBm or higher. Theoretically, the third port must be well-terminated by 50O standard.
5.4.4 Measured Results
The 30.5-to-64.5 GHz SPDT switch was measured via on-wafer probing. Fig.
5.16(a) and Fig. 5.16(b) present the test setups used for the circuit characterization.
The first and second ones are established for the S-parameters measurement and the P1dB respectively. A microphotograph of the 30.5-to-64.5 GHz SPDT switch is depicted in Fig. 5.17.
The control voltage for each state is 0 V for the off-state and -2V for the on-state. The measured on-arm insertion loss, input and output return loss from 30 to 70 GHz are plotted in Fig. 5.18. It is observed that the on-arm insertion loss is less than 6 dB with the input and output return loss is better than 3.3 dB and 4.7 dB from 30.5 to 64.5 GHz. Fig. 5.19 illustrates the measured off-arm isolation, input and output return loss from 30 to 70 GHz with the isolation better than 30 dB and the output return loss better than 1.8 dB from 30 to 70 GHz. The best isolation is 50 dB around 58.5 GHz It has almost 34 GHz bandwidth centered at 47 GHz for a flat insertion loss. The output power versus input power simulation is also exercised at 38 GHz as shown in Fig. 5.20. As indicated from the simulated data, the 1 dB compression was observed at 38 GHz for the input power of 20 dBm.
Fig. 5.2 Layout of the 24-to-65 GHz SPST switch.
Fig. 5.1 The schematic diagram of the 24-to-65 GHz SPST switch.
Fig. 5.4 The simulated return loss and isolation for the off-state of the 24-to-65 GHz SPST switch.
Fig. 5.3 The simulated return loss and insertion loss for the on-state of the 24-to-65 GHz SPST switch.
Fig. 5.6 The test setups for the 24-to-65 GHz SPST switch characterization.
(a) S parameter measurement, (b) P1dB at 38 GHz.
(b) (a)
Fig. 5.5 The simulated output power versus input power of the 24-to-65 GHz SPST switch.
Fig. 5.7 The microphotograph of the 24-to-65 GHz SPST switch.
Fig. 5.8 The measured return loss and insertion loss for the on-state of the 24-to-65 GHz SPST switch.
1dB Compression Point
Input Power (dBm)
-5 0 5 10 15 20 25
Output Power (dBm)
-10 -5 0 5 10 15 20 25
Measured at 38GHz
Fig. 5.10 The measured output power versus input power of the 24-to-65 GHz SPST switch.
Fig. 5.9 The measured return loss and isolation for the off-state of the 24-to-65 GHz SPST switch.
Fig. 5.12 Layout of the 30.5-to-64.5 GHz SPDT switch.
Fig. 5.11 The schematic diagram of the 30.5-to-64.5 GHz SPDT switch.
Fig. 5.14 The simulated return loss and isolation for the off-arm of the 30.5-to-64.5 GHz SPDT switch.
Fig. 5.13 The simulated return loss and insertion loss for the on-arm of the 30.5-to-64.5 GHz SPDT switch.
(a) (b) Fig. 5.15 The simulated output power versus input power of
the 30.5-to-64.5 GHz SPDT switch.
Fig. 5.16 The test setups for the 30.5-to-64.5 GHz SPDT switch characterization.
(a) S parameter measurement, (b) P1dB at 38 GHz.
Fig. 5.17 The microphotograph of the 30.5-to-64.5 GHz SPDT switch.
Fig. 5.18 The measured return loss and insertion loss for the on-arm of the 30.5-to-64.5 GHz SPDT switch.
1dB Compression Point
Input Power (dBm)
-5 0 5 10 15 20 25
Output Power (dBm)
-10 -5 0 5 10 15 20
Measured at 38GHz
Fig. 5.19 The measured return loss and isolation for the off-arm of the 30.5-to-64.5 GHz SPDT switch.
Fig. 5.20 The measured output power versus input power of the 30.5-to-64.5 GHz SPDT switch.
Chapter 6 C ONCLUSIONS
In this thesis, two kinds of MMIC circuits using InGaAs pHEMT are demonstrated.
A 35-to-70 GHz frequency doubler with maximally conversion gain of -8.4 dB for 1 dBm input power has been reported in Chapter 3. The saturated output power at 70 GHz is -2.6 dBm for 15 dBm input power. It has nearly 1 GHz bandwidth centered at 35 GHz for a flat conversion gain. The measured results are slightly inconsistent with the simulations, which are caused by the inaccurate nonlinear device model.
A 24-to-65 GHz SPST switch and 30.5-to-64.5 GHz SPDT switch have been presented in Chapter 5. For the designed 24-to-65 GHz SPST switch, the insertion loss is less than 3 dB from 24 to 65 GHz and the isolation is better than 30 dB from 10 to 80 GHz. The best isolation is 60 dB around 24 GHz. It has almost 41 GHz bandwidth centered at 44.5 GHz for a flat insertion loss. The 1 dB compression at 38 GHz occurs around the input power of 20 dBm. The measured results completely correspond to the simulations below 50 GHz. Nevertheless, the simulated results are deviate from the measurements beyond 50 GHz resulting from the inexact device model, given by the foundry, for the two extremely control biases at higher millimeter-wave frequencies.
For the design of 30.5-to-64.5 GHz SPDT switch, the insertion loss is less than 6 dB from 30.5 to 64.5 GHz and the isolation is better than 30 dB from 30 to 70 GHz. The best isolation is 50 dB around 58.5 GHz. It has almost 34 GHz bandwidth centered at 47 GHz for a flat insertion loss. The 1 dB compression at 38 GHz occurs
around the input power of 20 dBm. Similarly, the measured results of the 30.5-to-64.5 GHz SPDT switch have a full correspondence to the simulations below 50 GHz. So far as we may see, the simulated results disagree with the measurements beyond 50 GHz.
The design of MMIC circuits is an art of elaboration. Six recommendations for the design of MMIC circuits are dedicated in the following:
1) Before the beginning of the circuit design, we must take notice of that either for the linear or nonlinear models, an accurate device characterization must be well-characterized through the test keys, instead of the device models provided by the foundry.
2) The EM simulations including the input/output (I/O) pads, passive and active devices should coincide with the totally physical structures to guarantee the precision for the circuit simulations.
3) In order to reduce the parasitic and coupling effects, an appropriate layout must be carefully taken into account with a possibly minimum area usage;
furthermore, the width of each power line must be calculated for sufficiently power capability and moderately power consumption.
4) A suitable commercially CAD software for the circuit simulations should be applied to verify the validity of the circuit designs; in addition, the variation analyses including MMIC fabrications, temperature, parasitic and on-board bonding-wire effects are critical to certify the sensitivity and robustness of the circuits.
5) Some mature design procedures for the design of MMIC circuits, like design rule check (DRC) and layout versus schematic (LVS), should be adopted and sometimes the layout parasitic extraction (LPE) can be used for the post
layout simulations to obtain more accuracy.
6) The feasibility of measurements for the well-designed circuits must be taken into consideration, especially for the totally on-wafer probing tests.
These recommendations are extremely valuable for the design of MMIC circuits. The author suggests that the MMIC designers could follow these rules as the best regards.
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