This thesis is organized as six chapters. Brief content of each chapter is described as follows. In chapter2, the fundamental concepts and architectures of DAC are described first. In addition, the static and dynamic specifications that will impact a DAC’s performance are discussed.
Chapter 3 presents the non-idealities of current-steering DAC, including finite output impedance, mismatch in current source, timing non-idealities, and non-idealities due to switching in a current-steering DAC. In Chapter 4, based on the consideration discussed in chapter 2 and chapter 3, the design and implementation of a 12-bit 250MHz current-steering with the partial random element matching segmented architecture DAC is described in chapter 4.
Chapter 5 presents the simulation and measurement results. Conclusion and future work are in chapter 6.
Chapter2
Nyquist-Rate Digital-to-Analog Converter
Digital-to-analog converters (DACs) are essential in data processing systems. DACs interface the digital output of signal processors with the analog world and reconstruct the continuous-time analog signal. The digital-to-analog (D/A) converts a discrete amplitude, discrete time signal to a continuous amplitude, continuous time output.
A DAC is shown in Fig. 2.1. It converts a digital signal into an analog representation [25]. If the DAC generate large glitches during switching from one code to another, then a deglitching circuit is used to mask the glitches. Finally a low-pass filter is required to suppress the sharp edges introduced by the DAC [24].
Figure2.1 Digital-to-analog conversion
In this chapter, the fundamental of DAC and different techniques for converting a digital signal into an analog signal representation is presented. The approaches differ in speed, chip area, power efficiency, achievable accuracy, etc
2.1 Ideal D/A Converter
A digital-to-analog converter produces an analog output Vout that is proportional to the digital input Bin. For a N-bit D/A converter shown in Fig. 2.1, the output Vout can be expressed as:
(
020 121 22n 2 12n 1)
out ref n n
V =V D +D ++D− − +D− − (2.1)
where Di equals 1 or 0. We also define b0 as the least significant bit (LSB) and Dn-1 as the most significant bit (MSB). In a D/A converter, a further classification is by the scaling methods. Three methods are called current, voltage and charge scaling.
Figure 2.2 Block diagram of a n-bit D/A converter
2.2 Performance Metrics
The characterization of DACs is very important in understanding its design. The characteristics of the digital-analog converter can be divided into static, dynamic and dynamic range properties [1].
2.2.1 Static Performance
Five basic static parameters are major content of this section of this section, which are offset error, gain error, INL, DNL and monotonicity. To distinguish all values of calculations in the DAC, Xa(k) corresponds to the actual analog output for kth input code and Xi(k) corresponds for the ideal one.
Offset Error
The analog output should be 0V for digital input=0. However, an offset exists if the analog output voltage is not equal to zero. This can be seen as a shift in the transfer curve as illustrated in Fig. 2.3.
A na log O ut put V al ue
Figure 2.3 Non-ideal transfer curve with offset error
Gain Error
Gain error is the difference at the full-scale value between the ideal and actual when the offset error has been reduced to zero. For a non-ideal transfer curve with gain error shown in
Fig. 2.4, the gain error can be expressed as:
(2 1)
a i
N
X X
GainError
LSB
= −
− i (2.2)
Figure 2.4 Non-ideal transfer curve with gain error
Differential Non-Linearity(DNL)
The step size in the non-ideal data converter deviates from the ideal size △ and this error is called the differential nonlinearity (DNL) error. For a DAC the DNL can be defined as the difference between two adjacent analog outputs minus the ideal step size, i.e.
DNLk = Xa k, +1−Xa k, − ∆ (2.3)
The DNL is often normalized with respect to the step size to get the relative error, i.e.
k Xa k, 1 Xa k,
DNL + − − ∆
= ∆ (2.4)
The above definitions are often most practical for DACs since the analog values can be directly measured at the output
Integral Non-Linearity (INL)
The total deviation of an analog value from the ideal value is called integral nonlinearity (INL). For non-ideal transfer function with INL and DNL errors shown in Fig.
2.5, the normalized INL can be expressed as
k Xa k, Xi k,
INL −
= ∆ (2.5)
The relation between INL and DNL is given by exclude dynamic errors appearing at high signal frequencies. The DNL and INL are therefore usually used to characterize the static performance.
∆
Figure2.5 Non-ideal transfer function with INL and DNL errors of DAC
Monotonicity
If the analog amplitude level of the converter increases with increasing digital code, the converter is monotonic. An example of a non-monotonic DAC is shown in Fig. 2.6.
Xa
This implies that the DNL errors are less than one LSB , i.e.
k 1
DNL ≤ LSB for all k (2.8)
It should be noted that the above relations are sufficient to guarantee monotonicity, but it is possible to have a monotonic converter that does not meet the relations in (2.7) and (2.8).
There are some data converters architectures that are monotonic by design, e.g. a thermometer coded DAC.
2.2.2 Dynamic Performance
In addition to the static errors that are caused by mismatch in the components in the data converter, several other error sources will appear when the input signal change rapidly. These dynamic errors are often dependent on signal frequency and increases with signal amplitude and frequency. They appear in data converter but are usually more critical in DACs since the shape of the analog wave form determines the performance.
Settling Time
The settling time is defined as the time it takes for the converter to settle within some specified amount of the final value. The primary dynamic characteristic of the DAC is the conversion speed. The setting time define the operation frequency of DAC. The factors that determine the settling time of the DAC are the gain bandwidth, slew rate of op amp and parasitic capacitor. The output of transition can be illustrated as Fig. 2.7.
Figure 2.7 Actual output signal and ideal output signal (dashed) of a DAC
The settling can be divided in two phases, a non-linear slewing phase and a linear settling phase. The output signal of an actual DAC can not change its value instantly. The time it takes for the output to settle within a certain accuracy of the final value, for instance 0.1%, is called the settling time Ts, and determines the highest possible speed of the circuit.
The slewing phase should be as small as possible since it both increases the settling time and introduces distortion in the analog waveform. The slewing is normally caused by a too small bias current in the circuit driving the output and is therefore increased for large steps when more current is needed.
Glitch
When the switching time of different bits in binary weighted DAC is unmatched, the glitch occurs. As Fig. 2.8, if a DAC decodes 011 code to 100 code sequentially, the fast MSB changes previously than others. The output of a DAC will occur the error value. The plus effect of the output caused by different switching is called glitch.
Xa
2.2.3 Dynamic range
For DACs used in communications applications, the INL and DNL are not sufficient to characterize the performance. It is more convenient to characterize the performance in the frequency domain using measures as the signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR). The can be illustrated as Fig. 2.9.
Figure 2.9 Output spectrum of a DAC
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio of the signal power and the total noise power. SNR is usually expressed in dB as
Signal Power SNR( ) 10 log
Total Noise Power
dB
= ∗
(2.9)
Spurious Free Dynamic Range (SFDR)
The spurious free dynamic range (SFDR) is the ratio of the power of the signal and the
power of the largest spurious within a certain frequency band. SFDR is usually expressed in
The total harmonic distortion (THD) is the ratio of the total harmonic distortion power and power of the fundamental in a certain frequency band, i.e.
Total Harmonic Distortion Power fundamental and the total noise and distortion power within a certain frequency band, i.e.
Signal Power combine an appropriate set of signals that are all related in a binary fashion. This binary array of signals might be currents, but binary-weighted arrays of charge are also commonly used.
The binary weighted DAC utilizes a number of reference element that are binary weighted.
The output signal can be written as
( )
0( ) ( )
N-1( )
resistance ratio of only 2, independent of the number of bits, N.The R-2R ladder can be used to obtain binary-weighted current while using only a single-size resistor. (The resistors of size 2R are made out of two resistors size R, to improve matching properties). As a result, this R-2R approach usually gives both a smaller size and a better accuracy than a binary-size approach.
A N-bit DAC that uses an R-2R ladder is shown in Fig. 2.10. For the R-2R based circuit, we see that ratio through the switches is still large, and thus the switch sizes are usually scaled in size to accommodate the widely varying current levels. One approach to reduce this current ratio is shown in Fig. 2.10, where equal current flow through all the switches. However, this configuration is typically slower since the internal nodes of the R-2R ladder now exhibit some
voltage swings. stored on a number of binary weighted capacitors is used to perform the conversion. Fig. 2.11 is an example of a N-bit converter. Typically, the weighted capacitors are created using a number of unit capacitors.
At time nT ( on phase ψ1 ), the bit bi determine which of the binary weighted capacitors that should be charged from the reference voltage,V ref . During this phase, the plates of capacitor CNare connected to ground and virtual ground at the input of the op amp, i.e., there is no charge on CN, and qN (nT) = 0. Capacitor CC is used for offset compensation.
The total charge on the binary weighted capacitors at time nT is given by
1 1
At time nT +Τ/2 , on phaseψ2 , the weighted capacitors are discharged since their plates are connected to DC and virtual grounds. The charge is redistributed to ground and CN . The
charge onCN at the end of the settling is
( 1 ) ( 2)
N 2 N out
q nT+ T =C ⋅V nt+T (2.17)
Charge conservation gives
( 1 ) ( )
N 2 T
q nT+ T = −q nT (2.18)
Using (2.11) and (2.12) in (2.13) we have
( 2) ( )
out ref
N
V nt T C k nT V
+ =C ⋅ ⋅ (2.19)
The architecture in Fig. 2.6 is insensitive to offset voltage and finite gain of the amplifier. The limitations of the converter are the matching of the capacitors, the switch-on resistance, and finite bandwidth of the amplifier.
Figure2.11 The architecture of a N-bit charge-redistribution DAC
2.3.3 Current-Mode DAC
Current-mode DACs are very similar to resistor-based converter, but are intended for higher-speed applications. The basic idea is to switch currents to either the output or to ground, as shown in Fig. 2.12.
Figure2.12 N-bit binary-weighted current-mode DAC
Here, the output current is converted to a voltage through the use of Rf, and the upper portion of each current source always remains at ground potential.
The technology of usable switched-current of the current-mode is gone to realize. The switched-current technique is a natural choice in a CMOS process, since reference and sum element as well as switches are relatively easy to implement. The current-steering DAC has the advantage of being quite small for resolution below 10 bits and it is very fast. The major disadvantage is the sensitivity to device mismatch, glitches, and current source output impedance for higher number of bits. Another good property of the current-steering DAC is that its high power-efficiency since all power is directed to the output. The current-steering DAC is suitable for high-speed high-resolution applications, especially when special care is taken to improve the matching of the converter.
To achieve monotonicity, reduce the influence of glitches and reduce the sensitivity to matching errors, the DAC should be segmented into a coarse and fine part. The coarse part is
realized by thermometer coded and fine part is kept binary weighted. This is referred to as a segmented converter and is discussed further.
2.4 Thermometer Coded DAC Architecture
The thermometer coded DAC architecture utilizes a number of equally weighted elements. The binary input code is encoded into a thermometer code as illustrated in Table 2-1 for 3-bit input code. Generally, with N binary bits, we have M=2N-1 thermometer coded bits. The analog output at time nT is give by matching of the individual element becomes simpler than for the binary case. The total sum of all weights is 2N-1. The transfer function of the thermometer code converter is monotonic and the DNL and INL is improved compared to the binary version. The requirements on element
matching are also relaxed. In fast, if the matching is within a 50% margin, the converter is still mon0tonic.
Figure 2.13 A thermometer coded current-steering DAC with encoding circuit
In Fig. 2-13 we show a current-steering implementation of a thermometer coded DAC with binary-to-thermometer encoder. All current sources are equally large, Iunit. For a large number of bits, the digital circuit converting the binary code (X) into thermometer code (C) and the number of interconnecting wires become large, since the number of outputs is growing exponentially. This implies a more complex circuit layout. The encoding circuit can easily be pipelined and the propagation time through the encoder can be controlled.
2.5 Hybrid DAC Architecture
Combining the techniques discussed in Fig. 2-14 for realizing different portions of a D/A converter result in hybrid designs. Hybrid designs are an extremely popular approach for designing converters because they combine the advantages of binary-weighted and thermometer-coded architectures. For example, it is quite common to use a thermometer-code approach for the top few MSBs while using a binary-scaled technique for the lower LSBs. In this way, glitch is significantly reduced and accuracy is high for the MSB where it is needed
most. However, in the LSBs where glitch and accuracy requirements are much reduced, valuable circuit area is saved with a binary-scaled approach.
Figure 2-14 A N-bit segmented DAC where M MSBs are thermometer-code
2.6 Summary
In this chapter, the fundamental of the digital-to-analog Converters (DACs) is presented first. The performance parameters used to characterize the specifications of DAC is also described. Also, different types of Nyquist-Rate DACs are introduced.
According to the discussions of the advantages and disadvantages for different type DACs, we can choose the suitable architecture for our applications among several trades-off, like power consumption, speed, and die area.
Chapter3
System Analysis of DAC Design
Current-steering DAC is a popular topology when high speed and high resolution is needed since it can drive resistive loads directly, and do not require high speed amplifiers at the output. A differential output type current steering DAC is preferred because it can lower the common mode noise and second harmonic distortion. But it still has some non-idealities that will degrade the performance of the DAC. The errors sources that cause the non-idealities include finite output impedance effect, current source mismatch, timing non-idealities and non-idealities due to switching the current cells [1].
3.1 Major Error Sources in Current-steering DACs
Output impedance of current source:
The finite output resistance affects the linearity of the converter. This is primarily due to the fact that the output resistance of the converters is signal-dependent. We often use the cascsde structure to increase the output impedance of current source.
Matching errors:
Matching errors in the process cause the oxide thickness and threshold voltage, to vary, the unit currents are unequal, which also affects the linearity. The matching errors are of both stochastic and deterministic nature.
Doping and thermal gradients:
Since doping and thermal gradients oxide thickness and mobility to vary, the unit
currents are unequal, which also affects the linearity. This error is often overcome by using converter. Sources of random noise include the thermal noise of transistors and resistors and the coupling of noise from digital circuitry into the analog circuits through the common substrate, package, and supply lines.
Harmonic Distortion:
Signal-dependent non-idealities result in harmonic distortion in the DAC output. Ideally, even harmonics are completely cancelled through the use of a differential topology, but mismatch between the differential paths results in some residual even-harmonic distortion. In the following section, we discuss the non-idealities of current-steering DAC and the effects they will cause on both static performance and spectrum specification.
3.2 Finite output impedance of current source
The output impedance and the parasitic impedance of interconnections and switches in the converter will strongly influence the performance. Any non-ideal current source has a finite output resistance and can be modeled [1].
Fig. 3.1 shows a current-steering array including output impedance of each current source. It is a thermometer coded structure, where Ro represents the output impedance of each
Figure 3.1 Current sources with finite output impendence
current source. For the thermometer code of height N, the actual output voltage is
0
therefore the ideal output voltage for height j is
0
The difference between the ideal and actual voltage can result in INL error
( )
Fig. 3.2 shows an example of INL profile for a 12-bit DAC with variable current source
output impedance. From the figure we can find that INL decreased when the current source impedance increases. Also, the maximum INL value occurs when the middle digital input is applied.
Figure 3.2 The INL Profile of 12-bit DAC with different current source output impedance
Besides of static linearity, the finite output impedance of the current sources also has relation with dynamic performance. The SFDR is an index between dynamic performance and output impedance. The equation of SFDR can be calculated as
2
In general, output impedance of current source is farther great than output loading.
When ρ is very high, the approximate equation can be written as
( )
SFDR 40log 1 -12 N-2 dBc ρ
≈
(3-6)
Figure 3.3 shows another example how the output impedance affects the SFDR for differential output. This implies the output impedance of unit current source must be larger than 3MΩ if the SFDR is guaranteed to larger than 72dB.
Figure 3.3 Simulate SFDR in different output-impedance conditions
3.3 Current Source Mismatch
Intrinsic high linearity can be achieved by tacking all possible systematic, graded, and random errors. Important effects that must be taken are
1. Random errors: device mismatches.
2. Systematic and graded errors: edge effects, voltage drops in the supply lines,
thermal gradients, doping gradients, and oxide thickness gradients resulting in a Vt
shift across in the die.
In Fig3.4 show the average simulated and calculated SFDR for 12-b DAC with 8MSB thermometer-coded that have different mismatch pattern. Specifically input signal was formed by adding dither to the signal where amplitude is full swing, the ratio of the input signal frequency Fin to clock frequency Fclk is 1/4, and then quantizing the result to the resolution of DACs. The dither added to the sinusoidal input, was a while sequence with a triangular probability density function supported on, so the quantization error was white noise[15]. The curves are saturated at low mismatch, since in the simulations the harmonics are hidden in the noise floor.
Figure 3.4 The average simulated and calculated SFDR for a 12-bit DAC with 8MSB thermometer-coded that have different mismatch pattern
The random error of the current sources is determined by matching properties of the
MOS transistors. Consider two normally identical current sources and random mismatch between two identical devices as shown in Fig. 3.5. The output currents I1 and I2 exhibit
MOS transistors. Consider two normally identical current sources and random mismatch between two identical devices as shown in Fig. 3.5. The output currents I1 and I2 exhibit