具有部分隨機匹配的12位元250百萬赫芝電流式互補式金氧化半導體數位類比轉換器

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國

立

交

通

大

學

電機學院 IC 設計產業研發碩士班

碩

士

論

文

具有部分隨機匹配的 12 位元 250 百萬赫芝電流式互補式

金氧化半導體數位類比轉換器

12-bit 250MSample/s Current-Steering CMOS D/A

Converters with Partial Random Element Matching

研究生：白逸維

指導教授：洪崇智教授

中

華

民

國

九

十

六

年

十

二

月

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具有部分隨機匹配的 12 位元 250 百萬赫芝電流式互補式

金氧化半導體數位類比轉換器

12-bit 250MSample/s Current-Steering CMOS D/A

Converters with Partial Random Element Matching

研究生：白逸維 Student：Yi-Wei Pai

指導教授：洪崇智 Advisor：Chung-Chih Hung

國立交通大學

電機學院ＩＣ設計產業專研發專班

碩士論文

A Thesis

Submitted to College of Electrical and Computer Engineering National Chiao Tung University

in partial Fulfillment of the Requirements for the Degree of

Master in

Industrial Technology R & D Master Program on IC Design

December 2007

Hsinchu, Taiwan, Republic of China

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具有部分隨機匹配的 12 位元 250 百萬赫芝電流式互補式金

氧化半導體數位類比轉換器

學生：白逸維指導教授：洪崇智博士

國立交通大學電機學院產業研發碩士班

摘

要

高速數位類比轉換器是目前高效能系統，如資料通訊系統中不可獲缺的主要電路。然而電流驅動式數位類比轉換器因為製程不匹配效能往往受靜態和動態線性度限制。在本篇論文，主要設計一個簡單的隨機架構去改善製程不匹配。我們利用多輸入多輸出多工器架構再配合隨機產生器讓原本固定的線路去隨機改變，再配合特殊的電流源開關的佈局去改善不同製程的改變，我們可以打亂諧波，將能量平均分散到 noise floor 而增加 SFDR。本論文是配合上述簡單隨機架構的一個 12 位元 250MHz 數位類比轉換器，在數位類比轉換器電路的實現，切換電流源式是一個很好的實現方法。在數位類比轉換器中包含在較低的 4 位元為 2 進位權重架構和較高的 8 位元為含有隨機匹配的溫度計編碼架構。除此之外，為了增進數位類比轉換器的動態效能及提高解析度與元件間的匹配，分別使用了抑制突波的拴鎖器和特殊的佈局，來增加數位類比轉換器的效能。同時也考量了在佈局繞線時產生的寄生電容，所造成速度還有信號不同步的效應。數位類比轉換器採用 TSMC 0.18 µm 1P6M mixed‐signal CMOS 製程來實現，沒有部分隨機架構整體晶片的面積為 1.788 mm2 ，另外有含部份隨機架構整體晶片面積為 1.838 mm2 。

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12-bit 250MSample/s Current-Steering CMOS D/A

Converters with Partial Random Element Matching

Student：Yi-Wei Pai Advisor：Dr. Chung-Chih Hung

Industrial Technology R & D Master Program of

Electrical and Computer Engineering College

National Chiao Tung University

ABSTRACT

Current-Steering digital-to-analog converters (DACs) are very significant blocks of nowadays high-performance systems, such as data communication links using multilevel signaling. However, these current-steering DACs suffer from the element mismatch of technologies and this limits both the static and dynamic performance. This thesis proposes a simple random structure to improve the element mismatch is presented. We can use a multiplexer with 8-bit input and 8-bit output, to implement the random selection. The random generator controls the selection of the element in the MSB part so that the harmonics caused by mismatch can be attenuated. The simple random structure can be used to randomize tones such that spurious-free dynamic range is increased. To cooperate with a special geometrical arrangement of unit cells in the current sources of the MSB, along with a new switching sequence, results in full cancellation of gradient errors.

Utilizing the simple random structure, a 12-bit 250-MSample/s current-steering D/A converter is implemented in this thesis. The DAC includes a 4-bit binary-coded LSBs, 8-bit

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MSBs with thermometer decoders, and random element matching. The differential switches of current sources are controlled by de-glitch latch. The routing complexity and parasitic capacitance have to be considered for speed and signal synchronization.

12-bit current-steering D/A converters in a TSMC 0.18µm CMOS technology are presented. The simulation results of a 12-bit current-steering D/A converter with the partial random element matching show that with the signal frequency of 100.83 MHz at the update rate of 250 MHz, the SFDR is 66.4 dB. The differential nonlinearity and integral nonlinearity are below 0.5 and 0.7 least significant bits (LSB’s), respectively. The converter consumers a total power of 75 mW and its active area is 1.838 mm2. The simulation results of D/A

converter without the partial random element matching shows that with the signal frequency of 100 MHz at the update rate of 500 MHz, the SFDR is 68.9 dB. The differential nonlinearity and integral nonlinearity are below 0.8 and 0.8 LSB’s, respectively. The converter consumers a total power of 73 mW and its active area is 1.788 mm2.

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誌

謝

誌

謝

誌

謝

首先要感謝指導老師洪崇智老師在我兩年的研究生活中，提供良好的學習環境，以及對我的指導與照顧，學生銘記在心，在此向老師致上由衷感謝。另承蒙黃淑絹、李育民及溫宏斌教授對本論文的諸多指導與建議，使其更趨完備，在此感謝每一位老師。其次我要感謝天佑、文弘、介偉、哲揚、宗諺、家敏、政翰、琳家、家泰和俊達學長在這兩年的幫助與指導，在研究上的傾囊相授，以及同窗德文、建豪、正昇、明澤和國璽，在精神上及學業上的互相扶持，尤其是電資710實驗室的同學們，兩年來陪我ㄧ塊兒努力奮鬥，一起渡過同甘苦的日子，也因為你們，讓我的碩士班生活更加多采多姿，增添許多快樂與充實的回憶。此外也感謝學弟們永洲、智龍、竹緯、文霖，楓翔和介仁的熱情支持，為這間實驗室帶來許多歡笑與活力，感謝大家。最後，感謝我的父母與家人，感謝他們提供一個穩定且健全的環境，他們的默默支持及諄諄教誨，使我常感懷於心，讓我能全心投入研究之中，無後顧之憂的完成我的學業與論文。在此致上最高的敬意，希望你們永遠健康快樂。總之，我要感謝所有關心我、愛護我和曾經幫助過我的人，願我在未來能有ㄧ絲的榮耀歸於最愛我的家人、老師以及朋友，謝謝你們。白逸維國立交通大學中華民國九十六年十二月

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Abstract (Chinese)

I

Abstract (English)

II

Acknowledgment

IV

V

List of Figures

VII

List of Tables

XI

Chapter 1. Introduction

1

1.1 Motivation 1

1.2 Organization 2

Chapter 2. Nyquist-Rate Digital-to-Analog Converter

3

2.1 Ideal D/A converter 3

2.2 Performance Metrics 4

2.2.1 Static Performance 4

2.2.2 Dynamic Performance 9

2.2.3 Dynamic range 11

2.3 Binary Weighted DAC Architecture 12

2.3.1 R-2R Ladder DAC 13 2.3.2 Charge Redistribution DAC 14 2.3.3 Current-Mode DAC 15 2.4 Thermometer Coded DAC Architecture 17

2.5 Hybrid DAC Architecture 18

2.6 Summary 19

Chapter 3. System Analysis of DAC Design

20

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3.2 Finite output impedance of current source 21

3.3 Current Source Mismatch 24

3.4 Switched Gate Driver 31

3.5 Random routing 33

3.6 Summary 36

Chapter 4. Circuit Design of DAC

37

4.1 The System Structure of DAC 37 4.2 Digital Circuits 39

4.2.1 Thermometer decoder 40 4.2.2 Randomizer 41 4.2.3 High speed latch 43 4.3 Current Cell 45 4.3.1 Implementation of Switch Unit Current Cell 45 4.3.2 Reference Current Generation 47 4.4 Layout 48

4.5 Summary 54

Chapter 5. Simulation and Measurement Results

55

5.1 Simulation results 55

5.2 Test Circuits 59

5.3 Measurement Results 61

Chapter 6. Conclusions and Future Work 66

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List of Figures

Chapter 2

Fig. 2.1 Digital-to-analog conversion 3

Fig. 2.2 Block diagram of a N-bit D/A Converter 4

Fig. 2.3 Non-ideal transfer curve with offset error 5 Fig. 2.4 Non-ideal transfer curve with gain error 6 Fig. 2.5 Non-ideal transfer function with INL and DNL errors of DAC 7

Fig. 2.6 A non-monotonic DAC 8

Fig. 2.7 Actual output signal and ideal output signal (dashed) of a DAC 9

Fig. 2.8 Glitch output 10

Fig. 2.9 Output spectrum of a DAC 11

Fig. 2.10 N-bit R-2R based DAC 14

Fig. 2.11 The architecture of a N-bit charge-redistribution DAC 15

Fig 2.12 N-bit binary-weighted current-mode DAC 16

Fig 2.13 A thermometer coded current-steering DAC with encoding circuit 18 Fig 2-14 A N-bit segmented DAC where M MSBs are thermometer-code 19

Chapter 3

Fig. 3.1 Current sources with finite output impendence 22 Fig. 3.2 The INL profile of 12-bit DAC with different current source

output impedance 23

Fig. 3.3 Simulate SFDR in different output-impedance conditions 24 Fig. 3.4 The average simulated and calculated SFDR for a 12-bit DAC with 8MSB

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Fig. 3.5 Identical MOS current sources and random mismatch between two

identical devices 26

Fig. 3.6 Minimum gate-area of the unit current source transistor as function of the gate

voltage overdrive 28

Fig. 3.7 (a) Linear error (first-order error)

(b) Systematic error (Second-order error) In DAC current element 30

Fig. 3.8 Current cell matrix with dummy cell 31

Fig. 3.9 The Output Waveforms of Switch Drivers used for Driving the Current Cell. (a) Output switch gate waveforms

(b) High Crossing Points Due to Use the Driver of Intrinsic Delay (c) Middle Crossing Points

(d) Low Crossing Points Due to Use the Driver of Intrinsic Delay

(e) Low Crossing Points Due to Use the Driver of Rise / Fall Time 32 Fig 3.10 Randomization of bits in a thermometer coded DAC. The matching error

becomes uncorrelated with the signal. 33 Fig 3.11 A 2M-1 bit randomizer receiving at random generator controls 35

Fig 3.12 Output amplitude spectrums from a 12-bit DAC with 8MSB thermometer-coded DAC (a) without randomization and (b) with randomization 35

Chapter 4

Fig. 4.1 12-bit DAC Architecture 38 Fig. 4.2 Simplified block diagram of the DAC architecture 39 Fig. 4.3 (a) A 2M bit input and 2M bit output randomizer

(b) 8-bit input and output MUX with 3-bit selection. 42

Fig. 4.4 Random Generator 43

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Fig. 4.6 (a) The circuit schematic of the cascode current cell (b) Gain-Boosting 46 Fig. 4.7 The Circuit Schematic of the Bias Circuit 47 Fig. 4.8 “Balanced ring” technique of this work for reduction of quadratic errors.

(a) (1,8) rings (b) (2,7) rings (c) (3,6) rings (d) (4,5) rings 48 Fig. 4.9 Orientation of the axes X’ and Y’. Rotation of the quadratic error compared

error compared to the main axes of the current source array. 50 Fig. 4.10 Selection sequence for MSB part of input code for improved “balanced-ring”

technique 51 Fig. 4.11 The Final Layout 53

Chapter 5

Fig. 5.1 Sine wave spectrum for (a) Fs = 500 MHz and Fsig = 1.46 MHz

(b) Fs = 500 MHz and Fsig = 195.8 MHz without partial random element

matching 56

Fig. 5.2 The SFDR of input frequency between 0.488 MHz and 245.6 MHz at the sample rate 500 MHz without partial random element matching 56 Fig. 5.3 The differential nonlinearity (DNL) and integral nonlinearity (INL)

without partial random element matching 56 Fig 5.4 Sine wave spectrum for (a) Fs = 250 MHz and Fsig = 0.244 MHz

(b) Fs = 250 MHz and Fsig = 100.83 MHz with partial random element

matching 57

Fig. 5.5 The SFDR of input frequency between 0.244 MHz and 122.8 MHz at the sample rate 250 MHz with partial random element matching 58 Fig. 5.6 The differential nonlinearity (DNL) and integral nonlinearity (INL)

with partial random element matching 58 Fig. 5.7 Testing Setup 60

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Fig. 5.8 Power Supply Regulator 61

Fig. 5.9 Sine wave spectrum for Fs = 20 MHz and Fsig = 1 MHz 62

Fig 5.10 Sine wave spectrum for Fs = 100 MHz and Fsig = 2 MHz 62

Fig 5.11 Sine wave spectrum for Fs = 100 MHz and Fsig = 9.8758 MHz 62

Fig. 5.12 Sine wave spectrum for Fs = 200 MHz and Fsig = 19.81 MHz 63

Fig 5.13 The SFDR of input frequency between 3 MHz and 34.33 MHz at the sample rate100 MHz 64

Fig 5.14 The differential nonlinearity (DNL) and integral nonlinearity (INL) 64

Fig 5.15 The die microphotograph 65

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List of Tables

Chapter 2

Table 2-1 Decimal, binary, thermometer code representations 17

Chapter 4

Table 4.1 Truth Table of a 4-to-16 Line Decoder 40 Table 4.2 Boolean functions between the binary-input and thermometer-output 41

Chapter 5

Table 5-1 The total simulation results of this DAC 59 Table 5-2 The total measurement results of this DAC 65

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Chapter1

Introduction

In many signal processing and telecommunication applications, the digital-to-analog converter (DAC) is a critical building block limiting the accuracy and speed of the overall system. When applications require high speed and high resolution, the current-steering DAC architecture is almost exclusively used. It is more convenient to characterize the performance in the frequency domain using measures as the spurious-free dynamic range (SFDR) [1]. Since be specified as circuit errors, because the impact of DACs errors can be modeled.

1.1 Motivation

For high-speed application, the current-steering DACs are often used, since they can drive an output resistive load directly without requiring the use of an extra buffer [2]. However, the static linearity of current-steering DACs is sensitive to current-source mismatch [3]-[18]. Designers often use large devices [3], randomized layouts [8], [10], [12], calibration [15], etc. to reduce this mismatch. These techniques improve linearity, but at the expense of die area or dynamic performance.

In this thesis, a new simple random structure to improve the matching accuracy of the current source and efficiently increase the SFDR is applied for high-resolution and high-speed DACs. The DAC noise is transferred to white noise and the SFDR is optimal. The yield performance of DACs is enhanced by the new algorithm. In additional, a special layout method called Balanced-Ring [12] will help overcome the variation across a range of process. A high-speed

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and high-accuracy latch is designed to attain good dynamic performance.

12-bit 250MHz current-steering segmented architecture DACs fabricated in TSMC 0.18µm CMOS is designed by using segmented current-steering architecture that consists of 8 MSB’s of unary cells and 4 LSB’s of binary cells. In addition, a high speed and low crossing point switch driver is designed to minimize glitch error during dynamic switching transition.

1.2 Organization

This thesis is organized as six chapters. Brief content of each chapter is described as follows. In chapter2, the fundamental concepts and architectures of DAC are described first. In addition, the static and dynamic specifications that will impact a DAC’s performance are discussed. Chapter 3 presents the non-idealities of current-steering DAC, including finite output impedance, mismatch in current source, timing non-idealities, and non-idealities due to switching in a current-steering DAC. In Chapter 4, based on the consideration discussed in chapter 2 and chapter 3, the design and implementation of a 12-bit 250MHz current-steering with the partial random element matching segmented architecture DAC is described in chapter 4.

Chapter 5 presents the simulation and measurement results. Conclusion and future work are in chapter 6.

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Chapter2

Nyquist-Rate Digital-to-Analog Converter

Digital-to-analog converters (DACs) are essential in data processing systems. DACs interface the digital output of signal processors with the analog world and reconstruct the continuous-time analog signal. The digital-to-analog (D/A) converts a discrete amplitude, discrete time signal to a continuous amplitude, continuous time output.

A DAC is shown in Fig. 2.1. It converts a digital signal into an analog representation [25]. If the DAC generate large glitches during switching from one code to another, then a deglitching circuit is used to mask the glitches. Finally a low-pass filter is required to suppress the sharp edges introduced by the DAC [24].

Figure2.1 Digital-to-analog conversion

In this chapter, the fundamental of DAC and different techniques for converting a digital signal into an analog signal representation is presented. The approaches differ in speed, chip area, power efficiency, achievable accuracy, etc

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A digital-to-analog converter produces an analog output Vout that is proportional to the

digital input Bin. For a N-bit D/A converter shown in Fig. 2.1, the output Vout can be

expressed as:

(

0 1 2 1

)

02 12 22 12 n n out ref n n V V D D D − D − − − = + ++ + (2.1)

where Di equals 1 or 0. We also define b0 as the least significant bit (LSB) and Dn-1 as

the most significant bit (MSB). In a D/A converter, a further classification is by the scaling methods. Three methods are called current, voltage and charge scaling.

Figure 2.2 Block diagram of a n-bit D/A converter

2.2 Performance Metrics

The characterization of DACs is very important in understanding its design. The characteristics of the digital-analog converter can be divided into static, dynamic and dynamic range properties [1].

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Five basic static parameters are major content of this section of this section, which are offset error, gain error, INL, DNL and monotonicity. To distinguish all values of calculations in the DAC, Xa(k) corresponds to the actual analog output for kth input code and Xi(k)

corresponds for the ideal one.

Offset Error

The analog output should be 0V for digital input=0. However, an offset exists if the analog output voltage is not equal to zero. This can be seen as a shift in the transfer curve as illustrated in Fig. 2.3.

A

na

log

O

ut

put

V

al

ue

Figure 2.3 Non-ideal transfer curve with offset error

Gain Error

Gain error is the difference at the full-scale value between the ideal and actual when the offset error has been reduced to zero. For a non-ideal transfer curve with gain error shown in

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Fig. 2.4, the gain error can be expressed as: (2 1) a i N X X GainError LSB − = − i (2.2)

Figure 2.4 Non-ideal transfer curve with gain error

Differential Non-Linearity(DNL)

The step size in the non-ideal data converter deviates from the ideal size △ and this error is called the differential nonlinearity (DNL) error. For a DAC the DNL can be defined as the difference between two adjacent analog outputs minus the ideal step size, i.e.

DNL_k = X_{a k}_, +₁−X_{a k}_, − ∆ (2.3)

The DNL is often normalized with respect to the step size to get the relative error, i.e.

DNL_k = Xa k, +1−Xa k, − ∆

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The above definitions are often most practical for DACs since the analog values can be directly measured at the output

Integral Non-Linearity (INL)

The total deviation of an analog value from the ideal value is called integral nonlinearity (INL). For non-ideal transfer function with INL and DNL errors shown in Fig. 2.5, the normalized INL can be expressed as

INL_k = Xa k, −Xi k,

∆ (2.5)

The relation between INL and DNL is given by 1 k k INL DNL_ι ι= =

∑

(2.6)

The nonlinearity errors are usually measured using a low frequency input signal to exclude dynamic errors appearing at high signal frequencies. The DNL and INL are therefore usually used to characterize the static performance.

∆ , 1 a k X + , a k X , a m X , i m X

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Monotonicity

If the analog amplitude level of the converter increases with increasing digital code, the converter is monotonic. An example of a non-monotonic DAC is shown in Fig. 2.6.

Xa Xd 1LSB Non-monotonic , a k X , 1 a k X +

Figure 2.6 A non-monotonic DAC

Monotonicity is guaranteed if the deviation from the best-fit straight line is less than half a LSB, i.e.

1 2

k

INL ≤ LSB for all k (2.7)

This implies that the DNL errors are less than one LSB , i.e.

1

k

DNL ≤ LSB for all k (2.8)

It should be noted that the above relations are sufficient to guarantee monotonicity, but it is possible to have a monotonic converter that does not meet the relations in (2.7) and (2.8).

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There are some data converters architectures that are monotonic by design, e.g. a thermometer coded DAC.

2.2.2 Dynamic Performance

In addition to the static errors that are caused by mismatch in the components in the data converter, several other error sources will appear when the input signal change rapidly. These dynamic errors are often dependent on signal frequency and increases with signal amplitude and frequency. They appear in data converter but are usually more critical in DACs since the shape of the analog wave form determines the performance.

Settling Time

The settling time is defined as the time it takes for the converter to settle within some specified amount of the final value. The primary dynamic characteristic of the DAC is the conversion speed. The setting time define the operation frequency of DAC. The factors that determine the settling time of the DAC are the gain bandwidth, slew rate of op amp and parasitic capacitor. The output of transition can be illustrated as Fig. 2.7.

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The settling can be divided in two phases, a non-linear slewing phase and a linear settling phase. The output signal of an actual DAC can not change its value instantly. The time it takes for the output to settle within a certain accuracy of the final value, for instance 0.1%, is called the settling time Ts, and determines the highest possible speed of the circuit.

The slewing phase should be as small as possible since it both increases the settling time and introduces distortion in the analog waveform. The slewing is normally caused by a too small bias current in the circuit driving the output and is therefore increased for large steps when more current is needed.

Glitch

When the switching time of different bits in binary weighted DAC is unmatched, the glitch occurs. As Fig. 2.8, if a DAC decodes 011 code to 100 code sequentially, the fast MSB changes previously than others. The output of a DAC will occur the error value. The plus effect of the output caused by different switching is called glitch.

Xa Xm Xn 011 100 101 time Aout Glitch

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2.2.3 Dynamic range

For DACs used in communications applications, the INL and DNL are not sufficient to characterize the performance. It is more convenient to characterize the performance in the frequency domain using measures as the signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR). The can be illustrated as Fig. 2.9.

Figure 2.9 Output spectrum of a DAC

Signal-to-Noise Ratio (SNR)

The signal-to-noise ratio (SNR) is the ratio of the signal power and the total noise power. SNR is usually expressed in dB as

Signal Power SNR( ) 10 log

Total Noise Power

dB = ∗ _ _

  (2.9)

Spurious Free Dynamic Range (SFDR)

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power of the largest spurious within a certain frequency band. SFDR is usually expressed in dBc as

Signal Power SFDR( c) 10 log

Largest Spurious Power

dB = ∗ _ _

  (2.10)

Total Harmonic Distortion (THD)

The total harmonic distortion (THD) is the ratio of the total harmonic distortion power and power of the fundamental in a certain frequency band, i.e.

Total Harmonic Distortion Power THD 10 log

Signal Power

 

= ∗ _ _

  (2.11)

Signal-to-Noise and Distortion Ratio (SNDR)

The signal-to-noise and distortion ratio (SNDR) is the ratio of the power of the fundamental and the total noise and distortion power within a certain frequency band, i.e.

Signal Power SNDR 10 log

Noise and Distortion Power

 

= ∗  

  (2.12)

2.3 Binary Weighted DAC Architecture

The most popular approach for realizing at least some portion of D/A converter is to combine an appropriate set of signals that are all related in a binary fashion. This binary array of signals might be currents, but binary-weighted arrays of charge are also commonly used. The binary weighted DAC utilizes a number of reference element that are binary weighted. The output signal can be written as

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(

)

₀

(

)

(

)

N-1

(

)

a 0 1 N-1

X nT =A _b nT +2 b nT +⋅ +2 ⋅b nT _ (2.13)

Where A0 is the reference and T is the update period of the DAC.

2.3.1 R-2R Ladder DAC

A very popular architecture for D/A converter uses R-2R ladders. These ladders are useful for realizing binary-weighted current with a small number of components and with a resistance ratio of only 2, independent of the number of bits, N.

The R-2R ladder can be used to obtain binary-weighted current while using only a single-size resistor. (The resistors of size 2R are made out of two resistors size R, to improve matching properties). As a result, this R-2R approach usually gives both a smaller size and a better accuracy than a binary-size approach.

A N-bit DAC that uses an R-2R ladder is shown in Fig. 2.10. For the R-2R based circuit, we see that ref V I= 2R (2.14) and N N i-1 F i-1

out F i-1 ref i

i=1 i=1 b I R b V =R =V 2 R 2      

∑

(2.15)

However, as already mentioned, although the resistance ratio has been reduced, the current ratio through the switches is still large, and thus the switch sizes are usually scaled in size to accommodate the widely varying current levels. One approach to reduce this current ratio is shown in Fig. 2.10, where equal current flow through all the switches. However, this configuration is typically slower since the internal nodes of the R-2R ladder now exhibit some

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voltage swings. -+ 2R R 2R 2R 2R R R -Vref b0 b1 bn-2 bn-1 2R RF Vout 20I 2-1I 2-N+2I 2-N+1I 20I 2-1I 2-N+2I 2-N+1I

Figure 2.10 N-bit R-2R based DAC

2.3.2 Charge Redistribution DAC

The charge redistribution DAC is a switch capacitor (SC) circuit, where the charge stored on a number of binary weighted capacitors is used to perform the conversion. Fig. 2.11 is an example of a N-bit converter. Typically, the weighted capacitors are created using a number of unit capacitors.

At time nT ( on phase ψ1 ), the bit b_i determine which of the binary weighted

capacitors that should be charged from the reference voltage,V ref . During this phase, the

plates of capacitor CNare connected to ground and virtual ground at the input of the op amp,

i.e., there is no charge on CN, and qN (nT) = 0. Capacitor CCis used for offset compensation.

The total charge on the binary weighted capacitors at time nT is given by

1 1

0 0

( ) 2 ( )

N N

l

T ref l l ref l ref

l l

q nT V C b V C b V C k nT

− −

= =

=

∑

⋅ =

∑

⋅ ⋅ = ⋅ ⋅ (2.16)

At time nT +Τ/2 , on phaseψ2 , the weighted capacitors are discharged since their plates

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charge onCNat the end of the settling is 1 ( ) ( 2) 2 N N out q nT+ T =C ⋅V nt+T (2.17)

Charge conservation gives

1

( ) ( )

2

N T

q nT+ T = −q nT (2.18)

Using (2.11) and (2.12) in (2.13) we have

( 2) ( ) out ref N C V nt T k nT V C + = ⋅ ⋅ (2.19)

The architecture in Fig. 2.6 is insensitive to offset voltage and finite gain of the amplifier. The limitations of the converter are the matching of the capacitors, the switch-on resistance, and finite bandwidth of the amplifier.

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2.3.3 Current-Mode DAC

Current-mode DACs are very similar to resistor-based converter, but are intended for higher-speed applications. The basic idea is to switch currents to either the output or to ground, as shown in Fig. 2.12.

Figure2.12 N-bit binary-weighted current-mode DAC

Here, the output current is converted to a voltage through the use of Rf, and the upper

portion of each current source always remains at ground potential.

The technology of usable switched-current of the current-mode is gone to realize. The switched-current technique is a natural choice in a CMOS process, since reference and sum element as well as switches are relatively easy to implement. The current-steering DAC has the advantage of being quite small for resolution below 10 bits and it is very fast. The major disadvantage is the sensitivity to device mismatch, glitches, and current source output impedance for higher number of bits. Another good property of the current-steering DAC is that its high power-efficiency since all power is directed to the output. The current-steering DAC is suitable for high-speed high-resolution applications, especially when special care is taken to improve the matching of the converter.

To achieve monotonicity, reduce the influence of glitches and reduce the sensitivity to matching errors, the DAC should be segmented into a coarse and fine part. The coarse part is

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realized by thermometer coded and fine part is kept binary weighted. This is referred to as a segmented converter and is discussed further.

2.4 Thermometer Coded DAC Architecture

The thermometer coded DAC architecture utilizes a number of equally weighted elements. The binary input code is encoded into a thermometer code as illustrated in Table 2-1 for 3-bit input code. Generally, with N binary bits, we have M=2N-1 thermometer coded

bits. The analog output at time nT is give by

M

a 0 i

i=1

X =A ⋅

∑

C (nT) (2.20)

where C = nT_i

(

) { }

∈ 0,1 ,1 i≤ ≤M are the thermometer coded bits.

Decimal Binary Thermometer

0 000 0000000 1 001 0000001 2 010 0000011 3 011 0000111 4 100 0001111 5 101 0011111 6 110 0111111 7 111 1111111

Table 2-1 Decimal, binary, thermometer code representations.

In the thermometer code DAC the reference element are all equally large and the matching of the individual element becomes simpler than for the binary case. The total sum of all weights is 2N-1. The transfer function of the thermometer code converter is monotonic and

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matching are also relaxed. In fast, if the matching is within a 50% margin, the converter is still mon0tonic.

Figure 2.13 A thermometer coded current-steering DAC with encoding circuit

In Fig. 2-13 we show a current-steering implementation of a thermometer coded DAC with binary-to-thermometer encoder. All current sources are equally large, Iunit. For a large

number of bits, the digital circuit converting the binary code (X) into thermometer code (C) and the number of interconnecting wires become large, since the number of outputs is growing exponentially. This implies a more complex circuit layout. The encoding circuit can easily be pipelined and the propagation time through the encoder can be controlled.

2.5 Hybrid DAC Architecture

Combining the techniques discussed in Fig. 2-14 for realizing different portions of a D/A converter result in hybrid designs. Hybrid designs are an extremely popular approach for designing converters because they combine the advantages of binary-weighted and thermometer-coded architectures. For example, it is quite common to use a thermometer-code approach for the top few MSBs while using a binary-scaled technique for the lower LSBs. In this way, glitch is significantly reduced and accuracy is high for the MSB where it is needed

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most. However, in the LSBs where glitch and accuracy requirements are much reduced, valuable circuit area is saved with a binary-scaled approach.

Figure 2-14 A N-bit segmented DAC where M MSBs are thermometer-code

2.6 Summary

In this chapter, the fundamental of the digital-to-analog Converters (DACs) is presented first. The performance parameters used to characterize the specifications of DAC is also described. Also, different types of Nyquist-Rate DACs are introduced.

According to the discussions of the advantages and disadvantages for different type DACs, we can choose the suitable architecture for our applications among several trades-off, like power consumption, speed, and die area.

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Chapter3

System Analysis of DAC Design

Current-steering DAC is a popular topology when high speed and high resolution is needed since it can drive resistive loads directly, and do not require high speed amplifiers at the output. A differential output type current steering DAC is preferred because it can lower the common mode noise and second harmonic distortion. But it still has some non-idealities that will degrade the performance of the DAC. The errors sources that cause the non-idealities include finite output impedance effect, current source mismatch, timing non-idealities and non-idealities due to switching the current cells [1].

3.1 Major Error Sources in Current-steering DACs

Output impedance of current source:

The finite output resistance affects the linearity of the converter. This is primarily due to the fact that the output resistance of the converters is signal-dependent. We often use the cascsde structure to increase the output impedance of current source.

Matching errors:

Matching errors in the process cause the oxide thickness and threshold voltage, to vary, the unit currents are unequal, which also affects the linearity. The matching errors are of both stochastic and deterministic nature.

Doping and thermal gradients:

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currents are unequal, which also affects the linearity. This error is often overcome by using the careful unit-cell placement.

Edge effects:

Edge mismatch error occurs when the element does not see the same surroundings within a certain radius around them. This error is often eliminated by placing a number of dummy rows and columns around current source arrays and the external cost is the area of dummy current source.

Increased Random Noise:

An increase in the noise floor in the signal band reduces the dynamic range of the converter. Sources of random noise include the thermal noise of transistors and resistors and the coupling of noise from digital circuitry into the analog circuits through the common substrate, package, and supply lines.

Harmonic Distortion:

Signal-dependent non-idealities result in harmonic distortion in the DAC output. Ideally, even harmonics are completely cancelled through the use of a differential topology, but mismatch between the differential paths results in some residual even-harmonic distortion. In the following section, we discuss the non-idealities of current-steering DAC and the effects they will cause on both static performance and spectrum specification.

3.2 Finite output impedance of current source

The output impedance and the parasitic impedance of interconnections and switches in the converter will strongly influence the performance. Any non-ideal current source has a finite output resistance and can be modeled [1].

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Fig. 3.1 shows a current-steering array including output impedance of each current source. It is a thermometer coded structure, where Ro represents the output impedance of each

Figure 3.1 Current sources with finite output impendence

current source. For the thermometer code of height N, the actual output voltage is

0 out,N L R V =NI R N       (3-1)

therefore the ideal output voltage for height j is

0 out,j L R V =jI R N       (3-2)

The difference between the ideal and actual voltage can result in INL error

(

)

2 L o L o L j o L o L o R R R R IR INL =jI - = j N-j R +jR R +NR R       (3-3)

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output impedance. From the figure we can find that INL decreased when the current source impedance increases. Also, the maximum INL value occurs when the middle digital input is applied.

Figure 3.2 The INL Profile of 12-bit DAC with different current source output impedance

Besides of static linearity, the finite output impedance of the current sources also has relation with dynamic performance. The SFDR is an index between dynamic performance and output impedance. The equation of SFDR can be calculated as

2 dc dc ac ac 1+ K 1+ K SFDR= + -1 K K ρ ρ ρ ρ   _ _   _ _          _ _   i i i i (3-4) where N L ac dc o R 2 -1 K =K = , = 2 ρ R (3-5)

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In general, output impedance of current source is farther great than output loading. When ρ is very high, the approximate equation can be written as

(

)

1 SFDR 40log -12 N-2 dBc ρ   ≈ _ _   (3-6)

Figure 3.3 shows another example how the output impedance affects the SFDR for differential output. This implies the output impedance of unit current source must be larger than 3MΩ if the SFDR is guaranteed to larger than 72dB.

Figure 3.3 Simulate SFDR in different output-impedance conditions

3.3 Current Source Mismatch

Intrinsic high linearity can be achieved by tacking all possible systematic, graded, and random errors. Important effects that must be taken are

1. Random errors: device mismatches.

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thermal gradients, doping gradients, and oxide thickness gradients resulting in a Vt

shift across in the die.

In Fig3.4 show the average simulated and calculated SFDR for 12-b DAC with 8MSB thermometer-coded that have different mismatch pattern. Specifically input signal was formed by adding dither to the signal where amplitude is full swing, the ratio of the input signal frequency Fin to clock frequency Fclk is 1/4, and then quantizing the result to the resolution of

DACs. The dither added to the sinusoidal input, was a while sequence with a triangular probability density function supported on, so the quantization error was white noise[15]. The curves are saturated at low mismatch, since in the simulations the harmonics are hidden in the noise floor.

Figure 3.4 The average simulated and calculated SFDR for a 12-bit DAC with 8MSB thermometer-coded that have different mismatch pattern

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MOS transistors. Consider two normally identical current sources and random mismatch between two identical devices as shown in Fig. 3.5. The output currents I1 and I2 exhibit

mismatch components due to mismatch between transistors M1 and M2. The nominally

identical devices suffer from a finite mismatch due to uncertainties in each step of the manufacturing process. For example, the gate dimensions of MOSFETs suffer from random, microscopic variations and hence mismatches between the equivalent lengths and widths are laid out [19]. BIAS I1 M1 M2 BIAS

M

1

M

2 I2

Figure 3.5 Identical MOS current sources and random mismatch between two identical devices

For Fig. 3.4, assume M1 and M2 are nominally identical and have square-law I-V

characteristics：

(

)

2 1 2 D ox GS T W I C V V L µ = − (3.7)

Usually we increase W, L, and VGS to lower the mismatch in the drain current.

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larger L requires higher VGS-VT to attain a given ID, and increasing VGS-VT limits the voltage

swing at the drain of M1 and M2. As a consequence, some compromise is usually necessary to

obtain a reasonable combination of accuracy, speed, and output voltage swing.

In order to reduce to effect of current mismatch, proper dimensions of current sources should be chosen. An estimation of the minimum channel area of transistor versus mismatch parameters are described as follow [13]：

(

)

2

1 2

D GS T

I = β V −V (3.8)

Where β=µCox(W/L), the relative current mismatch is

(

)

2 2 2 2 ( ) 4 T GS T V I I V V σ β σ σ β   _∆ ∆ ∆   = _ _+       ₋ (3.9)

According to [6], the minimum size of current source is equal to

(

)

(

)

2 2 2 2 min 4 1 2 VT GS T I A A V V WL I β σ   +   −     =       (3.10) Where 2 ( ) A WL β β σ β ∆ = (3.11)

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2 ( ) VT T A V WL σ ∆ = (3.12)

The parameter AVT and Aβ are technology parameter, depended on the given process.

From (3-10), we can see that the minimum area of the current source, (WL)min , is function of

overdrive voltage, (VGS-VT) , and the current mismatch standard deviation (σI /I ). By

increasing the overdrive voltage, and minimum area required for current source can be decreased.

Fig 3.6 shows the required gate-area of the unit current source transistor as function of (VGS-VT). By increasing the (VGS-VT), the minimum area required can be decreased. For very

large values, however, the mismatch is mainly determined by the Aβ term and barely decrease

with the (VGS-VT). Consequently, a convenient criterion to determine the gate overdrive

voltage of the current source transistor is to make the two mismatch contributing terms in about equal.

Figure 3.6 Minimum gate-area of the unit current source transistor as function of the gate voltage overdrive

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Systematic and graded errors have become an important concern in high-resolution converters. Major sources of gradient error are oxide thickness and dopant variation. These parameters vary smoothly enough that they could be considered linear over the active area of D/A converter. Systematic and graded errors result from parameter variations, such as temperature generated within the active area of the converter.

If the resolution of the DAC increases by a single bit, the number of current-source array doubles. The area occupied by a single unity current source also doubles because of random matching constraint. This leads to a four times area increase for the current source array for each additional bit. For DAC with a resolution of 10-bit and higher, the dimension of the current source array become so large that process, temperature, and electrical gradients have to be considered. The nonlinearity errors introduced by these gradients can be partially compensated by the introduction of a special switching scheme. We only focus on the error source here.

The current error caused by the voltage drop in the ground lines is given by [8]

2 0 1 cosh( ) ( ) sinh( ) m gnd voltage drop m gnd m gnd g R x i x g R a a x g R = ≈ + +… (3.13)

where x is the coordinate of the current source along the ground line.

It is well know that wafers exhibit, in general, a radial pattern in the oxide thickness. This gives rise to a shift in the nominal values of the current sources approximately linear with the devices separation distance. On the other hand, temperature gradients and stress gradients are responsible for errors approximately parabolic across the array matrix.

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series expansion around the center of the current source array.

2 2

, , ( , ) 0 1 2 3 4 5

thermal technology

i x y =b +b x b y+ +b xy+b x +b y + (3.14)

where (x,y) is the coordinate of the unit in the current source array.

The current source array thus contains units with errors that are (to first order) linear and (to second order) quadratic in spatial distribution. These linear and quadratic error profiles are shown in Fig. 3.7.

Figure 3.7 (a) Linear error (first-order error) (b) Systematic error (Second-order error) In DAC current element

The edge effect means current matching error at the edge of the current source array as shown in Fig. 3.8. It can be avoided by placing sufficient rows and columns of dummy current cells at the edges.

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Active cell _{Dummy cell}

Figure 3.8 Current cell matrix with dummy cell

3.4 Switched Gate Driver

The differential output switch pair (M3, M4; Fig. 3.9(a)) could be driven directly with full supply rail swing outputs of the CMOS logic. This would be the lowest power solution. However, it is well known that for the best SFDR performance, the crossing point for the gate drive signals of the output current switch pair needs to be optimized [16]. The circuit that drives the differential switch should ensure that both switches are never completely off at the same time so that the current from the current source is always flowing at a constant value. This minimizes the excursion of the voltage on the switch common source node, Ci, during a

transition. Any current lost to parasitic capacitor Ca causes nonlinearity. The disturbance on Ci

should be symmetric around the nominal DC value. To the extent that the disturbance cannot be completely eliminated it is important that Ca be minimized. It is also important to note that

it is not necessary to bring the gates of the switch devices any higher than the voltage on the common source node Ci, when turning off the device (Vgs=0). Limiting the swing in this way

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node.

These circuits have been proposed that limit the voltage fluctuation, by ensuring that the two switching transistors are never simultaneously switched off. This design criterion turns out to have an important positive impact on the dynamic characteristics of the DAC because any asymmetry in the output lines of each current cell give rise to a glitch at the DAC output during a code transition. The correct timing of the switching control signals is thus of crucial importance because it reduces simultaneously the voltage swing at the internal nodes and the amplitude of the glitch.

Figure 3.9 The Output waveforms of switch drivers used for driving the current cell. (a) Output switch gate waveforms (b) High crossing points due to use the driver of intrinsic

delay (c) Middle crossing points (d) Low crossing points due to use the driver of intrinsic delay (e) Low crossing points due to use the driver of rise / fall time

This circuit put one switching transistor at the threshold of conducting by lowering the crossing point of the switching control signals, so that as soon as one of the switching transistors begins to switch off, the complementary switching transistor begins to switch on. Two different alternatives have been proposed: (1) circuits the use different rise/fall times [23] and (2) circuits that introduce a delay in one of the transitions [6] [8]. Both classes of circuits

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have a high switching speed. Fig. 3.9 shows the waveform of crossing point of the switching driver. Fig. 3.9 (b) show the high crossing points that both the switching transistors turn on at the time of transition for using the driver of intrinsic delay. Fig. 3.9 (c) shows the middle crossing point that both the switching transistors may be off at the same time. Fig. 3.8 (d), (e) show the low crossing points that both the switching transistors turn on at the time of transition for using different types of switching drivers, as mentioned above.

3.5 Random routing

A major error source of DAC nonlinearity is the current source mismatch due to process and environmental variations, which includes random, gradient and quadratic errors. The gradient and quadratic errors can be effectively compensated by optimizing switching schemes or using local biasing techniques [5]. The random variation of current source are determined by the inherent properties of the technology used and can be assumed to independent from each other and follow normal distribution.

Binary Thermometer Encoder Thermo Coded DAC Randomizer Binary Code Thermometer Code Random Thermometer Code N bit 2N-1 bit 2N-1 bit output

Figure 3.10 Randomization of bits in a thermometer coded DAC. The matching error becomes uncorrelated with the signal.

In a conventional thermometer code DAC, the input number (M), is represented by using 2M fixed reference element in the DAC. The matching errors become strongly

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distortion, the binary to thermometer encoder can be designed so that, at different times, different reference are chosen to represent M, we do not fix a reference to a certain code. If we choose the references in a way that is uncorrelated with the signal, the matching errors will no longer be signal dependent and hence the error will become noise. This is achieved by using a randomizer or scrambler as illustrated in Fig 3.10. In a real implementation the randomization can be implemented with a random generator. We can also choose to assign the references I a cyclic way, which does not give a completely uncorrelated error signal, but the improvement can be significant.

We can create MUX of L-bit input and L-bit output, hence the MUX utilizes selection to control L-way. There are MUX between local decoders and switch element. Fig. 3.11 shows a 2M-1 bit randomizer receiving at random generator controls. The random generator controls the

selection of the element in the MSB part so that the harmonics caused by mismatch can be attenuated. A perfect synchronization of the control signals at the DAC, so the random generator is controlled with the clock, thus well-designed synchronized driver is used in entire circuit.

To illustrate dynamic randomization, we show in Fig. 3.12 a simulation result where a full-scale sinusoid has been applied to a 12-bit DAC with 8MSB thermometer-coded D/A converter. To all current sources in the DAC a Gaussian distributed random error with standard deviation equal to 10% is applied. In Fig 3.12(a) we find clear distortion terms and in (b) the distortion has been reduced and the noise floor has increase. The SFDR is in both cases approximately 7dB.

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mux clk Local decode Local decode

Figure 3.11 A 2M-1 bit randomizer receiving at random generator controls

Figure 3.12 Output amplitude spectrums from a 12-bit DAC with 8MSB thermometer-coded DAC (a) without randomization and (b) with randomization

As is evident from the numerous spurs distributed across the spectrum in Fig. 3.12(a), rather severe harmonic distortion results from the static DAC-element errors in the absence of

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random switching. The maximum-amplitude spur occurs at a frequency of approximately 1.5π rad, and has power 82.5 dB below the power of the desired sinusoidal signal of frequency ω0

numerous additional simulations performed by the authors show that the DAC exhibits similar behavior when driven by inputs of different frequencies. It follows that merely 82.5 dB of SFDR is provided. The data in Fig. 3.12(b) indicates that harmonic distortion is not visible with full randomization DEM. As demonstrated by the simulation results and confirmed in the following section, the DAC easily provides 90 dB of SFDR.

3.6 Summary

In this chapter, we determine the proper output impedance, variance, and the size of current source. We invent a simple random structure to correct the mismatch error of current source. In order to design a high-speed and high-resolution current steering DAC, we should pay more attention to these non-idealities. The approaches to improve the non-idealities are also mentioned in this chapter.

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Chapter4

Circuit Design of DAC

In this chapter, the designed architecture of a 12-bit 250-MSamples/s current–steering CMOS D/A converter with the partial random element matching is introduced at first. Then each block of the DAC is presented and the circuit design is discussed. To design a high speed and high resolution DAC, we should pay more attentions to choose the proper architecture that can achieve a balance between good static and dynamic specifications versus a reasonable circuit power, area, and complexity. Besides, special layout technique is also presented to compensate the systematic and gradient errors, as mentioned in chapter 3.

4.1 The System Structure of DAC

The architecture of a 12-bit 250-MSamples/s current–steering CMOS D/A converter with the partial random element matching presented in this thesis is shown in Fig. 4.1. There are several blocks in this DAC, including digital circuits, randomizer, latches, current cells, and bias circuit. The input binary codes are either processed through digital circuits, then changed to thermometer codes (B11 – B4) or simply equally delayed (B3 – B0). The processed

signals then pass through the latches to keep synchronization used for driving switches of the current cells. In addition to synchronization, the latches can also reduce the glitch effect due to the drain voltage fluctuations of current sources. Finally, the current cell matrix can provide differential output currents controlled by the switches whose input signals have been synchronized. In the following, all the sub-circuitry of this DAC will be further discussed.

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Fig. 4.1 12-bit DAC architecture

Fig. 4.2 presents the block diagram of the DAC architecture. The DAC has a 4+8 segmented architecture: first, the eight most significant bits are linearly decoded with random element matching; second, the four least significant bits are also binary weighted.

The matrix that implements the 8 MSB’s is logically seen as being composed of four identical 8-bit unit elements DAC’s, connected in parallel. In two of the four unit element DAC’s, a two-stage row-column decoding logic and a randomizer, is implemented. The connection in parallel of four unit current sources provides the correct current scaling of the 8 MSB’s relative to the four binary bits.

The remaining 4 LSB’s select directly four binary weighted current sources. Note that that by removing the 4 LSB’s from this architecture, one obtains also a very interesting architecture for an 8-bit resolution DAC, but with 12-bit accuracy.

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Iout Iout

Figure 4.2 Simplified block diagram of the DAC architecture

4.2 Digital Circuits

In a segmented current-steering DAC, the function of the digital circuits it to convert the binary code to either thermometer code or only delayed the binary code and the digital circuit of randomizer structure and high-speed latch. To design the digital circuits, several issues should be taken into account:

High speed operation Circuit complexity Power consumption

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4.2.1 Thermometer decoder

Discrete quantities of information are represented in digital system by binary codes. A binary code of n bits is capable of representing up to 2n distinct element of coded information.

A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. If the n-bit coded information has unused combinations,

the decoder may have fewer than 2n outputs.

Binary-to-thermometer decoder accomplishes the equivalence of elements from binary code. The Tab. 4.1 shows truth table of a 4-to-16 line decoder. The circuit of the 4-to-16 bits binary-to-thermometer decoder will be realized. Finally, the Boolean function between the binary-input and thermometer-output are described in tab. 4.2.

Decimal d c b a A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15

Imperfect synchronization of the control signals at the switches.

Drain-voltage variations of the current-source transistors caused by the fact that both switch transistors are simultaneously in the off state.

Coupling of the control signals through the Cgd of the switches to the output.

To minimize the three effects, a well-designed synchronized driver is used. The high speed, low glitch latch is illustrated in Fig. 4.5(a). It provides two complementary signals needed at the input of the current switches.

In the conventional latch, both switches will be off for a short period. As a result, the capacitance at the drain of the current source transistor will be charged and then the current source will turn off. To recover the normal operation, the current source must progress through the linear region and back into saturation. Hence, turning off the current source not

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only slows down the speed but also increases glitch at the output. To solve the problem, the function of this latch is designed to shift down the crossing point of the differential signals used for driving the switches of the current cell.

The latch used here is a rise/fall time based driver. In order to obtain instantaneous change for output node with falling input, extra PMOS transistors (M1 and M2) are placed in parallel with each other cross-coupled at the top of the circuit. When the transitions of input signals (high low or low high) occur, the transistors M3-M10 will immediately change their states. However, the crossed-coupled PMOS transistors M1 and M2 will hold their states for a short period. After these transistors change their states, the charging speed will be increased. Thus, the combination of the (µn / µp) scaled PMOS transistors and the PMOS

positive feedback loop results in the rise time that is much faster than the fall time of the driver circuit. Due to the use of two additional inverters at the output of the driver and properly sizing the transistors of the whole latch, a lower crossing point can be realized. Fig. 2 (b) shows the voltage waveforms of the differential outputs, Q and Q . This latch not only performs the final synchronization of the signals used for switching different current cells but also reduces the delay between the different digital decoders.

D CK

D

Q Q

具有部分隨機匹配的12位元250百萬赫芝電流式互補式金氧化半導體數位類比轉換器

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電機學院 IC 設計產業研發碩士班

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具有部分隨機匹配的 12 位元 250 百萬赫芝電流式互補式

金氧化半導體數位類比轉換器

12-bit 250MSample/s Current-Steering CMOS D/A

Converters with Partial Random Element Matching

研 究 生：白逸維

指導教授：洪崇智 教授

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具有部分隨機匹配的 12 位元 250 百萬赫芝電流式互補式

金氧化半導體數位類比轉換器

12-bit 250MSample/s Current-Steering CMOS D/A

Converters with Partial Random Element Matching

研 究 生：白逸維 Student：Yi-Wei Pai

指導教授：洪崇智 Advisor：Chung-Chih Hung

研究生：白逸維

指導教授：洪崇智教授

研究生：白逸維 Student：Yi-Wei Pai

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學生：白逸維指導教授：洪崇智博士