Chapter 5. Simulation and Measurement Results
5.3 Measurement Results
The sample rate is set to 100 MHz at input frequency 2 MHz, 5.17 MHz, 12.83 MHz, 20.67 MHz and 29.15 MHz, respectively. A measured sine wave spectrum for Fs = 20 MHz and Fsig = 1 MHz is shown in Fig. 5.9. A measured sine wave spectrum for Fs = 100 MHz and Fsig = 2 MHz and 9.8758 MHz is shown in Fig. 5.10 and Fig.
5.11. A measured sine wave spectrum for Fs = 200 MHz and Fsig = 19.81 MHz is shown in Fig. 5.12. Fig. 5.13 shows the SFDR of input frequency between 2 MHz and 29.15 MHz at the sample rate 100 MHz. The differential nonlinearity (DNL) and integral nonlinearity (INL) are shown in the Fig 5.13. The total measured result of this DAC is summarized in Table 5-2 and the die microphotograph is shown in Fig. 5.14.
Figure.5.9 Sine wave spectrum for Fs = 20 MHz and Fsig = 1 MHz
Figure.5.10 Sine wave spectrum for Fs = 100 MHz and Fsig = 2 MHz
Figure.5.11 Sine wave spectrum for Fs = 100 MHz and Fsig = 9.8758 MHz
Figure.5.12 Sine wave spectrum for Fs = 200 MHz and Fsig = 19.81 MHz
Figure 5.13 The SFDR of input frequency between 3 MHz and 34.33 MHz at the sample rate100 MHz
Figure 5.14 The differential nonlinearity (DNL) and integral nonlinearity (INL)
Figure 5.15 The die microphotograph
Table 5-2 The total measurement results of this DAC
Process
TSMC 0.18 µm CMOS Mixed-Signal
Supply Voltage
Digital supply 1.8V Analog supply 3.3V
Sampling Frequency 100 MHz
DNL < 5 LSB
INL < 9 LSB
SFDR(Fin = 2 MHz) 46 dB @ CLK = 100 MHz
Power Dissipation 125 mW
Active Area 1.778 mm2
Chapter6
Conclusions and Future Work
In this thesis, the 12-bit 250-MHz DAC is implementation. We propose a new simple random structure and special layout to improve the static and dynamic linearity.
The current source is properly designed to reduce the nonlinearity caused by finite output impedance of current source. To overcome the random error and systematic error, the proper area of current source is selected and special layout technique is used.
A high speed, low crossing point latch is implemented to compensate the error at the DAC output due to switching in the current cells. The DAC is fabricated by 0.18µm 1P6M CMOS Mixed-Signal. Besides, the power dissipation is 125mW. The measure resultant of a 12-bit current-steering D/A converter without the partial random element matching shows that the signal frequency of 9.87 MHz at the update rate of 100 MHz, the SFDR is 37 dB. The differential nonlinearity and integral nonlinearity are below 5 and 9 least significant bits (LSB’s).
The DAC can be improved from several points of view in the future. First, due to lack of considering the parasitic loading effect caused by the layout, the post-layout dynamic performance simulation results will be degraded than the pre-layout simulation at high input frequency. Therefore, the DAC should be designed to keep enough margins to endure the loading effect and the floor plan should be modified to decrease the parasitic loading. Second, after passing through multi-bit registers to sample the input digital data, the MSBs and LSBs are binary-weighted. Third, the clock should be designed carefully because the current DAC operated at high speed.
And pay more attention to routing between circuit block. Finally, we can propose a calibration structure to improve the matching accuracy of the current sources is applied for high-resolution DACs. Because of the lower matching requirement of the current sources, the chip area is smaller and the cost is lower, too.
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